复旦计算机08级2010春季期末考试试题A

复旦大学计算机科学技术学院《计算机原理》期末考试试卷A卷共 13页课程代码：INFO130054.01-02 _考试形式：开卷2010年6月（本试卷答卷时间为100分钟，答案必须写在答卷上，做在试卷上无效）专业学号姓名成绩Problem 1.Number Conversion: IEEE 754 single precision 32-bit float standard representation with a little change is illustrated below.Normalized: (-1)sign * (1.fraction) * 2exponent-127(exp=1 to 254)Denormalized: (-1)sign * (0.fraction) * 2-126(when exp=0, fraction≠0)Zero: all 0’s in all 3 fields1)Convert the number -35.390625 into this changed IEEE 754 FP single precisionrepresentation (in hex).(-35.390625)10= (0x )1612)With changed 32-bit float representation, what is the equivalent value as adecimal number?A: (0011 1111 0001 0000 0000 0000 0000 0000)2B: (0000 0000 0011 0101 0000 0000 0000 0000)23)Calculate the sum of (35.390625)10 and (0011 1111 0001 0000 0000 0000 00000000)2using changed 32-bit float representation, and then round the sum (in binary number value, e.g. (1000.11)2for (8.75)10 ) to 4 bits to the right of the binary point by both round-up and round-down. Give your steps detailed.4)Given three numbers f1, f2 and f3 of this changed 32-bit representation, none ofthem equals +∞, -∞or NaN, and x is signed 32-complement representation.Please tell whether two C expressions below are always true. If yes, give the reason in detail; If no, give a counterexample and show the detail computation steps to get false.A: x = = (int) (float) x;B: (f1 > f2) = = ((f1 + f3) > (f2 + f3))2Problem 2.Please read the following C code and assembly code and then fill in the blanks.The assembly code:3Please give the reason for the blanks you filled in the assembly code and the result of the printf in main function.45Problem 3.The following figure illustrates a five stage pipeline processor similar to that in your text book (Figure 4.53, Page 334 in English Book). Notice there are three differencesfor this architecture from that in your book.First difference is that Function Units in Stage E become multi-cycle function units. Now stage E contains three function units, two Adder and one Subtracter. The Subtracter can only handle subtraction operations and takes 3 cycles to completion. The Adder can handle other calculation exception subtraction and takes 2 cycles to completion. Notice one Adder or Substracter can handle only one instruction at a time, that is, other instructions must wait in its Stage D until the expected Adder or Substracter is free.Second difference is that Memory Units will consume different cycle to complete a memory access. For a cache hit , it takes 1 cycle; for a cache miss , it takes 6 cycles; for a non-memory instruction , it takes 1 cycle to pass Stage M. And only one instruction can occupy the memory units, that is, if two memory instructions are entering the Stage M at the same time, the second instruction will wait the first instruction to complete before retrieve its own memory data.Third difference is that this architecture is 2-issue in-order pipeline processor. It means the fetch stage can fetch at most two instructions and all the state registers between stages can also store at most two instructions’ states. The fetch units will fetch as many instructions as possible to fill the state registers between Stage F and Stage D.61) This problem is based on the code in figure, which will be executed on theprocessor described above. Assume in cycle 0, no instruction is executed, and in cycle 1, the first two instructions are fetched. Fill in the blanks. (Stage: F , D , E , M , W , finished or not fetched , undecidable value marked with “--”) (10’)2)The cache miss in the above code cause the CPU to waste several cycles, becausethe next instruction depends on the value fetched by the cache miss instruction. So, we have a technical called “code motion” which changes the order of instructions so that the time used to load the data from memory can be hidden by the instructions do not use memory and do not depends on the memory instruction.Use this technology to optimize the original code in figure to get least execution time and write you code down.3)How many cycles are saved from this optimization?___[1]___4)The last instruction in this optimized instruction flow will exit its write-backstage in Cycle___[2]___7Problem 4.Implement the following 2 functions and make their functionalities be the same with the description. The coding rules are also same as Lab1. (If you think there is nothing t o do, just fill the blank with “--”)1)bitOr (10‟ + 2‟)2)logicalShift (2‟ * 6)8Problem 5.A computer has main memory(MM) with 256K words size, and a 8K words set associative cache. Each set of cache has 4 pages with 64 words in each page. Suppose the cache is initially empty. CPU read data from MM at the address of 0, 1, 2, …, 8447(When read misses in cache, the full page containing destination bytes is written into the cache first and read from the cache). This reading process repeats for 20 times. We know that cache access time is 10% of that of MM. LRU replacement policy is used on cache. Please figure out how many times the total reading operations will be faster using cache compared with no cache? You must write out complete steps with necessary descriptions.Problem 6.You are given the following definitions:Assume the following:•sizeof(int) == 4.•sq begins at memory address 0.•The machine has a 2048-byte direct-mapped data cache with 32-byte blocks.•The cache is initially empty.•The only memory accesses are to the entries of the array sq. Variables i and j are stored in registers.9Determine the cache performance of the following code:1)What is the total number of writes?2)What is the total number of writes that miss the cache?Given the above assumptions, determine the cache performance of the following code:3)What is the total number of writes?4)What is the total number of writes that miss the cache1011Problem 7.Virtual Address TranslationWe consider a virtual address system with the following parameters.• The memory is byte addressable. • Virtual addresses are 20 bits wide. • Physical addresses are 16 bits wide. • The page size is 4096 bytes.• The TLB is 4-way set associative with 16 total entries.In the following tables, all numbers are given in hexadecimal. The contents of the TLB and the page table for the first 16 virtual pages are as follows. If a VPN is not listed in the page table, assume it generates a page fault.1) In the four rows below, mark the bits that constitute the indicated part of thevirtual address with an X . Leave the remaining bits of each row blank.122)For the virtual address 0x7E37C, indicate the physical address and various resultsof the translation. If there is a page fault, enter “—” for the PPN and Physical Address. All answers should be given in hexadecimal.3)For the virtual address 0x16A48, indicate the physical address and various resultsof the translation. If there is a page fault, enter “—” for the PPN and Physical Address. All answers should be given in hexadecimal.13复旦大学计算机科学技术学院《计算机原理》期末考试答题纸A卷课程代码：INFO130054.01-02 _考试形式：开卷2010年6月（本试卷答卷时间为100分钟，答案必须写在答卷上，做在试卷上无效）专业学号姓名成绩Problem 1.14Problem 2.15Problem 3.16Problem 4.17Problem 5.18Problem 6.19Problem 7.20。