MM74C923中文资料

TL F 6037MM54C922 MM74C92216-Key Encoder MM54C923 MM74C92320-Key EncoderJuly 1993MM54C922 MM74C92216-Key Encoder MM54C923 MM74C92320-Key EncoderGeneral DescriptionThese CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches The keyboard scan can be implemented by either an external clock or external capacitor These encoders also have on-chip pull-up devices which permit switches with up to 50k X on resist-ance to be used No diodes in the switch array are needed to eliminate ghost switches The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor A Data Available output goes to a high level when a valid keyboard entry has been made The Data Available output returns to a low level when the en-tered key is released even if another key is depressed The Data Available will return high to indicate acceptance of the new key after a normal debounce period this two-key roll-over is provided between any two switchesAn internal register remembers the last key pressed even after the key is released The TRI-STATE outputs provide for easy expansion and bus operation and are LPTTL com-patibleFeaturesY 50k X maximum switch on resistance Y On or off chip clockY On-chip row pull-up devices Y 2key roll-overY Keybounce elimination with single capacitor Y Last key register at outputsY TRI-STATE outpust LPTTL compatible Y Wide supply range3V to 15VYLow power consumptionConnection DiagramsPin Assignment for Dual-In-Line PackageTL F 6037–1Top ViewOrder Number MM54C922orMM74C922Pin Assignmentfor SOICTL F 6037–14Top ViewOrder Number MM74C922Pin Assignment for DIP and SOIC PackageTL F 6037–2Top ViewOrder Number MM54C923orMM74C923TRI-STATE is a registered trademark of National Semiconductor Corporation C 1995National Semiconductor CorporationRRD-B30M105 Printed in U S AAbsolute Maximum Ratings(Note1)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin V CC b0 3V to V CC a0 3V Operating Temperature RangeMM54C922 MM54C923b55 C to a125 C MM74C922 MM74C923b40 C to a85 C Storage Temperature Range b65 C to a150 C Power Dissipation(P D)Dual-In-Line700mW Small Outline500mW Operating V CC Range3V to15V V CC18V Lead Temperature(Soldering 10seconds)260 CDC Electrical Characteristics Min Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max UnitsCMOS TO CMOSV T a Positive-Going Threshold Voltage V CC e5V I IN t0 7mA3 03 64 3V at Osc and KBM Inputs V CC e10V I IN t1 4mA6 06 88 6VV CC e15V I IN t2 1mA9 01012 9V V T b Negative-Going Threshold Voltage V CC e5V I IN t0 7mA0 71 42 0V at Osc and KBM Inputs V CC e10V I IN t1 4mA1 43 24 0VV CC e15V I IN t2 1mA2 156 0V V IN(1)Logical‘‘1’’Input Voltage V CC e5V3 54 5V Except Osc and KBM Inputs V CC e10V8 09VV CC e15V12 513 5V V IN(0)Logical‘‘0’’Input Voltage V CC e5V0 51 5V Except Osc and KBM Inputs V CC e10V12VV CC e15V1 52 5V I rp Row Pull-Up Current at Y1 Y2 V CC e5V V IN e0 1V CC b2b5m AY3 Y4and Y5Inputs V CC e10V b10b20m AV CC e15V b22b45m A V OUT(1)Logical‘‘1’’Output Voltage V CC e5V I O e b10m A4 5VV CC e10V I O e b10m A9VV CC e15V I O e b10m A13 5V V OUT(0)Logical‘‘0’’Output Voltage V CC e5V I O e10m A0 5VV CC e10V I O e10m A1VV CC e15V I O e10m A1 5V R on Column‘‘ON’’Resistance at V CC e5V V O e0 5V5001400X X1 X2 X3and X4Outputs V CC e10V V O e1V300700XV CC e15V V O e1 5V200500X I CC Supply Current V CC e5V0 551 1mAOsc at0V (one Y low)V CC e10V1 11 9mAV CC e15V1 72 6mAI IN(1)Logical‘‘1’’Input Current V CC e15V V IN e15V0 0051 0m Aat Output EnableI IN(0)Logical‘‘0’’Input Current V CC e15V V IN e0V b1 0b0 005m Aat Output EnableCMOS LPTTL INTERFACEV IN(1)Logical‘‘1’’Input Voltage 54C V CC e4 5V V CC b1 5V Except Osc and KBM Inputs74C V CC e4 75V V CC b1 5V V IN(0)Logical‘‘0’’Input Voltage 54C V CC e4 5V0 8V Except Osc and KBM Inputs74C V CC e4 75V0 8VV OUT(1)Logical‘‘1’’Output Voltage54C V CC e4 5V2 4VI O e b360m A74C V CC e4 75V2 4VI O e b360m AV OUT(0)Logical‘‘0’’Output Voltage54C V CC e4 5V0 4VI O e b360m A74C V CC e4 75V0 4VI O e b360m ANote1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation2DC Electrical CharacteristicsMin Max limits apply across temperature range unless otherwise specified (Continued)Symbol Parameter ConditionsMinTypMaxUnitsOUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet)(Short Circuit Current)I SOURCE Output Source Current V CC e 5V V OUT e 0V b 1 75b 3 3mA (P-Channel)T A e 25 CI SOURCE Output Source Current V CC e 10V V OUT e 0V b 8b 15mA (P-Channel)T A e 25 CI SINK Output Sink Current V CC e 5V V OUT e V CC 1 753 6mA (N-Channel)T A e 25 CI SINKOutput Sink Current V CC e 10V V OUT e V CC 816mA(N-Channel)T A e 25 CAC Electrical Characteristics T A e 25 C C L e 50pF unless otherwise notedSymbol ParameterConditionsMinTyp Max Units t pd0 t pd1Propagation Delay Time to C L e 50pF (Figure 1)Logical ‘‘0’’or Logical ‘‘1’’V CC e 5V 60150ns from D AV CC e 10V 3580ns V CC e 15V2560ns t 0H t 1HPropagation Delay Time from R L e 10k C L e 10pF (Figure 2)Logical ‘‘0’’or Logical ‘‘1’’V CC e 5V R L e 10k 80200ns into High Impedance State V CC e 10V C L e 10pF 65150ns V CC e 15V50110ns t H0 t H1Propagation Delay Time from R L e 10k C L e 50pF (Figure 2)High Impedance State to a V CC e 5V R L e 10k 100250ns Logical ‘‘0’’or Logical ‘‘1’’V CC e 10V C L e 50pF 55125ns V CC e 15V 4090ns C IN Input CapacitanceAny Input (Note 2)57 5pF C OUTTRI-STATE Output CapacitanceAny Output (Note 2)10pFAC Parameters are guaranteed by DC correlated testingNote 1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’provides conditions for actual device operationNote 2 Capacitance is guaranteed by periodic testingSwitching Time WaveformsTL F 6037–3T1 T2 RC T3 0 7RC where R 10k and C is external capacitor at KBM inputFIGURE 1TL F 6037–4FIGURE 23Block DiagramTL F 6037–5 Truth TableSwitch012345678910111213141516171819 Position Y1 X1Y1 X2Y1 X3Y1 X4Y2 X1Y2 X2Y2 X3Y2 X4Y3 X1Y3 X2Y3 X3Y3 X4Y4 X1Y4 X2Y4 X3Y4 X4Y5 X1Y5 X2Y5 X3Y5 X4 DA A01010101010101010101 T B00110011001100110011 A C00001111000011110000 O D00000000111111110000 U E 00000000000000001111 TOmit for MM54C922 MM74C9224Typical Performance CharacteristicsTypical I rp vs V IN at Any Y InputTL F 6037–6Typical R on vs V OUT at Any X OutputTL F 6037–7Typical F SCAN vs C OSCTL F 6037–8Typical Debounce Period vs C KBMTL F 6037–9Typical ApplicationsSynchronous Handshake (MM74C922)TL F 6037–10Synchronous Data Entry Onto Bus (MM74C922)TL F 6037–11Outputs are enabled when valid entry is made and go into TRI-STATE when key is releasedNote 3 The keyboard may be synchronously scanned by omitting the capacitor at osc and driving osc directly if the system clock rate is lower than 10kHz5Typical Applications(Continued)Asynchronous Data Entry Onto Bus(MM74C922)TL F 6037–12Outputs are in TRI-STATE until key is pressed then data is placed on busWhen key is released outputs return to TRI-STATEExpansion to32Key Encoder(MM74C922)TL F 6037–13 Theory of OperationThe MM74C922 MM74C923Keyboard Encoders imple-ment all the logic necessary to interface a16or20SPST key switch matrix to a digital system The encoder will con-vert a key switch closer to a4(MM74C922)or 5(MM74C923)bit nibble The designer can control both the keyboard scan rate and the key debounce period by altering the oscillator capacitor C OSE and the key bounce mask capacitor C MSK Thus the MM74C922 MM74C923’s per-formance can be optimized for many keyboardsThe keyboard encoders connect to a switch matrix that is4 rows by4columns(MM74C922)or5rows by4columns (MM74C923) When no keys are depressed the row inputs are pulled high by internal pull-ups and the column outputs sequentially output a logic‘‘0’’ These outputs are open drain and are therefore low for25%of the time and other-wise off The column scan rate is controlled by the oscillator input which consists of a Schmitt trigger oscillator a2-bit counter and a2–4-bit decoderWhen a key is depressed key0 for example nothing will happen when the X1input is off since Y1will remain high When the X1column is scanned X1goes low and Y1will go low This disables the counter and keeps X1low Y1goinglow also initiates the key bounce circuit timing and locks out the other Y inputs The key code to be output is a combina-tion of the frozen counter value and the decoded Y inputs Once the key bounce circuit times out the data is latched and the Data Available(DAV)output goes highIf during the key closure the switch bounces Y1input will go high again restarting the scan and resetting the key bounce circuitry The key may bounce several times but as soon as the switch stays low for a debounce period the closure is assumed valid and the data is latchedA key may also bounce when it is released To ensure thatthe encoder does not recognize this bounce as another key closure the debounce circuit must time out before another closure is recognizedThe two-key roll-over feature can be illustrated by assuminga key is depressed and then a second key is depressedSince all scanning has stopped and all other Y inputs are disabled the second key is not recognized until the first key is lifted and the key bounce circuitry has resetThe output latches feed TRI-STATE which is enabled when the Output Enable(OE)input is taken low6Physical Dimensions inches(millimeters)Ceramic Dual-In-Line Package(J)Order Number MM54C922J or MM74C922JNS Package Number J18ACeramic Dual-In-Line Package(J)Order Number MM54C923J or MM74C923JNS Package Number J20A7Physical Dimensions inches(millimeters)(Continued)Plastic Small Outline I C Package(M)Order Number MM74C922M or MM74C923MNS Package Number M20B8Physical Dimensions inches(millimeters)(Continued)Plastic Dual-In-Line Package(N)Order Number MM54C922N or MM74C922NNS Package Number N18A9M M 54C 922 M M 74C 92216-K e y E n c o d e r M M 54C 923 M M 74C 92320-K e y E n c o d e rPhysical Dimensions inches (millimeters)(Continued)Plastic Dual-In-Line Package (N)Order Number MM54C923N or MM74C923NNS Package Number N20ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor CorporationEuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。