Manufacturing
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System-on-Chip Manufacturing Test EZ614:ELEC6016: Digital Systems SynthesisSystem-on-Chip•SoC: due to scaling down of CMOS transistors it is possible to design a complete system from cores on a single chip, System-on-Chip (SoC).•SoC benefits: small size, optimised and low cost chips•Core types:–Soft: synthesisable HDL based designs, allow usermodifications hence their flexibility. Exampleprocessors–Hard: transistor level GDSII based designs, allow nomodification but optimised. Example analogue cores(PLL, ADC, DAC)Design Validation (Functional Test)•Validation: check design performs as expected –Simulation: uses testbench, can be performed atbehavioural level and RTL for more accurate timinganalysis–Formal property checking: uses formal methods todetermine whether RTL design satisfy certain properties under all conditions.Common to use both methods to validate large digitaldesignsManufacturing Test•Generate an appropriate set of test vectors to test the correct manufacturing of the design (not the correctimplementation of the specification)•This type of test is known as Structural Test and normally costs less than functional test since it takes less time to generate and apply. Widely used to test digital designs for silicon defects.•There exists different silicon defects particularly in nanometre and hence different models: stuck-at, delay, ..•Manufacturing test aims to produce fault-free chips •Design-for-test DA tools: Mentor Graphics, SynopsysS y s t e m i n t e g r a t o rI C p r o v i d e rCor ep r o vid erCost of TestSource: ITRS, “The International Technology Roadmap for Semiconductors, 2001 Edition.”/.1980198519901995200020052010201510.10.0010.00010.000010.01C o s t p e r t r a n s i s t o r (c e n t s )•Test time •Capital investmentCost of Test (cont …)•High level of integration (0.13µprovides x2 transistors per sq. millimetre than 0.18µ)–High number of gates and of latches–High volumes of test data –High test times012345678910199920022005200820112014YearR e l a t i v e t e s t t i m eGate count [Mg]1248326416700605040302010V o l u m e o f t e s t d a t a [G b]Challenges in Embedded-Core Test•SoC cores are only manufactured and tested in final system •Test joint responsibility-Core provider: core-level internal test-Core user: chip-level test integration•What are the test challenges?1. Test Access to Embedded Cores2.Cost Effective Design for Test schemes for SoC3. SoC-level Test optimizationChallenges in Embedded-Core Test (cont..)Test Access to Embedded Cores•Cores are deeply embedded-no direct access to core terminals-other cores between IC pins and core terminals-normally, core terminals > IC pins•To test cores as stand-alone units, we need to-provide core test access (core terminals)-isolate cores7Architecture for Core Test Access: off-chip-Source and sink: test stimuli for CUT/compare test responses -TAM: transport test patterns to/from CUT, on-chip hardware -Wrapper: switches core terminals to functional I/O or TAMsinkArchitecture for Core Test Access: on-chipsinkArchitecture for Core Test Accessoff-chip source and sink-more TAM area-requires expensive testers, unless test resource partitioning on-chip source and sink-less TAM area-requires low cost testers-close to CUT-BIST area overheadArchitecture for Core Test Access: TAM Design •TAM Functions:-test stimuli from Source to CUT-test responses from CUT to Sink•TAM Design Parameters:-width: transport capacity (no. of wires)-length: transport distance (wire length)•Numerous TAM designs have been reportedArchitecture for Core Test Access: TAM Design TAM Functions:-test stimuli from Source to CUT-test responses from CUT to SinkTAM Design Parameters:-width: transport capacity (no. of wires)-length: transport distance (wire length)Numerous TAM designs have been reported1. Multiplexed access [1]-all cores get access to full available TAM width-simple, but slow since 1 core can be accessed at a time-total test time = sum of individual core test times2. Reused system bus [2]-SoCs have on-chip system bus which connects cores-ARM Advanced Microcontroller Bus Architecture (AMBA) -cheap, but fixed bus width (32-bit), does not allow trade-off (area, test time,..)3-Scalabe(variable width) TAMs[3]-Optimization problem: core-user design for test architecture given set of cores and number of test pins-find: no. of TAMs, their widths, core assignments to TAMS such that-test time is reduced, test time & area overhead minimized under constraints (power consumption, place & route,...) [4-6]-allows trade-offs (area, test time), design time (reduced by CAD tools), silicon area (silicon is cheap!)-example of scalable TAM: Philips, TestRail[7]Variable width TAM ExampleIEEE P1500 Standard for Embedded Core Test (SECT) [8]•Standardize interface between core provider and core user •Do not standardize:-core internal test methods (Scan, BIST), source and sink-chip level test integration and optimization•Two main components of P1500 standard1. Core test information model: test patterns and waveforms for core, information about core integration into SoC through use of Core Test Language (CTL)2. Core test wrapper, how to connect the TAM to the CUTP1500 Core Test Wrapper•Transparent functional mode •Access for core-internal tests •Access for core-external testsfunctional datatest control + test stimulifunctional datatest stimulitest responsestest control+ test responsesWrapper Elements•Wrapper Bypass Register (WBY)-bypass for single-bit TAM•Wrapper Boundary Register (WBR)-provides test access at the core terminal-core-external testing, WBR serial SR WSI & WSO-WBR built from wrapper boundary cells (1FF, 2 mux)clkwpi 1/wsii 1wbc 2wcitcDesign for Test for SoC•SoC test involves dealing with large amount of test data •Example [9]: Network processor 7M gates IP needs 1.6Gof test data for 100% fault coverage•Test data needs storing & transferring between tester & core •Testers have limited memory and speed•Low cost SoC test needed to make best use of SoC[10]Test Cost Solution•Test Resource Partitioning-Adds on-chip hardware-Reduces the load on the ATE•Compression/decompression-Embedded deterministic test (TestKompress, Mentor Graphics)-SmartBIST(IBM)-SoCTest(synopsys)Test Cost Solution (cont…) Test data compressionSoC Test (cont…)System’s Integrators PerspectiveTrade-off serial/parallel decoders: TAT, AOH, Compression ratiosDesign for Test for SoC•Network processor IP [9] test data reduces to 94M from 1.6G using compression and still 100% fault coverage•Compression techniques: Golomb[ 14], FDR [15 ], Huffman [ 16-17]•Decoders-serial or parallel (trade-offs between speed and cost)-on-chip hardware decoder , FSM (6-12 states)-on-chip software decoder, embedded processor [22]Test Data Compression (cont …)= 26 bitstinith m = 4t init 10100000000000000010000001= 16 bits 26-16/26=39%t cmp t cmp10111001000110101000100101Huffman treeL 1=1L 11=012L 1=0013L 1=0001L 400004=DictionaryOccurrencePattern 0000010100111CodeC o m p a c t o rD e c o m p r e s s o rATEresponsesstimuliEDT –Mentor GraphicsSource: Embedded Deterministic Test for Low-Cost Manufacturing, J. Rajski et. Al, ITC02SummaryTest Resource Partitioning•Test Data Compression-Enabling technology for low cost test -Academic and commercial tools•Core wrapper and TMA design Influence cost of SoC test -Objectives minimise test time under area, power constraint -Academic and commercial toolsReferences1. J. Aerts, Scan chain design for test time reduction in core-based ICs, Proc. ITC, pp.448-57, 19982. P. Harrod, Testing reusable IP-A case study, Proc. ITC, pp.493-98,19993. E. Marinissen, A structured and scalable mechanism for test access to embedded reusablecores, proc. ITC, pp.284-93,19984. K. Chakrabarty, Design of SoC test access architecture under place-and-route and powerconstraints, Proc. of DAC, pp. 432-37, 20005. K. Chakrabarty, Test scheduling for core based systems, Proc.of ICCD, pp.391-94, 1999,6. N. Nicolici, B. Al-Hashimi, Power conscious test synthesis and scheduling for BIST RTL data paths,Proc. ITC, pp.662-671, 20007. S. Goel, Cluster-based architecture design for SoC, Proc. VTS, 2002E. Marinissen, On using IEEE P1500 SECT for test plug-n-play, proc. ITC, pp.770-77, 20008. IEEE P1500 Web Site, /gropus/1500/.9. A. Khoche, Test vector compression using EDA-ATE synergies, Proc. VTS, pp.97-102,200210. S. Beaumont, The Soc challenge, IEE Electronics and Communications Engineering, Journal, 13,6,pp.234-35,200111. A. Chandra, Test resource partitioning for Soc, Proc. DATE, 18,pp.80-91,200112. P. Gonciari, B. Al-Hashimi, Useless memory allocation in SoC test”, Proc. VTS, pp. 423-29, 200213. Y. Zorian, Test of future SoC, Proc. ICCD, pp.392-400, 200014. A. Chandra, Soc test data compression and decompression architectures based on Golomb coding, IEEE Trans. on CAD, 20,pp.113-120,2001--------useful website listing papers published in area of SoC-----E.J. Marinissen, /groups/1500/bib/-------Soc test benchmarks---------/itc02socbench-----Workshop on Testing Embedded Core Based Systems-------/groups/1500/tecs/----Virtual socket interface alliance (VSIA)-----/-----easy to read papers-----E.J. Marinissen, Towards a standard for embedded core test: an example, Proc. ITC, pp.616-27, 1999Y. Zorian, Testing embedded core based system chips, IEEE Computer, 32(6),pp.52-60, 1999Chapter 22, SoC book, Al-Hashimi, Good overview on SoC Manufacturing Test。
