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5416_dsk_vhdl_c5416_ddb

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------------------------------------------------------------------------ FILE NAME : c5416_ddb.vhd-- TITLE :-- DESCRIPTION : This module contains the Top level file for the 5416-- DDB CPLD-- NOTES : Active low signals are indicated with '_l' appended-- to the signal name.-- Identifiers ending in '_pin' are physical pins.-- All internal registers are active high.------------------------------------------------------------------------ REVISION HISTORY :---- REV DATE DESCRIPTION AUTHOR-- === ======== ================================= ================-- * 01/09/01 Original Release------------------------------------------------------------------------LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;--USE IEEE.STD_LOGIC_ARITH.ALL;--USE WORK.STD_ARITH.ALL;--USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY c5416_ddb ISPORT(------------------------------------------------------------------------------- CPLD Reset Interface-----------------------------------------------------------------------------board_reset_l_pin: IN STD_LOGIC;-- Pulse Cont. Board Rst (Pin BRD_RST#)button_reset_l_pin: IN STD_LOGIC;-- Pushbutton Reset (Pin SW_RST#)db_vcc_bad_l_pin: IN STD_LOGIC;-- DB Power Reset (Pin DB_P_RST#)usb_dsp_reset_l_pin : IN STD_LOGIC;-- USB Host DSP Reset (Pin USB_DSP_RST#)emu_sel_pin: IN STD_LOGIC;-- Emulation Select (JTAG or On-board)reset_strobe_l_pin: OUT STD_LOGIC;-- Rst to TPS3307 (Pin MAN_RST#)dc_reset_l_pin: OUT STD_LOGIC;-- Rst to Daughter Board (Pin DC_RESET#)------------------------------------------------------------------------------- CPLD User Switches/Leds Interface-----------------------------------------------------------------------------user_switch0_pin : IN STD_LOGIC;-- Dip Switch 0 (Pin USER_SW0)user_switch1_pin : IN STD_LOGIC;-- Dip Switch 1 (Pin USER_SW1)user_switch2_pin : IN STD_LOGIC;-- Dip Switch 2 (Pin USER_SW2)user_switch3_pin : IN STD_LOGIC;-- Dip Switch 3 (Pin USER_SW3)user_led0_l_pin : OUT STD_LOGIC;-- User LED 0 (Pin USER_LED0#)user_led1_l_pin : OUT STD_LOGIC;-- User LED 1 (Pin USER_LED1#)user_led2_l_pin : OUT STD_LOGIC;-- User LED 2 (Pin USER_LED2#)user_led3_l_pin : OUT STD_LOGIC;-- User LED 3 (Pin USER_LED3#)------------------------------------------------------------------------------- CPLD Memory Interface-----------------------------------------------------------------------------dsp_data_dir_pin : OUT STD_LOGIC;-- DSP Data Buffer Dir (Pin DSP_DATA_DIR)dsp_data_oe_l_pin : OUT STD_LOGIC;-- DSP Data Buffer OE (Pin DSP_DATA_OE#)dm_mem_loc_pin: OUT STD_LOGIC;-- On-Board/Daughter Mem Sel (Pin DM_SEL#)dm_page0_pin: OUT STD_LOGIC;-- External Data Mem Pg Sel (Pin DM_PG0)dm_page1_pin : OUT STD_LOGIC;-- External Data Mem Pg Sel (Pin DM_PG1)dm_page2_pin : OUT STD_LOGIC;-- External Data Mem Pg Sel (Pin DM_PG2)dm_page3_pin : OUT STD_LOGIC;-- External Data Mem Pg Sel (Pin DM_PG3)dm_page4_pin : OUT STD_LOGIC;-- External Data Mem Pg Sel (Pin DM_PG4)dc_ds_l_pin : OUT STD_LOGIC;-- Daughter Card Data Mem Sel (Pin DC_DS#)dc_is_l_pin : OUT STD_LOGIC;-- Daughter Card I/O Mem Sel (Pin DC_IS#)dc_ps_l_pin : OUT STD_LOGIC;-- Daughter Card Program Mem Sel (Pin DC_PS#) dc_io_strb_l_pin: OUT STD_LOGIC;-- Duaghter Card I/O Strobedc_m_strb_l_pin: OUT STD_LOGIC;-- Daughter Card Memory Strobedc_cntl_oe_l_pin : OUT STD_LOGIC;------------------------------------------------------------------------------- CPLD Daughter Card Interface-----------------------------------------------------------------------------dc_det_l_pin : IN STD_LOGIC;-- Daughter Board Detect (Pin DC_DET#) dc_stat1_pin: IN STD_LOGIC;dc_stat0_pin: IN STD_LOGIC;dc_cntl1_pin: OUT STD_LOGIC;dc_cntl0_pin: OUT STD_LOGIC;bsp2_sel_pin : OUT STD_LOGIC;-- On-board/Daughter BSP 2 Sel (Pin BSP2_SEL#)db_abce_l_pin : OUT STD_LOGIC;-- (Pin DB_ABCE#)db_able_l_pin : OUT STD_LOGIC;-- (Pin DB_ABLE#)db_aboe_l_pin : OUT STD_LOGIC;-- (Pin DB_ABOE#)db_bace_l_pin : OUT STD_LOGIC;-- (Pin DB_BACE#)db_bale_l_pin : OUT STD_LOGIC;-- (Pin DB_BALE#)db_baoe_l_pin : OUT STD_LOGIC;-- (Pin DB_BAOE#)------------------------------------------------------------------------------- CPLD DSP Interface-----------------------------------------------------------------------------dsp_addr0_pin : IN STD_LOGIC;-- DSP Addr0, for I/O Reg Sel (Pin DA0)dsp_addr1_pin : IN STD_LOGIC;-- DSP Addr1, for I/O Reg Sel (Pin DA1)dsp_addr2_pin : IN STD_LOGIC;-- DSP Addr2, for I/O Reg Sel (Pin DA2)dsp_addr14_pin : IN STD_LOGIC;-- DSP Addr14, for I/O Device Sel (Pin DA14)dsp_addr15_pin : IN STD_LOGIC;-- DSP Addr15, for I/O Device Sel (Pin DA15)dsp_addr22_pin : IN STD_LOGIC;-- DSP Addr22, for PS on-brd/DB Mem Sel (Pin DA22) dsp_ds_l_pin : IN STD_LOGIC;-- DSP Data Mem Sel (Pin DSP_DS#)dsp_io_strobe_l_pin : IN STD_LOGIC;-- DSP I/O Memory Strobe (Pin DSP_IOSTRB#)dsp_is_l_pin : IN STD_LOGIC;-- DSP I/O Mem Sel (Pin DSP_IS#)dsp_m_strobe_l_pin : IN STD_LOGIC;-- DSP Memory Strobe (Pin DSP_MSTRB#)dsp_ps_l_pin : IN STD_LOGIC;-- DSP Program Mem Sel (Pin DSP_PS#)dsp_rw_l_pin : IN STD_LOGIC;-- DSP Read/Write Sel (Pin DSP_R/W#)dsp_data0_pin : INOUT STD_LOGIC;-- DSP EMIF Data0 (Pin DD0)dsp_data1_pin : INOUT STD_LOGIC;-- DSP EMIF Data1 (Pin DD1)dsp_data2_pin : INOUT STD_LOGIC;-- DSP EMIF Data2 (Pin DD2)dsp_data3_pin : INOUT STD_LOGIC;-- DSP EMIF Data3 (Pin DD3)dsp_data4_pin : INOUT STD_LOGIC;-- DSP EMIF Data4 (Pin DD4)dsp_data5_pin : INOUT STD_LOGIC;-- DSP EMIF Data5 (Pin DD5)dsp_data6_pin : INOUT STD_LOGIC;-- DSP EMIF Data6 (Pin DD6)dsp_data7_pin : INOUT STD_LOGIC;-- DSP EMIF Data7 (Pin DD7)------------------------------------------------------------------------------- CPLD Codec (A/D) Interface-----------------------------------------------------------------------------codec_clk_pin: IN STD_LOGIC; -- Codec Serial Clk (Pin MIC/SPKR_SCLK) codec_bclk_pin: OUT STD_LOGIC;-- Codec Bit Clkcodec_fs_pin : OUT STD_LOGIC; -- Codec Frame Sync (Pin MIC/SPKR_FS) codec_mc_pin: OUT STD_LOGIC;-- Codec Master Clockcodec_md_pin: OUT STD_LOGIC;-- Codec Master Datacodec_ml_pin: OUT STD_LOGIC;-- Codec Master Loadcodec_clk_out_pin : OUT STD_LOGIC; -- Derived codec clock------------------------------------------------------------------------------- CPLD Device Control Interface-------------------------------------------------------------------------------flash_ps_l_pin : OUT STD_LOGIC;-- On-Board FLASH PS Enable (Pin FLASH_PS#)--flash_ds_l_pin : OUT STD_LOGIC;-- On-Board FLASH DS Enable (Pin FLASH_DS#)--sram_ds_l_pin : OUT STD_LOGIC;-- On-Board SRAM DS Enable (Pin SRAM_DS#)--sram_ps_l_pin : OUT STD_LOGIC;-- On-Board SRAM PS Enable (Pin SRAM_PS#)-- The following signals have been added for Rev C of the boardsram_we_l_pin : OUT STD_LOGIC;sram_re_l_pin : OUT STD_LOGIC;flash_ce_l_pin : OUT STD_LOGIC;flash_we_l_pin : OUT STD_LOGIC;flash_oe_l_pin : OUT STD_LOGIC;dc_we_l_pin : OUT STD_LOGIC;dc_re_l_pin : OUT STD_LOGIC;dc_oe_l_pin : OUT STD_LOGIC;------------------------------------------------------------------------------- CPLD Clock Interface-----------------------------------------------------------------------------board_ver2_pin: IN STD_LOGIC;board_ver1_pin: IN STD_LOGIC;board_ver0_pin: IN STD_LOGIC;clk_20mhz_pin : IN STD_LOGIC-- 20MHz Clock from Osc. (Pin CLK_20MHZ));END c5416_ddb;ARCHITECTURE rtl OF c5416_ddb ISSIGNAL board_reset_l: STD_LOGIC;-- board resetSIGNAL board_ver: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL boot_int_l: STD_LOGIC;-- boot interruptSIGNAL bsp2_sel: STD_LOGIC;-- bsp1 select controlSIGNAL button_reset_l: STD_LOGIC;-- Switch ResetSIGNAL clk_20mhz: STD_LOGIC;-- cpld clockSIGNAL codec_bclk: STD_LOGIC;SIGNAL codec_clk: STD_LOGIC;-- codec clockSIGNAL codec_fs: STD_LOGIC;SIGNAL codec_hreg_sel: STD_LOGIC;SIGNAL codec_lreg_sel: STD_LOGIC;SIGNAL codec_mc: STD_LOGIC;SIGNAL codec_md: STD_LOGIC;SIGNAL codec_ml: STD_LOGIC;SIGNAL codec_mt_start: STD_LOGIC;SIGNAL codec_mt_rdy: STD_LOGIC;SIGNAL codec_m_data: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL cpld_rev: STD_LOGIC_VECTOR(3 DOWNTO 0); -- cpld revisionSIGNAL dc_32odd: STD_LOGIC;-- DB Mem Access Even/OddSIGNAL dc_det_l: STD_LOGIC;-- Daughter Board DetectSIGNAL db_abce_l: STD_LOGIC;-- AB Data Latch Chip EnableSIGNAL db_able_l: STD_LOGIC;-- AB Data Latch Latch EnableSIGNAL db_aboe_l: STD_LOGIC;-- AB Data Latch Output EnableSIGNAL db_bace_l: STD_LOGIC;-- BA Data Latch Chip EnableSIGNAL db_bale_l: STD_LOGIC;-- BA Data Latch Latch EnableSIGNAL db_baoe_l: STD_LOGIC;-- BA Data Latch Output EnableSIGNAL dc_cntl: STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL dm_mem_loc: STD_LOGIC;-- Data Memory Location (On-board/Daughtercard) SIGNAL dc_stat: STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL dc_reset_reg: STD_LOGIC;-- DC Reset from DSPSIGNAL db_vcc_bad_l: STD_LOGIC;-- DB Power ResetSIGNAL dc_wide: STD_LOGIC;-- Daughter Board Mem WidthSIGNAL dc_ds_l: STD_LOGIC;-- Daughter Card Data Memory SelectSIGNAL dc_is_l: STD_LOGIC;-- Daughter Card I/O Memory SelectSIGNAL dc_ps_l: STD_LOGIC;-- Daughter Card Program Memory SelectSIGNAL dc_io_strb_l: STD_LOGIC;-- Daughter Card I/O StrobeSIGNAL dc_m_strb_l: STD_LOGIC;-- Duaghter Memory StrobeSIGNAL dc_reset_l: STD_LOGIC;-- Daughter Card ResetSIGNAL dm_page: STD_LOGIC_VECTOR(4 DOWNTO 0); -- Data Memory Page 0 through 4 SIGNAL dsp_addr_high: STD_LOGIC;-- DSP Address 22SIGNAL dsp_addr_mid: STD_LOGIC_VECTOR(3 DOWNTO 0); -- dsp addr 12 -> 15SIGNAL dsp_addr_low: STD_LOGIC_VECTOR(2 DOWNTO 0); -- dsp addr 0 -> 2SIGNAL dsp_data: STD_LOGIC_VECTOR(7 DOWNTO 0); -- dsp data 7 -> 0SIGNAL dsp_data_in: STD_LOGIC_VECTOR(7 DOWNTO 0); -- dsp data in 7 -> 0SIGNAL dsp_data_out: STD_LOGIC_VECTOR(7 DOWNTO 0); -- dsp data out 7 -> 0SIGNAL dsp_data_dir: STD_LOGIC;-- DSP Data Buffer DirectionSIGNAL dsp_data_oe_l: STD_LOGIC;-- DSP Data Buffer OESIGNAL dsp_ds_l: STD_LOGIC;-- DSP's Data Memory SelectSIGNAL dsp_cpld_cs: STD_LOGIC;-- DSP's CPLD Chip selectSIGNAL dsp_io_strobe_l: STD_LOGIC;-- DSP's I/O StrobeSIGNAL dsp_is_l: STD_LOGIC;-- DSP's I/O Memory SelectSIGNAL dsp_m_strobe_l: STD_LOGIC;-- DSP's Memory StrobeSIGNAL dsp_ps_l: STD_LOGIC;-- DSP's Progam Mem SelectSIGNAL dsp_reset_l: STD_LOGIC;-- DSP's ResetSIGNAL dsp_rw_l: STD_LOGIC;-- DSP_RW#SIGNAL emu_sel: STD_LOGIC;-- Emulation SelectSIGNAL flash_ds_l: STD_LOGIC;-- flash chip enable for data spaceSIGNAL flash_ps_l: STD_LOGIC;-- flash chip enable for program spaceSIGNAL float_l: STD_LOGIC;-- FLOAT#SIGNAL mem_type_ds: STD_LOGIC;-- FLASH or SRAM CE RegisterSIGNAL mem_type_ps: STD_LOGIC;-- FLASH or SRAM CE RegisterSIGNAL dc_io_cntl : STD_LOGIC;SIGNAL reset_strobe_l: STD_LOGIC;-- Reset into TPS3307SIGNAL sram_ds_l: STD_LOGIC;-- sram chip enable for data spaceSIGNAL sram_ps_l: STD_LOGIC;-- sram chip enable for program spaceSIGNAL user_led: STD_LOGIC_VECTOR(3 DOWNTO 0); -- user_led 0 through 3SIGNAL user_switch0: STD_LOGIC;-- Dip Switch 0SIGNAL user_switch1: STD_LOGIC;-- Dip Switch 1SIGNAL user_switch2: STD_LOGIC;-- Dip Switch 2SIGNAL user_switch3: STD_LOGIC;-- Dip Switch 3SIGNAL usb_dsp_reset_l: STD_LOGIC;-- USB Software ResetSIGNAL codec_div_sel : STD_LOGIC;SIGNAL codec_clk_hold : STD_LOGIC;SIGNAL codec_clk_div : STD_LOGIC_VECTOR( 1 DOWNTO 0 );SIGNAL codec_clk_out : STD_LOGIC;------------------------------------------------------------------------ Component Definitions----------------------------------------------------------------------COMPONENT daughter_boardPORT(dc_32odd: IN STD_LOGIC;-- Even or Odd Address Selectdm_mem_loc: IN STD_LOGIC;-- Data Memory Location (Onboard or Daughtercard) dc_wide: IN STD_LOGIC;-- 16 or 32-bit Accessesdsp_addr_high: IN STD_LOGIC;-- dsp Address 19dsp_addr_low: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- dsp Address 0 ->2dsp_addr_mid: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- dsp Address 12 -> 15dsp_ds_l: IN STD_LOGIC;-- dsp's Data Memory Selectdsp_io_strobe_l: IN STD_LOGIC;-- dsp's I/O Strobedsp_is_l: IN STD_LOGIC;-- dsp's I/O Memory Selectdsp_m_strobe_l: IN STD_LOGIC;-- dsp's Memory Strobedsp_ps_l: IN STD_LOGIC;-- dsp's Program Memory Selectdsp_rw_l: IN STD_LOGIC;-- dsp's Read/Write Linedb_abce_l: OUT STD_LOGIC;-- AB Data Latch CEdb_able_l: OUT STD_LOGIC;-- AB Data Latch LEdb_aboe_l: OUT STD_LOGIC;-- AB Data Latch OEdb_bace_l: OUT STD_LOGIC;-- BA Data Latch CEdb_bale_l: OUT STD_LOGIC;-- BA Data Latch LEdb_baoe_l: OUT STD_LOGIC;-- BA Data Latch OEdc_ds_l: OUT STD_LOGIC;-- DC Data Selectdc_is_l: OUT STD_LOGIC;-- DC I/O Selectdc_ps_l: OUT STD_LOGIC;-- DC Program Selectdc_io_strb_l: OUT STD_LOGIC;-- Daughter Card I/O Strobedc_m_strb_l: OUT STD_LOGIC);-- DC Memory StrobeEND COMPONENT; -- daughter_boardCOMPONENT decodePORT(dm_mem_loc: IN STD_LOGIC;-- Data Memory Location (Onboard or Daughtercard) dsp_addr_high : IN STD_LOGIC;dsp_addr_mid: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- dsp addr 12 -> 15dsp_ds_l: IN STD_LOGIC;-- DSP's Data Space Selectdsp_is_l: IN STD_LOGIC;-- DSP's I/O Space Selectdsp_ps_l: IN STD_LOGIC;-- DSP's Program Space Selectdsp_rw_l: IN STD_LOGIC;-- dsp's read/write signalmem_type_ds: IN STD_LOGIC;-- flash/sram memory select (reg)mem_type_ps: IN STD_LOGIC;-- flash/sram memory select (reg)dsp_data_dir: OUT STD_LOGIC;-- dsp data buffer directiondsp_data_oe_l: OUT STD_LOGIC;-- dsp data buffer oedsp_cpld_cs: OUT STD_LOGIC;-- DSP's CPLD Chip Enableflash_ds_l: OUT STD_LOGIC;-- flash chip enable for data spaceflash_ps_l: OUT STD_LOGIC;-- flash chip enable for program spacesram_ds_l: OUT STD_LOGIC;-- sram chip enable for data spacesram_ps_l: OUT STD_LOGIC);-- sram chip enable for program spaceEND COMPONENT; -- decodeCOMPONENT registersPORT(board_reset_l: IN STD_LOGIC; -- board resetcpld_rev: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- cpld revisiondc_det_l: IN STD_LOGIC; -- daughter board detectdc_stat: IN STD_LOGIC_VECTOR(1 DOWNTO 0);dsp_addr_low: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- dsp addr 0 -> 3dsp_cpld_cs: IN STD_LOGIC; -- dsp cpld chip seldsp_data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- dsp data In 0 -> 7dsp_io_strobe_l: IN STD_LOGIC; -- dsp's I/O strobedsp_reset_l: IN STD_LOGIC; -- dsp reset status for registerdsp_rw_l: IN STD_LOGIC;codec_mt_rdy: IN STD_LOGIC;user_switch0: IN STD_LOGIC;-- user dip switch 0user_switch1: IN STD_LOGIC;-- user dip switch 1user_switch2: IN STD_LOGIC;-- user dip switch 2user_switch3: IN STD_LOGIC;-- user dip switch 3board_ver: IN STD_LOGIC_VECTOR(2 DOWNTO 0);bsp2_sel: OUT STD_LOGIC; -- McBSP2 sel Controldc_32odd: OUT STD_LOGIC; -- DB Memory Access Even/Odddc_cntl: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);dm_mem_loc: OUT STD_LOGIC; -- Data Memory Location (Onboard or Daughtercard) dm_page: OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- memory page 0 -> 4dc_reset_reg: OUT STD_LOGIC; -- DB Reset from DSPdc_wide: OUT STD_LOGIC; -- DB Memory Width 16/32dsp_data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- dsp data out 0 -> 7 mem_type_ds: OUT STD_LOGIC; -- CE for FLASH or SRAMmem_type_ps: OUT STD_LOGIC; -- CE for FLASH or SRAMdc_io_cntl : OUT STD_LOGIC;user_led: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);codec_mt_start: OUT STD_LOGIC;codec_m_data: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);codec_div_sel : OUT STD_LOGIC;codec_clk_hold : OUT STD_LOGIC;codec_clk_div : OUT STD_LOGIC_VECTOR( 1 downto 0 ) );END COMPONENT; -- registersCOMPONENT codecPORT(board_reset_l: IN STD_LOGIC;-- Reset Signalcodec_clk: IN STD_LOGIC; -- PLL Clockcodec_mt_start: IN STD_LOGIC; -- load new valuecodec_m_data: IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- Datacodec_bclk: OUT STD_LOGIC;codec_fs: OUT STD_LOGIC;codec_mc: OUT STD_LOGIC; -- codec master clockcodec_md: OUT STD_LOGIC; -- codec master datacodec_ml: OUT STD_LOGIC;-- codec master loadcodec_mt_rdy: OUT STD_LOGIC;codec_div_sel : IN STD_LOGIC;codec_clk_hold : IN STD_LOGIC;codec_clk_div : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );codec_clk_out : OUT STD_LOGIC);END COMPONENT;-- codecCOMPONENT resetPORT(board_reset_l: IN STD_LOGIC; -- board reset from tps3707button_reset_l: IN STD_LOGIC; -- reset from push buttondc_reset_reg: IN STD_LOGIC; -- db reset register (dsp)db_vcc_bad_l: IN STD_LOGIC; -- 3.3b db monitorusb_dsp_reset_l: IN STD_LOGIC; -- dsp reset from usb host intf.emu_sel: IN STD_LOGIC; -- Emulation Selected (JTAG or On-board)reset_strobe_l: OUT STD_LOGIC; -- reset strobe to tps3707dc_reset_l: OUT STD_LOGIC);-- reset to dcEND COMPONENT; -- resetBEGIN------------------------------------------------------------------------ Input Pin Assignments----------------------------------------------------------------------board_reset_l <= board_reset_l_pin;board_ver(2) <= board_ver2_pin;board_ver(1) <= board_ver1_pin;board_ver(0) <= board_ver0_pin;button_reset_l <= button_reset_l_pin;clk_20mhz <= clk_20mhz_pin;dc_det_l <= dc_det_l_pin;db_vcc_bad_l <= db_vcc_bad_l_pin;dc_stat(1) <= dc_stat1_pin;dc_stat(0) <= dc_stat0_pin;dsp_addr_high <= DSP_ADDR22_pin;dsp_addr_mid(3) <= DSP_ADDR15_pin;dsp_addr_mid(2) <= DSP_ADDR14_pin;dsp_addr_mid(1) <= '0'; -- Was DSP_ADDR13_pindsp_addr_mid(0) <= '0'; -- Was DSP_ADDR12_pindsp_addr_low(2) <= DSP_ADDR2_pin;dsp_addr_low(1) <= DSP_ADDR1_pin;dsp_addr_low(0) <= DSP_ADDR0_pin;dsp_data_in(7) <= dsp_data7_pin;dsp_data_in(6) <= dsp_data6_pin;dsp_data_in(5) <= dsp_data5_pin;dsp_data_in(4) <= dsp_data4_pin;dsp_data_in(3) <= dsp_data3_pin;dsp_data_in(2) <= dsp_data2_pin;dsp_data_in(1) <= dsp_data1_pin;dsp_data_in(0) <= dsp_data0_pin;dsp_ds_l <= dsp_ds_l_pin;dsp_io_strobe_l <= dsp_io_strobe_l_pin;dsp_is_l <= dsp_is_l_pin;dsp_m_strobe_l <= dsp_m_strobe_l_pin;dsp_ps_l <= dsp_ps_l_pin;dsp_rw_l <= dsp_rw_l_pin;codec_clk <= codec_clk_pin;usb_dsp_reset_l <= usb_dsp_reset_l_pin;user_switch0 <= user_switch0_pin;user_switch1 <= user_switch1_pin;user_switch2 <= user_switch2_pin;user_switch3 <= user_switch3_pin;emu_sel <= emu_sel_pin;------------------------------------------------------------------------ Bi-Directional Output Pin Assignments----------------------------------------------------------------------dsp_data7_pin <= dsp_data_out(7) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data6_pin <= dsp_data_out(6) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data5_pin <= dsp_data_out(5) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data4_pin <= dsp_data_out(4) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data3_pin <= dsp_data_out(3) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data2_pin <= dsp_data_out(2) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data1_pin <= dsp_data_out(1) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';dsp_data0_pin <= dsp_data_out(0) WHEN (dsp_cpld_cs = '1' AND dsp_rw_l = '1') ELSE 'Z';------------------------------------------------------------------------ Output Pin Assignments----------------------------------------------------------------------bsp2_sel_pin <= bsp2_sel;dc_cntl1_pin <= dc_cntl(1);dc_cntl0_pin <= dc_cntl(0);db_abce_l_pin <= db_abce_l;db_able_l_pin <= db_able_l;db_aboe_l_pin <= db_aboe_l;db_bace_l_pin <= db_bace_l;db_bale_l_pin <= db_bale_l;db_baoe_l_pin <= db_baoe_l;dm_mem_loc_pin <= dm_mem_loc;dc_ds_l_pin <= dc_ds_l;dc_is_l_pin <= dc_is_l;dc_ps_l_pin <= dc_ps_l;dc_io_strb_l_pin <= dc_io_strb_l;dc_m_strb_l_pin <= dc_m_strb_l;dc_reset_l_pin <= dc_reset_l;dm_page4_pin <= dm_page(4);dm_page3_pin <= dm_page(3);dm_page2_pin <= dm_page(2);dm_page1_pin <= dm_page(1);dm_page0_pin <= dm_page(0);dsp_data_dir_pin <= dsp_data_dir;dsp_data_oe_l_pin <= dsp_data_oe_l;--flash_ds_l_pin <= flash_ds_l;--flash_ps_l_pin <= flash_ps_l;codec_bclk_pin <= codec_bclk;codec_fs_pin <= codec_fs;codec_mc_pin <= codec_mc;codec_md_pin <= codec_md;codec_ml_pin <= codec_ml;codec_clk_out_pin <= codec_clk_out;reset_strobe_l_pin <= reset_strobe_l;--sram_ds_l_pin <= sram_ds_l;--sram_ps_l_pin <= sram_ps_l;user_led3_l_pin <= user_led(3);user_led2_l_pin <= user_led(2);user_led1_l_pin <= user_led(1);user_led0_l_pin <= user_led(0);dc_cntl_oe_l_pin <= '0'; -- WHEN dc_det_l_pin = '0' else '1';------------------------------------------------------------------------ BEGIN: REV C ADDS---------------------------------------------------------------------- dc_we_l_pin <= '0' when ( ( dsp_m_strobe_l = '0'and dsp_rw_l = '0')or ( dc_io_strb_l = '0'and dsp_rw_l = '0'and dc_io_cntl = '1'))else '1';dc_re_l_pin <= '0' when ( ( dsp_m_strobe_l = '0'and dsp_rw_l = '1')or ( dc_io_strb_l = '0'and dsp_rw_l = '1'and dc_io_cntl = '1'))else '1';dc_oe_l_pin <= not dsp_rw_l_pin;sram_re_l_pin <= '0' when (( dsp_m_strobe_l = '0'and dsp_rw_l = '1')and( ( dsp_ps_l = '0'and mem_type_ps = '1')or( dsp_ds_l = '0'and mem_type_ds = '1'and dm_mem_loc = '0'))) else '1';sram_we_l_pin <= '0' when (( dsp_m_strobe_l = '0'and dsp_rw_l = '0')and( ( dsp_ps_l = '0'and mem_type_ps = '1')or( dsp_ds_l = '0'and mem_type_ds = '1'and dm_mem_loc = '0'))) else '1';flash_oe_l_pin <= '0' when (( dsp_m_strobe_l = '0'and dsp_rw_l = '1')and( ( dsp_ps_l = '0'and mem_type_ps = '0')or( dsp_ds_l = '0'and mem_type_ds = '0'and dm_mem_loc = '0'))) else '1';flash_we_l_pin <= '0' when (( dsp_m_strobe_l = '0'and dsp_rw_l = '0')and( ( dsp_ps_l = '0'and mem_type_ps = '0')or( dsp_ds_l = '0'and mem_type_ds = '0'and dm_mem_loc = '0'))) else '1';flash_ce_l_pin <= '0' when ( dsp_m_strobe_l = '0'and( mem_type_ps = '0'or( mem_type_ds = '0'and dm_mem_loc = '0'))) else '1';------------------------------------------------------------------------ END: REV C ADDS---------------------------------------------------------------------------------------------------------------------------------------------- CPLD Revision Number-- Current Status : Rev 2------------------------------------------------------------------------cpld_rev <= "0010";-- CPLD Versions:-- 0000 Original C5416 DDB CPLD Code-- 0001 Added in code to derive codec clock for 6/8/24/48KHz operation -- 0010 Changed memory interface------------------------------------------------------------------------ Instantiate Components----------------------------------------------------------------------I_daughter_board : daughter_boardPORT MAP(dc_32odd,dm_mem_loc,dc_wide,dsp_addr_high,dsp_addr_low,dsp_addr_mid,dsp_ds_l,dsp_io_strobe_l,dsp_is_l,dsp_m_strobe_l,dsp_ps_l,dsp_rw_l,db_abce_l,db_able_l,db_aboe_l,db_bace_l,db_bale_l ,db_baoe_l,dc_ds_l,dc_is_l,dc_ps_l,dc_io_strb_l,dc_m_strb_l);I_decode : decodePORT MAP(dm_mem_loc,dsp_addr_high,dsp_addr_mid,dsp_ds_l,dsp_is_l,dsp_ps_l,dsp_rw_l,mem_type_ds,mem_type_ps,dsp_data_dir,dsp_data_oe_l,dsp_cpld_cs,flash_ds_l,flash_ps_l,sram_ds_l,sram_ps_l);I_registers : registersPORT MAP(board_reset_l,cpld_rev,dc_det_l,dc_stat,dsp_addr_low,dsp_cpld_cs,dsp_data_in,dsp_io_strobe_l,dsp_reset_l,dsp_rw_l,codec_mt_rdy,user_switch0,user_switch1,user_switch2,user_switch3,board_ver,bsp2_sel,dc_32odd,dc_cntl,dm_mem_loc,dm_page,dc_reset_reg,dc_wide,dsp_data_out,mem_type_ds,mem_type_ps,dc_io_cntl,user_led,codec_mt_start,codec_m_data,codec_div_sel,codec_clk_hold, codec_clk_div);I_codec : codecPORT MAP(board_reset_l,codec_clk,codec_mt_start,codec_m_data,codec_bclk,codec_fs,codec_mc,codec_md,codec_ml,codec_mt_rdy,codec_div_sel,codec_clk_hold, codec_clk_div,codec_clk_out);I_reset : resetPORT MAP(board_reset_l,button_reset_l,dc_reset_reg,db_vcc_bad_l,usb_dsp_reset_l,emu_sel,reset_strobe_l,dc_reset_l);END rtl;。

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基于tms320c5416的相关运算

基于tms320c5416的相关运算

基于tms320c5416的相关运算
TMS320C5416是德州仪器（TI）公司生产的一款数字信号处
理器（DSP），主要应用于声音和语音处理、图像处理、机器
视觉、无线通信等领域。

它内置了丰富的算法库和硬件加速器，能够高效地完成复杂的数学运算和信号处理任务。

下面列举一些TMS320C5416常用的数学运算和信号处理指令：
1. 加法和减法指令：ADD、SUB。

2. 乘法指令：MPY（单精度乘法）、MPY16H（16位高位乘法）、MPY32（32位乘法）。

3. 除法指令：DIVS（有符号除法）、DIVU（无符号除法）。

4. 取模指令：MODS（有符号取模）、MODU（无符号取模）。

5. 移位指令：LSL（逻辑左移）、LSR（逻辑右移）、ASL
（算术左移）、ASR（算术右移）。

6. 逻辑运算指令：AND、OR、XOR、NOT。

7. 浮点运算指令：FADD、FSUB、FMUL、FDIV等。

8. 快速傅里叶变换（FFT）指令：FFT、IFFT。

9. 快速卷积（FIR）指令：FIR。

10. 数字滤波器指令：IIR2（二阶直接型数字滤波器）、IIR4（四阶直接型数字滤波器）等。

以上仅是部分指令，TMS320C5416还支持许多高级的数学运
算和信号处理算法，如卡尔曼滤波、小波变换、奇异值分解等。

这些指令和算法的高效执行是TMS320C5416广泛应用于数字
信号处理领域的关键所在。

2_DSP试验箱VC5416板原理说明讲解

2_DSP试验箱VC5416板原理说明讲解

DSP试验箱VC5416板原理说明一、DSP试验箱VC5416板的原理图位置C:\ICETEK\VC5416AE\DOCS\ICETEK-VC5416Ae原理图.pdf ，共6张①CPU.PFD ②CPLD.PFD ③RAM.PFD ④UART.PFD ⑤EXIO.PFD ⑥CODEC.PFD ICETEK-VC5416-A评估板及教学实验箱实验指导书VE3.pdfICETEK-VC5416-A 评估板技术指标（实验指导书P1）ICETEK-VC5416-A 原理图和实物图（实验指导书P2）所涉及的芯片请：到厂家网站，查看厂家的DATASHEET（英文版，权威；中文版是翻译）,内含其功能、技术指标、典型应用电路；或一般百度也可找到厂家的DATASHEET；或上中国知网，查相关应用的论文二、CPU.PFD原理图解剖1、CPU :TMS320VC5416CPU使用TI公司TMS320VC5416，其权威资料/product/tms320vc5416 或见教材、网络资料2、电源：VC5416的工作电压为３.３Ｖ、１.６Ｖ。

需要将5Ｖ的ＶＣＣ转化１１１７－３３是低压差线性稳压源芯片（加ａｍｓ之类前缀表示厂家），把5V 转成3.3v 。

（Ｃ２６对应的１０４＝１０＊１０＾４ｐｆ＝０．１ｕｆ）１１１７－ＡＤＪ是低压差线性稳压源芯片，ＡＤＪ表示输出电压可调； 查见ＴＬＶ１１１７－ＡＤＪ芯片资料知：495049*)1(R I R R V V ADJ REF O ++= REF V 典型值＝１.２５ｖ；ADJ I 典型值＝５５ｕｆ，可忽略。

（ＴＬＶ１１１７－ＡＤＪ） （此处电路中２个电阻值似乎有误）３、无源晶体Ｘ１、Ｘ２是５４１６的时钟引脚９６和９７。

集成电路振荡端子外围电路中总是以一个晶振（或其它谐振元件）和两个电容组成回路；晶振旁的2个电容是晶体的匹配电容，只有在外部所接电容为匹配电容的情况下，振荡频率才能保证在标称频率附近的误差范围内。

tms320vc5416数据手册

tms320vc5416数据手册

TMS320VC5416Fixed-Point Digital Signal Processor Data ManualPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.Literature Number:SPRS095PMarch1999–Revised October2008Revision HistoryTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH 1999–REVISED OCTOBER 2008NOTE:Page numbers for previous revisions may differ from page numbers in the current version.This data sheet revision history highlights the technical changes made to the SPRS095O device-specific data sheet to make it an SPRS095P revision.Scope:This document has been reviewed for technical accuracy;the technical content is up-to-date as of the specified release date with the following corrections.2Revision History Submit Documentation FeedbackContentsTMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH 1999–REVISED OCTOBER 2008Revision History ...........................................................................................................................1TMS320VC5416Features.......................................................................................................2Introduction.......................................................................................................................2.1Description ..................................................................................................................2.2PinAssignments............................................................................................................2.2.1TerminalAssignments forthe GGUPackage...............................................................2.2.2Pin AssignmentsforthePGEPackage......................................................................2.2.3Signal Descriptions ..............................................................................................3Functional Overview ...........................................................................................................3.1Memory ......................................................................................................................3.1.1Data Memory .....................................................................................................3.1.2Program Memory ................................................................................................3.1.3Extended Program Memory ...................................................................................3.2On-Chip ROM With Bootloader ...........................................................................................3.3On-Chip RAM ...............................................................................................................3.4On-Chip Memory Security .................................................................................................3.5Memory Map ................................................................................................................3.5.1Relocatable Interrupt Vector Table ............................................................................3.6On-Chip Peripherals .......................................................................................................3.6.1Software-Programmable Wait-State Generator .............................................................3.6.2Programmable Bank-Switching ................................................................................3.6.3Bus Holders ......................................................................................................3.7Parallel I/O Ports ...........................................................................................................3.7.1Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)..........................................................3.7.2HPI Nonmultiplexed Mode ......................................................................................3.8Multichannel Buffered Serial Ports (McBSPs)..........................................................................3.9Hardware Timer ............................................................................................................3.10Clock Generator ............................................................................................................3.11Enhanced External Parallel Interface (XIO2)...........................................................................3.12DMA Controller .............................................................................................................3.12.1Features ..........................................................................................................3.12.2DMA External Access ...........................................................................................3.12.3DMA Memory Maps .............................................................................................3.12.4DMA Priority Level ...............................................................................................3.12.5DMA Source/Destination Address Modification .............................................................3.12.6DMA in Autoinitialization Mode ................................................................................3.12.7DMA Transfer Counting .........................................................................................3.12.8DMA Transfer in Doubleword Mode ..........................................................................3.12.9DMA Channel Index Registers .................................................................................3.12.10DMA Interrupts ..................................................................................................3.12.11DMA Controller Synchronization Events .....................................................................3.13General-Purpose I/O Pins .................................................................................................3.13.1McBSP Pins as General-Purpose I/O .........................................................................3.13.2HPI Data Pins as General-Purpose I/O ......................................................................3.14Device ID Register .........................................................................................................3.15Memory-Mapped Registers ...............................................................................................3.16McBSP Control Registers and Subaddresses ..........................................................................3.17DMA Subbank Addressed Registers ....................................................................................3.18Interrupts ....................................................................................................................4Support .............................................................................................................................Contents3TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 4.1Documentation Support...................................................................................................4.2Device and Development-Support Tool Nomenclature................................................................5Electrical Specifications......................................................................................................5.1Absolute Maximum Ratings...............................................................................................5.2Recommended Operating Conditions...................................................................................5.3Electrical Characteristics.................................................................................................5.3.1Test Loading.....................................................................................................5.3.2Timing Parameter Symbology............................................................................................5.3.3Internal Oscillator With External Crystal.................................................................................5.4Clock Options...............................................................................................................5.4.1Divide-By-Two and Divide-By-Four Clock Options..........................................................5.4.2Multiply-By-N Clock Option(PLL Enabled)...................................................................5.5Memory and Parallel I/O Interface Timing..............................................................................5.5.1Memory Read....................................................................................................5.5.2Memory Write....................................................................................................5.5.3I/O Read..........................................................................................................5.5.4I/O Write..........................................................................................................5.5.5Ready Timing for Externally Generated Wait States..................................................................5.5.6and Timings...............................................................................................5.5.7Reset,BIO,Interrupt,and MP/MC Timings.............................................................................5.5.8Instruction Acquisition and Interrupt Acknowledge Timings..........................................5.5.9External Flag(XF)and TOUT Timings..................................................................................5.5.10Multichannel Buffered Serial Port(McBSP)Timing...................................................................5.5.10.1McBSP Transmit and Receive Timings....................................................................5.5.10.2McBSP General-Purpose I/O Timing.......................................................................5.5.10.3McBSP as SPI Master or Slave Timing....................................................................5.5.11Host-Port Interface Timing...............................................................................................5.5.11.1HPI8Mode.....................................................................................................5.5.11.2HPI16Mode....................................................................................................6Mechanical Data.................................................................................................................6.1Package Thermal Resistance Characteristics..........................................................................4Contents Submit Documentation FeedbackTMS320VC5416Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008List of Figures2-1144-Ball GGU MicroStar BGA™(Bottom View).............................................................................2-2144-Pin PGE Low-Profile Quad Flatpack(Top View).......................................................................3-1TMS320VC5416Functional Block Diagram..................................................................................3-2Program and Data Memory Map................................................................................................3-3Extended Program Memory Map...............................................................................................3-4Process Mode Status Register..................................................................................................3-5Software Wait-State Register(SWWSR)[Memory-Mapped Register(MMR)Address0028h].........................3-6Software Wait-State Register(SWWSR)[Memory-Mapped Register(MMR)Address0028h].........................3-7Bank-Switching Control Register BSCR)[MMR Address0029h]...........................................................3-8Host-Port Interface—Nonmulltiplexed Mode.................................................................................3-9HPI Memory Map.................................................................................................................3-10Multichannel Control Register(MCR1).........................................................................................3-11Multichannel Control Register(MCR2).........................................................................................3-12Pin Control Register(PCR)......................................................................................................3-13Nonconsecutive Memory Read and I/O Read Bus Sequence.............................................................3-14Consecutive Memory Read Bus Sequence(n=3reads)..................................................................3-15Memory Write and I/O Write Bus Sequence.................................................................................3-16DMA Transfer Mode Control Register(DMMCRn)...........................................................................3-17On-Chip DMA Memory Map for Program Space(DLAXS=0and SLAXS=0).........................................3-18On-Chip DMA Memory Map for Data and IO Space(DLAXS=0and SLAXS=0)....................................3-19DMPREC Register................................................................................................................3-20General-Purpose I/O Control Register(GPIOCR)[MMR Address003Ch]................................................3-21General-Purpose I/O Status Register(GPIOSR)[MMR Address003Dh].................................................3-22Device ID Register(CSIDR)[MMR Address003Eh].........................................................................3-23IFR and IMR Registers...........................................................................................................5-1Tester Pin Electronics............................................................................................................5-2Internal Divide-By-Two Clock Option With External Crystal...............................................................5-3External Divide-By-Two Clock Timing.........................................................................................5-4Multiply-By-One Clock Timing..................................................................................................5-5Nonconsecutive Mode Memory Reads.......................................................................................5-6Consecutive Mode Memory Reads............................................................................................5-7Memory Write(MSTRB=0)....................................................................................................5-8Parallel I/O Port Read(IOSTRB=0).........................................................................................5-9Parallel I/O Port Write(IOSTRB=0)..........................................................................................5-10Memory Read With Externally Generated Wait States.....................................................................5-11Memory Write With Externally Generated Wait States.....................................................................5-12I/O Read With Externally Generated Wait States...........................................................................5-13I/O Write With Externally Generated Wait States...........................................................................5-14HOLD and HOLDA Timings(HM=1).........................................................................................List of Figures5TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 5-15Reset and BIO Timings.........................................................................................................5-16Interrupt Timing..................................................................................................................5-17MP/MC Timing...................................................................................................................5-18Instruction Acquisition(IAQ)and Interrupt Acknowledge(IACK)Timings................................................5-19External Flag(XF)Timing......................................................................................................5-20TOUT Timing.....................................................................................................................5-21McBSP Receive Timings.......................................................................................................5-22McBSP Transmit Timings.......................................................................................................5-23McBSP General-Purpose I/O Timings........................................................................................5-24McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=0....................................................5-25McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=0....................................................5-26McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=1....................................................5-27McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=1....................................................5-28Using HDS to Control Accesses(HCS Always Low)........................................................................5-29Using HCS to Control Accesses...............................................................................................5-30HINT Timing......................................................................................................................5-31GPIOx Timings...................................................................................................................5-32Nonmultiplexed Read Timings.................................................................................................5-33Nonmultiplexed Write Timings.................................................................................................5-34HRDY Relative to CLKOUT....................................................................................................6List of Figures Submit Documentation FeedbackTMS320VC5416Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008List of Tables2-1Terminal Assignments for the TMS320VC5416GGU(144-Pin BGA Package).........................................2-2Signal Descriptions...............................................................................................................3-1Standard On-Chip ROM Layout...............................................................................................3-2Processor Mode Status(PMST)Register Bit Fields........................................................................3-3Software Wait-State Register(SWWSR)Bit Fields.........................................................................3-4Software Wait-State Control Register(SWCR)Bit Fields..................................................................3-5Bank-Switching Control Register(BSCR)Fields..............................................................................3-6Bus Holder Control Bits..........................................................................................................3-7Sample Rate Input Clock Selection...........................................................................................3-8Clock Mode Settings at Reset.................................................................................................3-9DMD Section of the DMMCRn Register......................................................................................3-10DMA Reload Register Selection...............................................................................................3-11DMA Interrupts...................................................................................................................3-12DMA Synchronization Events..................................................................................................3-13DMA Channel Interrupt Selection..............................................................................................3-14Device ID Register(CSIDR)Bits................................................................................................3-15CPU Memory-Mapped Registers................................................................................................3-16Peripheral Memory-Mapped Registers for Each DSP Subsystem........................................................3-17McBSP Control Registers and Subaddresses.................................................................................3-18DMA Subbank Addressed Registers...........................................................................................3-19Interrupt Locations and Priorities................................................................................................5-1Input Clock Frequency Characteristics.........................................................................................5-2Clock Mode Pin Settings for the Divide-By-2and By Divide-By-4Clock Options.......................................5-3Divide-By-2and Divide-By-4Clock Options Timing Requirements.......................................................5-4Divide-By-2and Divide-By-4Clock Options Switching Characteristics...................................................5-5Multiply-By-N Clock Option Timing Requirements..........................................................................5-6Multiply-By-N Clock Option Switching Characteristics......................................................................5-7Memory Read Timing Requirements..........................................................................................5-8Memory Read Switching Characteristics.....................................................................................5-9Memory Write Switching Characteristics.....................................................................................5-10I/O Read Timing Requirements................................................................................................5-11I/O Read Switching Characteristics...........................................................................................5-12I/O Write Switching Characteristics............................................................................................5-13Ready Timing Requirements for Externally Generated Wait States......................................................5-14Ready Switching Characteristics for Externally Generated Wait States..................................................5-15HOLD and HOLDA Timing Requirements....................................................................................5-16HOLD and HOLDA Switching Characteristics...............................................................................5-17Reset,BIO,Interrupt,and MP/MC Timing Requirements..................................................................5-18Instruction Acquisition(IAQ)and Interrupt Acknowledge(IACK)Switching Characteristics...........................List of Tables7TMS320VC5416Fixed-Point Digital Signal ProcessorSPRS095P–MARCH1999–REVISED 5-19External Flag(XF)and TOUT Switching Characteristics...................................................................5-20McBSP Transmit and Receive Timing Requirements.......................................................................5-21McBSP Transmit and Receive Switching Characteristics..................................................................5-22McBSP General-Purpose I/O Timing Requirements........................................................................5-23McBSP General-Purpose I/O Switching Characteristics...................................................................5-24McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=0).................................5-25McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=0).............................5-26McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=0).................................5-27McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=0).............................5-28McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=1).................................5-29McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=1).............................5-30McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=1).................................5-31McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=1).............................5-32HPI8Mode Timing Requirements.............................................................................................5-33HPI8Mode Switching Characteristics..........................................................................................5-34HPI16Mode Timing Requirements............................................................................................5-35HPI16Mode Switching Characteristics.......................................................................................6-1Thermal Resistance Characteristics............................................................................................8Submit Documentation Feedback List of Tables1TMS320VC5416FeaturesTMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P–MARCH1999–REVISED OCTOBER2008Reads•Advanced Multibus Architecture With ThreeSeparate16-Bit Data Memory Buses and One•Arithmetic Instructions With Parallel Store and Program Memory Bus Parallel Load•40-Bit Arithmetic Logic Unit(ALU)Including a•Conditional Store Instructions40-Bit Barrel Shifter and Two Independent•Fast Return From Interrupt 40-Bit Accumulators•On-Chip Peripherals•17-×17-Bit Parallel Multiplier Coupled to a–Software-Programmable Wait-State 40-Bit Dedicated Adder for Non-Pipelined Generator and ProgrammableSingle-Cycle Multiply/Accumulate(MAC)Bank-SwitchingOperation–On-Chip Programmable Phase-Locked •Compare,Select,and Store Unit(CSSU)for the Loop(PLL)Clock Generator With External Add/Compare Selection of the Viterbi Operator Clock Source–One16-Bit Timer•Exponent Encoder to Compute an Exponent–Six-Channel Direct Memory Access(DMA) Value of a40-Bit Accumulator Value in aControllerSingle Cycle–Three Multichannel Buffered Serial Ports •Two Address Generators With Eight Auxiliary(McBSPs)Registers and Two Auxiliary Register–8/16-Bit Enhanced Parallel Host-Port Arithmetic Units(ARAUs)Interface(HPI8/16)•Data Bus With a Bus Holder Feature•Power Consumption Control With IDLE1,•Extended Addressing Mode for8M×16-Bit IDLE2,and IDLE3Instructions With Maximum Addressable External ProgramPower-Down ModesSpace•CLKOUT Off Control to Disable CLKOUT •128K×16-Bit On-Chip RAM Composed of:•On-Chip Scan-Based Emulation Logic,IEEE –Eight Blocks of8K×16-Bit On-ChipStd1149.1(JTAG)Boundary Scan Logic(1) Dual-Access Program/Data RAM•144-Pin Ball Grid Array(BGA)(GGU Suffix)–Eight Blocks of8K×16-Bit On-ChipSingle-Access Program RAM•144-Pin Low-Profile Quad Flatpack(LQFP)(PGE Suffix)•16K×16-Bit On-Chip ROM Configured forProgram Memory• 6.25-ns Single-Cycle Fixed-Point InstructionExecution Time(160MIPS)•Enhanced External Parallel Interface(XIO2)•8.33-ns Single-Cycle Fixed-Point Instruction •Single-Instruction-Repeat and Block-RepeatExecution Time(120MIPS) Operations for Program Code• 3.3-V I/O Supply Voltage(160and120MIPS)•Block-Memory-Move Instructions for BetterProgram and Data Management• 1.6-V Core Supply Voltage(160MIPS)•Instructions With a32-Bit Long Word Operand• 1.5-V Core Supply Voltage(120MIPS)(1)IEEE Standard1149.1-1990Standard-Test-Access Port and •Instructions With Two-or Three-OperandBoundary Scan ArchitectureTMS320C54x,TMS320are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©1999–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.。

ISL5416中文资料

ISL5416中文资料

Intersil公司的ISL5416信道可编程下变频器是专门为3G无线通信协议制造的，但也同时支持2G和2.5G标准。

在蜂窝基站的接收部分，这种四信道可编程下变频器独特的滤波器配置可把四个分立的宽带信道集成到一个线路中，并把所有的后处理功能集中起来进行一个完整的通道化处理。

这种最新CommLink系列的软件无线电从高速模数变频器接收输入的宽带信号，然后对中频至基带的信号进行调谐、滤波并抽取信号。

ISL5416有多级滤波、自动增益控制和再采样功能。

ISL5416的滤波功能可实现大于100dB的带外滤波，满足3G 的邻频功率比要求。

ISL5416已批量生产，采用256引脚BGA(1.0mm间距)封装，1,000件批量时每片57.00美元。

ISL5416四通道可编程数字下变频器目录四通道宽带可编程下变频器 3特点 3应用范围 4方框图 4管脚描述 8功能描述 11输入选择/格式模块 12时钟 12输入格式 12门控/内插模式 12多路复用输入模式 13SYNCInX的使用 13NCO/混频器 15PN码发生器 16CIC滤波器 17后端布线 19FIR滤波器部分 19AGC 21内插半带滤波器/重采样滤波器 25数据输出格式化部分 28串行数据输出 29串行数据输出时隙内容/格式寄存器 29通道布线屏蔽 29微处理器接口 30写内部寄存器 30读内部寄存器 31JTAG 32上电顺序 33一、ISL5416（四通道宽带可编程下变频器）介绍ISL5416是一种四通道宽带可编程数字下变频器（WPDC），是专门为大动态应用设计的。

比如蜂窝通信的基站，需要在很小的空间处理多个通道。

WPDC在单个封装上集成了四个通道，每个通道包括：一个NCO，一个数字混频器，多个数字滤波器，一个AGC和以个重采样滤波器。

所有的通道都可以独立编程和实时更新。

每个通道都可以选择四组数字输入总线中的任何一组。

每个调谐电路可以处理一个WCDMA通道，为了增加带宽，信道可以组成级连或者多相电路。