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RD74LVC273BFPEL中文资料

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RD74LVC273BOctal D-type Flip-Flops with ClearREJ03D0323–0100ZRev.1.00Jun. 16, 2004 DescriptionThe RD74LVC273B has eight edge trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.Features•V CC = 1.65 V to 5.5 V•All inputs V IH (Max.) = 5.5 V (@V CC = 0 V to 5.5 V)•All outputs V OUT (Max.) = 5.5 V (@V CC = 0 V)•Typical V OL ground bounce < 0.8 V (@V CC = 3.3 V, Ta = 25°C)•Typical V OH undershoot > 2.0 V (@V CC = 3.3 V, Ta = 25°C)•High Output current±4 mA (@V CC = 1.65 V)±8 mA (@V CC = 2.3 V)±12 mA (@V CC = 2.7 V)±24 mA (@V CC = 3.0 V to 5.5 V)•Ordering InformationPart Name Package Type Package Code PackageAbbreviation Taping Abbreviation(Quantity)RD74LVC273BFPEL SOP–20 pin(JEITA)FP–20DAV FP EL (2,000 pcs / reel) RD74LVC273BTELL TSSOP–20 pin TTP–20DAV T ELL (2,000 pcs / reel)Function TableInputsCLR CLK D Output QL X X LH↑H HH↑L LH↓X Q0Note:H:High levelL:Low levelX:Immaterial↑:Low to high transition↓:High to low transitionQ0:Output level before the indicated steady state input conditions were established.Pin ArrangementAbsolute Maximum RatingsItemSymbol RatingsUnitConditionsSupply voltage V CC –0.5 to 7.0V Input diode current I IK –50mA V I = –0.5 VInput voltage V I –0.5 to 7.0V –50V O = –0.5 V Output diode current I OK 50mAV O = V CC +0.5 V –0.5 to V CC +0.5Output “H” or “L”Output voltage V O –0.5 to 7.0VV CC : OFF Output current I O±50mA V CC , GND current / pin I CC or I GND 100mA Storage temperatureTstg–65 to 150°C Note:The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two ofwhich may be realized at the same time.Recommended Operating ConditionsItemSymbol RatingsUnitConditions1.5 to 5.5Data hold Supply voltage V CC 1.65 to 5.5V At operation V I 0 to 5.5CLK, CLR , D 0 to V CC Output “H” or “L”Input/Output voltageV O0 to 5.5V V CC : OFFOperating temperature Ta –40 to 85°C –4V CC = 1.65 V –8V CC = 2.3 V –12V CC = 2.7 V I OH–24mAV CC = 3.0 V to 5.5 V 4V CC = 1.65 V 8V CC = 2.3 V 12V CC = 2.7 V Output currentI OL24mA V CC = 3.0 V to 5.5 V 20V CC = 1.65 V to 2.7 V Input rise / fall time*1t r / t f10ns/V V CC = 3.0 V to 5.5 VNote:1.This item guarantees maximum limit when one input switches.Waveform: Refer to test circuit of switching characteristics.Electrical CharacteristicsTa = –40 to 85°CItemSymbol V CC (V)Min Max Unit Test Conditions1.65 to 1.95V CC × 0.65—2.3 to 2.7 1.7—2.7 to 3.6 2.0—V IH4.5 to5.5V CC × 0.7—1.65 to 1.95—V CC × 0.352.3 to 2.7—0.72.7 to 3.6—0.8Input voltageV IL4.5 to5.5—V CC × 0.3V1.65 to 5.5V CC – 0.2—I OH = –100 µA 1.65 1.2—I OH = –4 mA2.3 1.7—I OH = –8 mA 2.7 2.2—3.0 2.4—I OH = –12 mA 3.0 2.2—V OH4.53.8—I OH = –24 mA 1.65 to 5.5—0.2I OL = 100 µA 1.65—0.45I OL = 4 mA 2.3—0.7I OL = 8 mA 2.7—0.4I OL = 12 mA 3.0—0.55Output voltageV OL4.5—0.55V I OL = 24 mAInput current I IN 0 to 5.5—±5.0µA V IN = 5.5 V or GND Output leak current I OFF 0—±5.0µA V IN /V OUT = 5.5 V 2.7 to 3.6—±5.0V IN = 3.6 V to 5.5 V I CC 2.7 to 5.5— 5.0V IN = V CC or GNDQuiescent supply current∆I CC2.7 to3.6—500µAV IN = one input at (V CC –0.6)V,other inputs at V CC or GNDTa = –40 to 85°CItemSymbol V CC (V)MinTypMax Unit FROM (Input)TO (Output)1.8±0.15——55.02.5±0.2——95.02.7——150.03.3±0.3——150.0Maximum clock frequencyfmax5.0±0.5——150.0MHz1.8±0.15 1.0—21.62.5±0.2 1.0—10.52.7 1.0—8.53.3±0.3 1.5—7.5t PLH t PHL5.0±0.51.0— 6.0nsCLKQ1.8±0.15 1.0—21.62.5±0.2 1.0—10.52.7 1.0—8.53.3±0.3 2.0—7.5Propagation delay timet PHL5.0±0.51.0— 6.0nsCLRQ1.8±0.15 6.0——2.5±0.2 4.0——2.7 2.0——3.3±0.3 2.0——Setup timet SU5.0±0.52.0——ns 1.8±0.15 4.0——2.5±0.2 2.0——2.7 1.5——3.3±0.3 1.5——Hold timet h5.0±0.51.5——ns 1.8±0.159.0——2.5±0.2 4.0——2.73.3——3.3±0.3 3.3——Pulse widtht W5.0±0.53.3——ns 1.8±0.15———2.5±0.2———2.7———3.3±0.3—— 1.0Between output pinsskew*1t OSLH t OSHL5.0±0.5—— 1.0ns Input capacitance C IN 3.3— 4.0—pF Output capacitance C O3.3—8.0—pF Note:1.This parameter is characterized but not tested.t OSLH = |t PLHm – t PLHn |, t OSHL = |t PHLm – t PHLn |Ta = 25°CItemSymbol V CC = (V)Min Typ Max Unit Test Conditions 1.8—25—2.5—26—3.3—28—Power dissipation capacitanceC PD5.0—32—pFf = 10 MHzTest CircuitPackage Dimensions RENESAS SALES OFFICESRenesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500 Fax: <1> (408) 382-7501Renesas Technology Europe Limited.Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United KingdomTel: <44> (1628) 585 100, Fax: <44> (1628) 585 900Renesas Technology Europe GmbHDornacher Str. 3, D-85622 Feldkirchen, GermanyTel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11Renesas Technology Hong Kong Ltd.7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong KongTel: <852> 2265-6688, Fax: <852> 2375-6836Renesas Technology Taiwan Co., Ltd.FL 10, #99, Fu-Hsing N. Rd., Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999Renesas Technology (Shanghai) Co., Ltd.26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, ChinaTel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952Renesas Technology Singapore Pte. Ltd.1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632Tel: <65> 6213-0200, Fax: <65> 6278-8001Colophon .1.0。

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HD74ALVC2G240US资料

HD74ALVC2G240US资料


Item Propagation delay time Enable time Disable time
•
VCC = 1.5±0.1 V
Symbol tPLH tPHL tZH tZL tHZ tLZ Min 2.0 2.0 2.0 Typ Max 7.0 7.0 7.0 Unit ns ns ns Test conditions CL = 15 pF CL = 15 pF CL = 15 pF FROM (Input) A OE OE TO (Output) Y Y Y
Rev.1, Jan. 2002, page 5 of 13
HD74ALVC2G240
Switching Characteristics
(Ta = −40 to 85°C) • VCC = 1.2 V
Symbol tPLH tPHL tZH tZL tHZ tLZ Min Typ 5.5 6.5 4.5 Max Unit ns ns ns Test conditions CL = 15 pF CL = 15 pF CL = 15 pF FROM (Input) A OE OE TO (Output) Y Y Y
mA mA mA mA mW °C
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
MC74ACT273MG资料

MC74ACT273MG资料

MC74AC273, MC74ACT273Octal D Flip−FlopThe MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW−to−HIGH clock transition, is transferred to the corresponding flip−flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.Features•Ideal Buffer for MOS Microprocessor or Memory •Eight Edge-Triggered D Flip−Flops •Buffered Common Clock•Buffered, Asynchronous Master Reset•See MC74AC377 for Clock Enable Version •See MC74AC373 for Transparent Latch Version •See MC74AC374 for 3-State Version •Outputs Source/Sink 24 mA•′ACT273 Has TTL Compatible Inputs •Pb−Free Packages are Available*Pinout: 20−Lead Packages Conductors(Top View)H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial= LOW-to-HIGH Clock Transition*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.See general marking information in the device markingsection on page 6 of this data sheet.DEVICE MARKING INFORMATIONFigure 1. Logic Diagram1234567CPMRNOTE:That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.MAXIMUM RATINGSSymbol ParameterValue Unit V CC DC Supply Voltage (Referenced to GND)− 0.5 to + 7.0V V IN DC Input Voltage (Referenced to GND)− 0.5 to V CC + 0.5V V OUT DC Output Voltage (Referenced to GND)− 0.5 to V CC + 0.5V I IN DC Input Current, per Pin±20mA I OUT DC Output Sink/Source Current, per Pin ±50mA I CC DC V CC or GND Current per Output Pin ±50mA T stgStorage Temperature− 65 to + 150°CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.RECOMMENDED OPERATING CONDITIONSSymbol ParameterMin Typ Max Unit V CC Supply Voltage′AC 2.0 5.0 6.0V ′ACT4.55.0 5.5V in , V outDC Input Voltage, Output Voltage (Ref. to GND)0−V CC Vt r , t fInput Rise and Fall Time (Note 1)′AC Devices except Schmitt Inputs V CC @ 3.0 V−150−V CC @ 4.5 V −40−ns/V V CC @ 5.5 V −25−t r , t f Input Rise and Fall Time (Note 2)′ACT Devices except Schmitt Inputs V CC @ 4.5 V −10−ns/V V CC @ 5.5 V−8.0−T J Junction Temperature (PDIP)−−140°C T A Operating Ambient Temperature Range −402585°C I OH Output Current − High −−−24mA I OLOutput Current − Low−−24mA 1.V IN from 30% to 70% V CC ; see individual Data Sheets for devices that differ from the typical input rise and fall times.2.V IN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.DC CHARACTERISTICSSymbol Parameter V CC(V)74AC74ACUnit Conditions T A = +25°C T A = −40°C to +85°CTyp Guaranteed LimitsV IH Minimum High Level Input Voltage 3.04.55.51.52.252.752.13.153.852.13.153.85V V OUT = 0.1 Vor V CC − 0.1 VV IL Maximum Low Level Input Voltage 3.04.55.51.52.252.750.91.351.650.91.351.65V V OUT = 0.1 Vor V CC − 0.1 VV OH Minimum High Level Output Voltage 3.04.55.52.994.495.492.94.45.42.94.45.4V I OUT = −50 m A3.04.55.5−−−2.563.864.862.463.764.76V*V IN = V IL or V IH−12 mAI OH−24 mA−24 mAV OL Maximum Low Level Output Voltage 3.04.55.50.0020.0010.0010.10.10.10.10.10.1V I OUT = 50 m A3.04.55.5−−−0.360.360.360.440.440.44V*V IN = V IL or V IH12 mAI OL24 mA24 mAI IN Maximum Input Leakage Current 5.5−±0.1±1.0m A V I = V CC, GNDI OLD I OHD †Minimum Dynamic Output Current 5.55.5−−−−75−75mA V OLD = 1.65 V MaxV OHD = 3.85 V MinI CC Maximum Quiescent Supply Current 5.5−8.080m A V IN = V CC or GND *All outputs loaded; thresholds on input associated with output under test.†Maximum test duration 2.0 ms, one output loaded at a time.NOTE:Note: I IN and I CC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V CC.AC CHARACTERISTICS(For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)Symbol Parameter V CC*(V)74AC74ACUnitFigureNo.T A = +25°C C L = 50 pF T A = −40°C to +85°C C L = 50 pFMin Typ Max Min Maxf max Maximum ClockFrequency3.35.090140125175−−75125−−Mhz3−3t PLH Propagation DelayClock to Output3.35.04.03.07.05.512.59.03.02.514.010.0ns3−6t PHL Propagation DelayClock to Output3.35.04.03.07.05.013.010.03.52.514.511.0ns3−6t PHL Propagation DelayMR to Output3.35.04.03.07.05.013.010.03.52.514.010.5ns3−6*Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTSSymbol Parameter V CC*(V)74AC74ACUnitFigureNo.T A = +25°C C L = 50 pF T A = −40°C to +85°C C L = 50 pFTyp Guaranteed Minimumt s Setup Time, HIGH or LOWData to CP3.35.03.52.55.54.06.04.5ns3−9t h Hold Time, HIGH or LOWData to CP3.35.0−2.0−1.01.01.0ns3−9t w Clock Pulse WidthHIGH or LOW3.35.03.52.55.54.06.04.5ns3−6t w MR Pulse WidthHIGH or LOW3.35.02.01.55.54.06.04.5ns3−6t rec Recovery TimeMR to CP3.35.01.51.03.52.04.53.0ns3−9*Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V.DC CHARACTERISTICSSymbol Parameter V CC(V)74ACT74ACTUnit Conditions T A = +25°CT A =−40°C to +85°CTyp Guaranteed LimitsV IH Minimum High Level Input Voltage 4.5 1.5 2.0 2.0V V OUT = 0.1 V5.5 1.5 2.0 2.0or V CC − 0.1 VV IL Maximum Low Level Input Voltage 4.5 1.50.80.8V V OUT = 0.1 V5.5 1.50.80.8or V CC − 0.1 VV OH Minimum High Level Output Voltage 4.5 4.49 4.4 4.4V I OUT = −50 m A5.5 5.49 5.4 5.4*V IN = V IL or V IH4.5− 3.86 3.76V I OH−24 mA5.5− 4.86 4.76−24 mAV OL Maximum Low Level Output Voltage 4.50.0010.10.1V I OUT = 50 m A5.50.0010.10.1*V IN = V IL or V IH4.5−0.360.44VI OL 24 mA5.5−0.360.4424 mAI IN Maximum Input Leakage Current 5.5−±0.1±1.0m A V I = V CC, GND D I CCT Additional Max. I CC/Input 5.50.6− 1.5mA V I = V CC −2.1 VI OLD I OHD †Minimum Dynamic Output Current 5.55.5−−−−75−75mA V OLD = 1.65 V MaxV OHD = 3.85 V MinI CC Maximum Quiescent Supply Current 5.5−8.080m A V IN = V CC or GND *All outputs loaded; thresholds on input associated with output under test.†Maximum test duration 2.0 ms, one output loaded at a time.AC CHARACTERISTICS(For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)Symbol Parameter V CC*(V)74ACT74ACTUnitFigureNo.T A = +25°C C L = 50 pFT A = −40°C to +85°CC L = 50 pFMin Typ Max Min Maxf max Maximum Clock Frequency 5.0125200−125−MHz3−3t PHL Propagation Delay Clock to Output 5.0 3.0 6.010 2.511.0ns3−6 t PLH Propagation Delay Clock to Output 5.0 3.0 6.511 2.512.0ns3−6 t PHL Propagation Delay MR to Output 5.0 3.07.011 2.511.5ns3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V.AC OPERATING REQUIREMENTSSymbol Parameter V CC*(V)74ACT74ACTUnitFigureNo.T A = +25°C C L = 50 pFT A = −40°C to +85°CC L = 50 pFTyp Guaranteed Minimumt s Setup Time, HIGH or LOW − Data to CP 5.0 3.0 4.5 5.0ns3−9 t h Hold Time, HIGH or LOW − Data to CP 5.0−2.5 2.0 2.0ns3−9 t w Clock Pulse Width − HIGH or LOW 5.0 2.5 4.0 4.5ns3−6 t w MR Pulse Width − HIGH or LOW 5.0 2.5 4.0 4.5ns3−6 t rec Recovery Time − MR to CP 5.0−1.0 2.0 3.0ns3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V.CAPACITANCESymbol Parameter Value Typ Unit Test ConditionsC IN Input Capacitance 4.5pF V CC = 5.0 VC PD Power Dissipation Capacitance50pF V CC = 5.0 VORDERING INFORMATIONDevice Package Shipping†MC74AC273N PDIP−2018 Units / Rail18 Units / RailMC74AC273NG PDIP−20(Pb−Free)MC74ACT273N PDIP−2018 Units / Rail18 Units / RailMC74ACT273NG PDIP−20(Pb−Free)MC74AC273DW SOIC−20WB38 Units / Rail38 Units / RailMC74AC273DWG SOIC−20WB(Pb−Free)MC74AC273DWR2SOIC−20WB1000 / Tape & Reel1000 / Tape & ReelMC74AC273DWR2G SOIC−20WB(Pb−Free)MC74AC273DTR2TSSOP−20*2500 / Tape & ReelMC74AC273DTR2G TSSOP−20*2500 / Tape & ReelMC74ACT273DW SOIC−20WB38 Units / Rail38 Units / RailMC74ACT273DWG SOIC−20WB(Pb−Free)MC74ACT273DWR2SOIC−20WB1000 / Tape & Reel1000 / Tape & ReelMC74ACT273DWR2G SOIC−20WB(Pb−Free)MC74ACT273DTR2TSSOP−20*2500 / Tape & ReelMC74ACT273DTR2G TSSOP−20*2500 / Tape & ReelMC74AC273MEL SOEIAJ−202000 / Tape & Reel2000 / Tape & ReelMC74AC273MELG SOEIAJ−20(Pb−Free)MC74ACT273M SOEIAJ−2040 Units / RailMC74ACT273MG SOEIAJ−2040 Units / Rail(Pb−Free)MC74ACT273MEL SOEIAJ−202000 / Tape & Reel2000 / Tape & ReelMC74ACT273MELG SOEIAJ−20(Pb−Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.*This package is inherently Pb−Free.MARKING DIAGRAMSSOEIAJ−2074AC273AWLYWWG 201201TSSOP−20SOIC−20WBAC 273ALYW G G1A =Assembly Location WL, L =Wafer Lot YY, Y =YearWW, W =Work Week G or G = Pb−Free Package(Note: Microdot may be in either location)74ACT273AWLYWWG 201201ACT 273ALYW GG1PDIP−20MC74AC273N AWLYYWWG201MC74ACT273N AWLYYWWG 201PACKAGE DIMENSIONSPDIP−20N SUFFIX CASE 738−03ISSUE ENOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.DIM MIN MAX MIN MAX MILLIMETERSINCHES A 25.6627.171.010 1.070B 6.10 6.600.2400.260C 3.81 4.570.1500.180D 0.390.550.0150.022G 2.54 BSC 0.100 BSC J 0.210.380.0080.015K 2.80 3.550.1100.140L 7.62 BSC 0.300 BSC M 0 15 0 15 N0.51 1.010.0200.040____E 1.27 1.770.0500.070F 1.27 BSC 0.050 BSCPACKAGE DIMENSIONSSOIC−20 WB DW SUFFIX CASE 751D−05ISSUE GDIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION:MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.6.400.252−−−−−−TSSOP−20D5 SUFFIX CASE 948E−02ISSUE BPACKAGE DIMENSIONSSOEIAJ−20M SUFFIX CASE 967−01ISSUE ADIM MIN MAX MIN MAX INCHES−−− 2.05−−−0.081MILLIMETERS 0.050.200.0020.0080.350.500.0140.0200.150.250.0060.01012.3512.800.4860.5045.10 5.450.2010.2151.27 BSC 0.050 BSC 7.408.200.2910.3230.500.850.0200.0331.10 1.500.0430.0590 0.700.900.0280.035−−−0.81−−−0.032A 1H E Q 1L E _10 _0 _10 _NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).A b c D E e L M ZON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

74LVC273D,112,74LVC273DB,118,74LVC273DB,112,74LVC273DB,112,74LVC273BQ,115, 规格书,Datasheet 资料

74LVC273D,112,74LVC273DB,118,74LVC273DB,112,74LVC273DB,112,74LVC273BQ,115, 规格书,Datasheet 资料


4
芯天下--/
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times in free air VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS maximum speed performance low-voltage applications MIN. 2.7 1.2 0 0 −40 0 0
芯天下--/
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
FEATURES • Wide supply voltage range from 1.2 to 3.6 V • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50 Ω transmission lines at 85 °C • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION
TC74VHC273FT资料

TC74VHC273FT资料

TOSHIBA CMOS Digital Integrated Circuit Silicon MonolithicTC74VHC273F,TC74VHC273FT,TC74VHC273FKOctal D-Type Flip-Flop with ClearThe TC74VHC273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C 2MOS technology.It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.When the CLR input is held “L”, the Q outputs are at a low logic level independent of the other inputs.An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.Features• High speed: f max = 165 MHz (typ.) at V CC = 5 V • Low power dissipation: I CC = 4 μA (max) at Ta = 25°C • High noise immunity: V NIH = V NIL = 28% V CC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: t pLH ∼ − t pHL•Wide operating voltage range: V CC (opr) = 2 to 5.5 V • Low noise: V OLP = 0.9 V (max)• Pin and function compatible with 74ALS273WeightSOP20-P-300-1.27A : 0.22 g (typ.) TSSOP20-P-0044-0.65A : 0.08 g (typ.) VSSOP20-P-0030-0.50: 0.03 g (typ.)TC74VHC273FTC74VHC273FTTC74VHC273FKPin AssignmentIEC Logic SymbolTruth TableX: Don’t careSystem DiagramV CC 16 Q8 D8 D7 15 14 CLR1234567D2 Q2 Q3 D3 D4 Q7 8D5 13 Q6 D6 (top view)Q1 D1 12 9Q4GND 10CK11Q5 19 18 17 20 (11)(1)(3)(7)(4)D11DD3D2(13)(8)(14)D5D4(2) (6) (12) Q1 Q3 Q5 (5) (9) (15)Q2 Q4 Q6R C1CKCLR D6(17)(18)D7(16) Q7 (19)Q8D8Absolute Maximum Ratings (Note)Characteristics Symbol Rating Unit Supply voltage range V CC−0.5 to 7.0 VDC input voltage V IN−0.5 to 7.0 VDC output voltage V OUT−0.5 to V CC+ 0.5 VInput diode current I IK−20 mA Output diode current I OK±20 mA DC output current I OUT±25 mA DC V CC/ground current I CC±75 mA Power dissipation P D 180mW Storage temperature T stg−65 to 150 °CNote: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction.Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and thesignificant change in temperature, etc.) may cause this product to decrease in the reliability significantlyeven if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolutemaximum ratings and the operating ranges.Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability testreport and estimated failure rate, etc).Operating Ranges (Note)Characteristics Symbol Rating Unit Supply voltage V CC 2.0 to 5.5 VInput voltage V IN0 to 5.5VOutput voltage V OUT0 to V CC VOperating temperature T opr−40 to 85 °CInput rise and fall time dt/dv 0 to 100 (V CC= 3.3 ± 0.3 V)0 to 20 (V CC= 5 ± 0.5 V)ns/VNote: The operating ranges must be maintained to ensure the normal operation of the device.Unused inputs must be tied to either VCC or GND.Electrical CharacteristicsDC CharacteristicsTest Condition Ta = 25°CTa = −40 to 85°CCharacteristics SymbolV CC (V)Min Typ.Max Min MaxUnitHigh-level input voltageV IH⎯2.03.0 to 5.5 1.50V CC × 0.7⎯ ⎯ ⎯ ⎯1.50 V CC × 0.7⎯ ⎯VLow-level input voltageV IL⎯2.03.0 to 5.5 ⎯ ⎯⎯ ⎯0.50 V CC × 0.3⎯ ⎯0.50V CC × 0.3VI OH = −50 μA2.03.04.5 1.9 2.9 4.4 2.0 3.0 4.5⎯ ⎯ ⎯ 1.9 2.9 4.4 ⎯ ⎯ ⎯ High-level output voltageV OHV IN= V IH or V ILI OH = −4 mA I OH = −8 mA3.04.5 2.583.94⎯ ⎯⎯ ⎯2.483.80⎯ ⎯VI OL = 50 μA2.03.04.5 ⎯ ⎯ ⎯ 0.0 0.0 0.00.1 0.1 0.1 ⎯ ⎯ ⎯ 0.1 0.1 0.1 Low-level output voltageV OLV IN= V IH or V ILI OL = 4 mA I OL = 8 mA3.04.5 ⎯ ⎯ ⎯ ⎯ 0.36 0.36⎯ ⎯ 0.440.44VInput leakage currentI IN V IN = 5.5 V or GND 0 to 5.5 ⎯ ⎯±0.1⎯±1.0μA Quiescent supply currentI CCV IN = V CC or GND5.5⎯⎯ 4.0 ⎯ 40.0μATiming Requirements (input: t r = t f = 3 ns)AC Characteristics (input: t r= t f= 3 ns)Note 1: Parameter guaranteed by design.t osLH= |t pLHm− t pLHn|, t osHL= |t pHLm− t pHLn|Note 2: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Average operating current can be obtained by the equation:I CC (opr)= C PD·V CC·f IN+ I CC/8 (per bit)And the total C PD when n pcs.of flip flop operate can be gained by the following equation:C PD (total) = 22 + 9·nNoise Characteristics (input: t r= t f= 3 ns)Test Condition Ta = 25°CUnit Characteristics SymbolV CC (V)Typ. MaxQuiet output maximum dynamic V OL V OLP C L= 50 pF 5.0 0.5 0.8 V Quiet output minimum dynamic V OL V OLV C L= 50 pF 5.0 −0.5 −0.8VMinimum high level dynamic inputV IHD C L= 50 pF 5.0 ⎯ 3.5 V voltageMaximum low level dynamic inputV ILD C L= 50 pF 5.0 ⎯ 1.5 V voltageInput Equivalent CircuitWeight: 0.22 g (typ.)Weight: 0.08 g (typ.)Weight: 0.03 g (typ.)RESTRICTIONS ON PRODUCT USE20070701-EN GENERAL •The information contained herein is subject to change without notice.•TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. 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