■DESCRIPTIONSThe FUJITSU MB90920 Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc.The instruction set retains the same AT architecture as the FUJITSU original F2MC-8L and F2MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing.In addition, a 32-bit accumulator is built in to enable long word processing.■FEATURES•ClockBuilt-in PLL clock frequency multiplication circuit.Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 4 times of oscillation clock(for 4MHz oscillation clock, 4Hz to 16MHz).Operation by sub-clock(up to 50KHz : 100KHz oscillation clock divided by 2).(Continued)■PACKAGESMB90920 Series2•16-bit input capture (4 channels)Detects rising, falling, or both edges.16-bit capture register × 4Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.•16-bit reload timer (2 channels)16-bit reload timer operation (select toggle output or one-shot output)Event count function selection provided•Real Time Watch timer (main clock)Operates directly from oscillator clock.Compensates for oscillator deviationRead/write enabled second/minute/hour/date registerSignal interrupt•16-bit PPG (3channels)Output pins (3) , external trigger input pin (1)Output clock frequencies : f CP, f CP/22, f CP/24, f CP/26•Delay interruptGenerates interrupt for task switching.Interruptions to CPU can be generated/deleted by software setting.•External interrupts (8 channels)8-channel independent operationInterrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.•A/D converter10-bit or 8-bit resolution × 8 channels (input multiplexed)Conversion time : 2.6µs (at f CP= 16 MHz)External trigger startup available (P50/INT0/ADTG)Internal timer startup available (16-bit reload timer 1)•UART(LIN/SCI) (2 channels)Equipped with full duplex double bufferClock-asynchronous or clock-synchronous serial transmission is available•SIO (1 channels)Clock synchronized data transmission.LSB-first or MSB-first data transmission selection are available.•CAN interfaceConforms to CAN specifications version 2.0 Part A and B.Automatic resend in case of error.Automatic transfer in response to remote frame.16 prioritized message buffers for data and messages for data and IDMultiple message supportReceiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masksSupports up to 1 MbpsCAN WAKEUP function (connects RX internally to INT0)•LCD controller/driver (32 segment x 4 common)Segment driver and command driver with direct LCD panel (display) drive capability•Low voltage/Program Looping detect resetAutomatic reset when low voltage is detectedProgram Looping detection function(Continued)MB90920 Series3 (Continued)•Stepping motor controller (4 channels)High current output for all channels × 4Synchronized 8/10-bit PWM for all channels × 2•Sound generator8-bit PWM signal mixed with tone frequency from 8-bit reload counter.PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8kHz (at f CP= 16MHz)Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)•Input/output portsGeneral-purpose input/output port (CMOS output)- 70 ports (dual clock system)- 72 ports (single clock system)•Capable of changing input voltage for portAutomotive/CMOS-Schmitt (initial level is Automotive in single-chip mode)•Flash memory security functionProtect the content of FLASH memory (FLASH memory device only)MB90920 Series4■PRODUCT LINEUP• MB90920 SeriesPart numberParameterMB90F927MB90F927S MB90V920MB90V920S Configuration Flash ROM model Flash ROM model Evaluation model Evaluation model CPU F2MC-16LX CPUSystem clockOn-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock PLL × 4) Sub-clock pin(X0A, X1A)Yes No Yes No ROM Flash ROM 64 KB ExternalRAM 4 KB10 KBI/O port70 (sub-clock pins exist) / 72 (sub-clock pins not exist)SIO 1 ChannelLCD segment32UART UART(LIN/SCI) 2 ChannelsCAN 1 Channel16-Bit Input Capture 4 Channels16-Bit Reload Timer 2 Channels16-Bit Free Run Timer 1 ChannelReal Time Watch Timer 1 Channel16-bit PPG 3 ChannelsExternal Interrupt8 ChannelsA/D converter8 ChannelsLVD/CPU Loop Reset Yes NoStepping Motro Control 4 ChannelsSound Generator 1 ChannelFlash Security Yes NoOperation Voltage 3.7V ~ 5.5V 4.5V ~ 5.5VPackages QFP100, LQFP100PGA-299MB90920 Series5■PIN ASSIGNMENTSMB90920 Series 6MB90920 Series7■PIN DESCRIPTIONSPin no.SymbolCircuittypeDescriptionLQFP QFP8082X0AHigh speed oscillator input pin.8183X1High speed oscillator output pin.7880P92G General purpose I/O port.X0A ALow speed oscillator input pin. If no oscillator is connected,apply pull-down processing.7779P93G General purpose I/O port.X1A ALow speed oscillator output pin. If no oscillator is connected,leave open.7577RST B Reset input pin.8385P00JGeneral purpose input/output port.SIN0UART ch.0 serial data input pin.INT4INT4 external interrupt input pin.SEG24LCD segment output.8486P01EGeneral purpose input/output port.SOT0UART ch.0 serial data output pin.INT5INT5 external interrupt input pin.SEG25LCD segment output.8587P02EGeneral purpose input/output port.SCK0UART ch.0 serial clock input/output pin.INT6INT6 external interrupt input pin.SEG26LCD segment output.8688P03JGeneral purpose input/output port.SIN1UART ch.1 serial data input pin.INT7INT7 external interrupt input pin.SEG27LCD segment output.8789P04EGeneral purpose input/output port.SOT1UART ch.1 serial data output pin.SEG28LCD segment output.8890P05EGeneral purpose input/output port.SCK1UART ch.1 serial clock input/output pin.TRG16-bit PPG ch.0-2 external trigger input pin.SEG29LCD segment output.MB90920 Series 8MB90920 Series9(Continued) Pin no.SymbolCircuittypeDescriptionLQFP QFP4547P51KGeneral purpose input output port.INT1INT1 external interrupt input pin.SI SIO data input pin.4648P52GGeneral purpose input output port.INT2INT2 external interrupt input pin.SO SIO data ouput pin.5052P53GGeneral purpose input output port.INT3INT3 external interrupt input pin.SCK SIO clock input pin.52 to 5554 to 57P70 to P73HGeneral purpose input output ports.PWM1P0PWM1M0PWM2P0PWM2M0Stepping motor controller ch.0 output pins.57 to 6059 to 62P74 to P77HGeneral purpose input output ports.PWM1P1PWM1M1PWM2P1PWM2M1Stepping motor controller ch.1 output pins.62 to 6564 to 67P80 to P83HGeneral purpose input output ports.PWM1P2PWM1M2PWM2P2PWM2M2Stepping motor controller ch.2 output pins.67 to 7069 to 72P84 to P87HGeneral purpose input output ports.PWM1P3PWM1M3PWM2P3PWM2M3Stepping motor controller ch.3 output pins.7274P54GGeneral purpose input output port.TX0CAN interface 0 TX output pin.7375P55GGeneral purpose output port.RX0CAN interface 0 RX input pin.7476P56GGeneral purpose input output port.SGO Sound generator SG0 output pin.FRCK Free-run timer clock input pin.MB90920 Series10Note:*1 : Type C in MB90F927 and MB90F927S, type D in MB90V920 and MB90V920S.Pin no.SymbolCircuittypeDescriptionLQFP QFP7678P57GGeneral purpose input output port.SGA Sound generator SGA output pin.28 to 3130 to 33V0 to V3 LCD controller /driver reference power supply pins.56, 6658, 68DV CCHigh current output buffer with dedicated power supply input pins(pin numbers 54-57, 59-62, 64-67, 69-72) .51, 61, 7153, 63, 73DV SSHigh current output buffer with dedicated power supply GND pins(pin numbers 54-57, 59-62, 64-67, 69-72) .3234AV CC A/D converter dedicated power supply input pin.3537AV SS A/D converter dedicated GND supply pin.3335AVRH A/D converter Vref + input pin.47484950MD0MD1C Test mode input pins. Connect to V CC.4951MD2C/D*1Test mode input pin. Connect to V SS.2527CExternal capacitor pin. Connect an 0.1 µF capacitor between thispin and V SS.21, 8223, 84V CC Power supply input pins.9, 40, 7911, 42, 81V SS GND power supply pins.■I/O CIRCUIT TYPE(Continued)(Continued)(Continued)■HANDLING DEVICESPrecautions for Handling Semiconductor Devices•Strictly observe maximum rated voltages (prevent latchup)When CMOS integrated circuit devices are subjected to applied voltages higher than V CC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than V SS, or when voltages in excess of rated levels are applied between V CC and V SS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-conductor devices, always take sufficient care to avoid exceeding maximum ratings.Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AV CC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DV CC) do not exceed the digital power supply (V CC) .Once the digital power supply (V CC) is switched on, the analog power (AV CC,AVRH) and dedicated power supply for the high current output buffer pins (DV CC) may be turned on in any sequence.•Stable supply voltageEven within the warranted operating range of V CC supply voltage, sudden fluctuations in supply voltage can cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-quencies (50 Hz to 60 Hz) should be within 10% of the standard V CC value, and voltage fluctuations that occur during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.•Power-on proceduresIn order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during power-on should be attained within 50 µs (0.2 V to 2.7 V) .•Treatment of unused pinsIf unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least2 kΩ.Any unused input/output pins should be left open in output status, or if found set to input status, they should be treated in the same way as input pins.Any unused output pins should be left open.•Treatment of A/D converter power supply pinsEven if the A/D converter is not used, pins should be connected so that AV CC= V CC, and AV SS= AVRH = V SS.•Use of external clock signalsEven when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the•Power supply pinsDevices are designed to prevent problems such as latchup when multiple V CC and V SS supply pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground.As shown in figure below, all V CC power supply pins must have the same potential. All V SS power supply pins should be handled in the same way. If there are multiple V CC or V SS systems, the device will not operate properlyIn addition, care must be given to connecting the V CC and V SS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between V CC and V SS as close to the pins as possible.•Proper sequence of A/D converter power supply analog inputA/D converter power (AV CC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply (V CC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off before the digital power supply is switched on (V CC) . In both power-on and shut-off, care should be taken that AVRH does not exceed AV CC. Even when pins which double as analog input pins are used as input ports, be sure that the input voltage does not exceed AV CC. (There is no problem if analog power supplies and digital power supplies are turned off and on at the same time.)•Handling the power supply for high-current output buffer pins (DV CC, DV SS)Always apply power to high-current output buffer pins (DV CC, DV SS) after the digital power supply (V CC) is turned on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DV CC, DV SS) before switching off the digital power supply (V CC) . (There will be no problem if high-current output buffer pins and digital power supplies are turned off and on at the same time.)Even when high-current output buffer pins are used as general purpose ports, the power for high current output buffer pins (DV CC, DV SS) should be applied to these pins.•Pull-up/pull-down resistanceThe MB90920 series does not support internal pull-up/pull-down resistance. If necessary, use external compo-nents.•Precautions for when not using a sub clock signal.If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open.•Notes on during operation when external clock is stopped.The microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.■BLOCK DIAGRAM■MEMORY MAPNote : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFF H will appear in the image from 004000H to 00FFFF H, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFF H.■I/O MAP•Other than CAN Interface (Continued)Address Register name Symbol Read/write Peripheral functionInitial value 00H Port 0 data register PDR0R/W Port 0X X X X X X X X 01H Port 1 data register PDR1R/W Port 1- - XXXXXX 02H Port 2 data register PDR2R/W Port 2X X X X X X - -03H Port 3 data register PDR3R/W Port 3X X X X X X X X 04H Port 4 data register PDR4R/W Port 4X X X X X X X X 05H Port 5 data register PDR5R/W Port 5X X X X X X X X 06H Port 6 data register PDR6R/W Port 6X X X X X X X X 07H Port 7 data register PDR7R/W Port 7X X X X X X X X 08H Port 8 data register PDR8R/W Port 8X X X X X X X X 09H Port 9 data registerPDR9R/WPort 9- - - -X X X X0A H to 0F H (Disabled) 10H Port 0 direction register DDR0R/W Port 00 0 0 0 0 0 0 011H Port 1 direction register DDR1R/W Port 1- - 0 0 0 0 0 012H Port 2 direction register DDR2R/W Port 20 0 0 0 0 0 - -∗113H Port 3 direction register DDR3R/W Port 30 0 0 0 0 0 0 0∗114H Port 4 direction register DDR4R/W Port 40 0 0 0 0 0 0 015H Port 5 direction register DDR5R/W Port 50 0 0 0 0 0 0 016H Port 6 direction register DDR6R/W Port 60 0 0 0 0 0 0 017H Port 7 direction register DDR7R/W Port 70 0 0 0 0 0 0 018H Port 8 direction register DDR8R/W Port 80 0 0 0 0 0 0 019H Port 9 direction register DDR9R/W Port 9- - - - 0 0 0 01A H Analog input enable ADERR/WPort 6, A/D1 1 1 1 1 1 1 11B H to 1F H (Disabled) 20H A/D control status register lower ADCS0R/W A/D converter0 0 0 - - - - 021H A/D control status register higher ADCS1R/W 0 0 0 0 0 0 0 -22H A/D data register lower ADCR0R 0 0 0 0 0 0 0 023H A/D data register higher ADCR1R - - - - - - 0 024H Compare clear register CPCLR R/W 16-bit free-run timer X X X X X X X X 25H R/W X X X X X X X X 26H Timer data registerTCDT R/W 0 0 0 0 0 0 0 027H R/W 0 0 0 0 0 0 0 028H Timer control status register lower TCCSL R/W 0 0 0 0 0 0 0 029HTimer control status register higher TCCSHR/W0 1 - 0 0 0 0 0(Continued)(Continued)2122(Continued) Address Register name Symbol Read/write Peripheral function Initial value 80H PWM control register 0PWC0R/WStepping motorcontroller00 0 0 0 0 - - 081H (Disabled)82H PWM control register 1PWC1R/WStepping motorcontroller10 0 0 0 0 - - 083H (Disabled)84H PWM control register 2PWC2R/WStepping motorcontroller20 0 0 0 0 - - 085H (Disabled)86H PWM control register 3PWC3R/WStepping motorcontroller30 0 0 0 0 - - 0 87H to 89H (Disabled)8A H A/D setting register 0ADSR0R/WA/D0 0 0 0 0 0 0 08B H A/D setting register 1ADSR1R/W0 0 0 0 0 0 0 0 8C H Port Input Level Select 0PIL0R/W Port Input Level Se-lect0 0 0 0 0 0 0 08D H Port Input Level Select 1PIL1R/W- - - 0 0 0 0 0 8E H to9D H*4(Disabled)9E H ROM correction control register PACSR R/WAddress matchdetection function- - - - - 0 - 0 9F H Delay interrupt/release DIRR R/W Delayed interrupt- - - - - - - 02324(Continued) C4H Serial mode register 1SMR1R/WUART(LIN/SCI) 10 0 0 0 0 0 0 0C5H Serial control register 1SCR1R/W0 0 0 0 0 0 0 0 C6HReception/Transmission data reg-ister 1RDR1/TDR1R/W0 0 0 0 0 0 0 0 C7H Serial status register 1SSR1R/W0 0 0 0 1 0 0 0 C8HExtended Communication ControlRegister 1ECCR1R/W0 0 0 0 0 0 X X C9H Extended Status Control Register 1ESCR1R/W0 0 0 0 0 1 0 0 CA H Baud Rate Generator Register 10BGR10R/W0 0 0 0 0 0 0 0 CB H Baud Rate Generator Register 11BGR11R/W0 0 0 0 0 0 0 0 CC H Watch timer control register lower WTCRL R/WReal-timewatch timer0 0 0 - - 0 0 0CD H Watch timer control register middle WTCRM R/W0 0 0 0 0 0 0 0 CE H Watch timer control register higher WTCRH R/W- - - - 0 0 0 0 CF H Subclock Control register SCCR W Subclock- - - - 0 0 0 0D0H toFF H(Disabled)1FF0H ROM correction address 0PADR0R/WAddress matchdetection functionX X X X X X X X 1FF1H ROM correction address 1PADR0R/W X X X X X X X X 1FF2H ROM correction address 2PADR0R/W X X X X X X X X 1FF3H ROM correction address 3PADR1R/W Address matchdetection functionX X X X X X X X 1FF4H ROM correction address 4PADR1R/W X X X X X X X X 1FF5H ROM correction address 5PADR1R/W X X X X X X X X Address Register name Symbol Read/write Peripheral function Initial value25(Continued)Address Register name Symbol Read/write Peripheral function Initial value3900H to 391F H (Disabled)3920H PPG0 down counter register PDCR0R 16-bit PPG 01 1 1 1 1 1 1 13921H 1 1 1 1 1 1 1 13922H PPG0 cycle setting register PCSR0W X X X X X X X X 3923H X X X X X X X X 3924H PPG0 duty setting registerPDUT0WX X X X X X X X 3925H X X X X X X X X3926H to 3927H (Disabled)3928H PPG1 down counter register PDCR1R 16-bit PPG 11 1 1 1 1 1 1 13929H 1 1 1 1 1 1 1 1392A H PPG1 cycle setting register PCSR1W X X X X X X X X 392B H X X X X X X X X 392C H PPG1 duty setting registerPDUT1WX X X X X X X X 392D H X X X X X X X X392E H to 392F H (Disabled)3930H PPG2 down counter register PDCR2R 16 bit PPG 21 1 1 1 1 1 1 13931H 1 1 1 1 1 1 1 13932H PPG2 cycle setting register PCSR2W X X X X X X X X 3933H X X X X X X X X 3934H PPG2 duty setting registerPDUT2WX X X X X X X X 3935H X X X X X X X X3936H to 3957H (Disabled)3958H Sub second data register WTBR R/W Real time watch timerX X X X X X X X3959H X X X X X X X X 395A H - - - X X X X X 395B H Second data register WTSR R/W - - 0 0 0 0 0 0395C H Minute data register WTMR R/W - - 0 0 0 0 0 0395D H Hour data register WTHR R/W - - - 0 0 0 0 0395E H Day data registerWTDRR/W0 0 - 0 0 0 0 1395F H(Disabled)3960H to396F H LCD display RAMVRAMR/WLCD controller/driver X X X X X X X X3970H(Disabled)26(Continued)Address Register name Symbol Read/write Peripheral function Initial value3971H to397F H (Disabled)3980HPWM1 compare register 0PWC10R/WStepping motorcontroller 0X X X X X X X X 3981H- - - - - -X X 3982HPWM2 compare register 0PWC20R/WX X X X X X X X 3983H- - - - - -X X 3984H PWM1 select register 0PWS10R/W- - 0 0 0 0 0 0 3985H PWM2 select register 0PWS20R/W- 0 0 0 0 0 0 0 3986H to3987H(Disabled)3988HPWM1 compare register 1PWC11R/WStepping motorcontroller 1X X X X X X X X 3989H- - - - - -X X 398A HPWM2 compare register 1PWC21R/WX X X X X X X X 398B H- - - - - -X X 398C H PWM1 select register 1PWS11R/W- - 0 0 0 0 0 0 398D H PWM2 select register 1PWS21R/W- 0 0 0 0 0 0 0 398E H to398F H(Disabled)3990HPWM1 compare register 2PWC12R/WStepping motorcontroller 2X X X X X X X X 3991H- - - - - -X X3992HPWM2 compare register 2PWC22R/WX X X X X X X X 3993H- - - - - -X X 3994H PWM1 select register 2PWS12R/W- - 0 0 0 0 0 0 3995H PWM2 select register 2PWS22R/W- 0 0 0 0 0 0 0 3996H to3997H(Disabled)3998HPWM1 compare register 3PWC13R/WStepping motorcontroller 3X X X X X X X X 3999H- - - - - -X X399A HPWM2 compare register 3PWC23R/WX X X X X X X X 399B H- - - - - -X X 399C H PWM1 select register 3PWS13R/W- - 0 0 0 0 0 0 399D H PWM2 select register 3PWS23R/W- 0 0 0 0 0 0 0 399E H to39FF H(Disabled)3A00H to3AFF HArea reserved for CAN interface 03B00H to3BFF H(Disabled)27•Initial value symbols : “0” initial value 0.“1” initial value 1.“X” initial value undetermined“-” initial value undetermined (none) •Write/read symbols : “R/W” read/write enabled “R” read only “W” write only•Addresses in the area 0000H to 00FF H are reserved for the principal functions of the MCU. Read access attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.Note:*1: P22/SEG0 to P27/SEG5 and P30/SEG6 to P35/SEG11 initially will be LCD segments output as LCD outputcontrol register LOCR1 (58H ) is “11111111B ” initially. To use Port 2 and Port 3 as the general-purpose input/output ports, please set LOCR1 to “00000000B ” to disable the LCD segment output first.3C00H to 3CFF H Area reserved for CAN interface 03D00H to 3DFF H (Disabled) 3E00H to 3EFF H(Disabled)Address Register nameSymbolRead/write Peripheral functionInitial value28•I/O Map for CAN Interface(Continued) Address Register name SymbolRead/writeInitial value000040HMessage buffer valid area BVALR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000041H000042HTransmission request regHi ister TREQR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000043H000044HTransmission cancel register TCANR (W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000045H000046HTransmission completed register TCR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000047H000048HReceiving completed register RCR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000049H00004A HRemote request receiving register RRTRR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00004B H00004C HReceiving overrun register ROVRR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00004D H00004E HReceiving interrupt enable register RIER (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00004F H003C00HControl status register CSR(R/W, R) 0 0 - - - 0 0 00 - - - - 0 - 1 003C01H003C02HLast event indicator register LEIR (R/W) - - - - - - - -0 0 0 - 0 0 0 0 003C03H003C04HRX/TX error counter RTEC (R) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 003C05H003C06HBit timing register BTR (R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 003C07H003C08HIDE register IDER (R/W) XXXXXXXX XXXXXXXX 003C09H003C0A HTransmission RTR register TRTRR (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 003C0B H003C0C HRemote frame receiving wait register RFWTR (R/W) XXXXXXXX XXXXXXXX 003C0D H003C0E HTransmission interrupt enable register TIER (R/W) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 003C0F H29(Continued)Address Register name SymbolRead/writeInitial value003C10H Acceptance mask select register AMSR (R/W)XXXXXXXXXXXXXXXX 003C11H 003C12H XXXXXXXX XXXXXXXX 003C13H 003C14H Acceptance mask register 0AMR0 (R/W)XXXXXXXXXXXXXXXX 003C15H 003C16H XXXXX- - -XXXXXXXX 003C17H 003C18H Acceptance mask register 1AMR1 (R/W)XXXXXXXXXXXXXXXX 003C19H 003C1A H XXXXX- - -XXXXXXXX003C1B H003A00Hto 003A1F H General purpose RAM (R/W) XXXXXXXX to XXXXXXXX003A20H ID register 0IDR0(R/W)XXXXXXXXXXXXXXXX 003A21H 003A22H XXXXX- - -XXXXXXXX 003A23H 003A24H ID register 1IDR1(R/W)XXXXXXXXXXXXXXXX 003A25H 003A26H XXXXX- - -XXXXXXXX 003A27H 003A28H ID register 2IDR2(R/W)XXXXXXXXXXXXXXXX 003A29H 003A2A H XXXXX- - -XXXXXXXX 003A2B H 003A2C H ID register 3IDR3(R/W)XXXXXXXXXXXXXXXX 003A2D H 003A2E H XXXXX- - -XXXXXXXX 003A2F H 003A30H ID register 4IDR4(R/W)XXXXXXXXXXXXXXXX 003A31H 003A32H XXXXX- - -XXXXXXXX 003A33H30(Continued) Address Register name SymbolRead/writeInitial value003A34HID register 5IDR5 (R/W)XXXXXXXX XXXXXXXX 003A35H003A36HXXXXX- - -XXXXXXXX 003A37H003A38HID register 6IDR6 (R/W)XXXXXXXX XXXXXXXX 003A39H003A3A HXXXXX- - -XXXXXXXX 003A3B H003A3C HID register 7IDR7 (R/W)XXXXXXXX XXXXXXXX 003A3D H003A3E HXXXXX- - -XXXXXXXX 003A3F H003A40HID register 8IDR8 (R/W)XXXXXXXX XXXXXXXX 003A41H003A42HXXXXX- - -XXXXXXXX 003A43H003A44HID register 9IDR9 (R/W)XXXXXXXX XXXXXXXX 003A45H003A46HXXXXX- - -XXXXXXXX 003A47H003A48HID register 10IDR10 (R/W)XXXXXXXX XXXXXXXX 003A49H003A4A HXXXXX- - -XXXXXXXX 003A4B H003A4C HID register 11IDR11 (R/W)XXXXXXXX XXXXXXXX 003A4D H003A4E HXXXXX- - -XXXXXXXX 003A4F H003A50HID register 12IDR12 (R/W)XXXXXXXX XXXXXXXX 003A51H003A52HXXXXX- - -XXXXXXXX 003A53H31(Continued)Address Register name SymbolRead/writeInitial value003A54H ID register 13IDR13 (R/W)XXXXXXXXXXXXXXXX 003A55H 003A56H XXXXX- - -XXXXXXXX 003A57H 003A58H ID register 14IDR14 (R/W)XXXXXXXXXXXXXXXX 003A59H 003A5A H XXXXX- - -XXXXXXXX 003A5B H 003A5C H ID register 15IDR15 (R/W)XXXXXXXXXXXXXXXX 003A5D H 003A5E H XXXXX- - -XXXXXXXX 003A5F H 003A60H DLC register 0DLCR0 (R/W) - - - -XXXX - - - -XXXX 003A61H 003A62H DLC register 1DLCR1 (R/W) - - - -XXXX - - - -XXXX 003A63H 003A64H DLC register 2DLCR2 (R/W) - - - -XXXX - - - -XXXX 003A65H 003A66H DLC register 3DLCR3 (R/W) - - - -XXXX - - - -XXXX 003A67H 003A68H DLC register 4DLCR4 (R/W) - - - -XXXX - - - -XXXX 003A69H 003A6A H DLC register 5DLCR5 (R/W) - - - -XXXX - - - -XXXX 003A6B H 003A6C H DLC register 6DLCR6 (R/W) - - - -XXXX - - - -XXXX 003A6D H 003A6E H DLC register 7DLCR7 (R/W) - - - -XXXX - - - -XXXX 003A6F H 003A70H DLC register 8DLCR8 (R/W) - - - -XXXX - - - -XXXX 003A71H 003A72H DLC register 9DLCR9 (R/W) - - - -XXXX - - - -XXXX 003A73H 003A74H DLC register 10DLCR10(R/W)- - - -XXXX- - - -XXXX 003A75H。
