nandflash命名规则大全(三星,海力士,美光)

1. H yn ix SDRAM :HY57V281620ETP-HHY XX X XX XX X X HYNIX MEMORYPRODUCT FAMIL¥57 :SDRAMPROCESS & POWERSUPPLYV : VDD=3.3V & VDIX1=3.3VY : VDD^3.0V & VDDQ=3,0VU : VDD=2.5V & VDDQ=2.5VW : VDD-2.5V &甘DDQ二3 : Vt)D= L.BV B L VDDQ= l.SVDCNSITZ16 : 16M32 : 32M64 : &4M28 : UflM2A : 128M withTZSF56 : 256M5A : 256M with TCSR12 :512MORGANIZATION斗：X4g : x816 ；X1632 : X32#of BANK1 i 2Bdnk&2 :斗Banks XX X X X-XX XTEMPERATUREBlank : Com mere ia 1(01? -70T) E :Extended ('25r-S5D 1:Industrial (*40r-S6'C)SPEED5 : ZOOMHZ55 : 183MHzS : 166MHz7 : 143MHzK : PC13X CL2H : PC®,CL38 : 125MHzr ; FC100f CL2s : PC 100, CL310 : 100MHzPACKAGE MATERIALBLANK : NormalP: Lead freeH : Halogen freeR : Lead & Haloge n freePACKAGE TYPET : TSOPS : Stack Package [Hynix)K ；stack Package (M & T)J : Stack Package f Others)W : KGDPOWER CONSUMPTIONBLANK ; Normal PowerL : Low PowerS : Super Low PowerINTERFACE0 : LVTTL1 : SSTL_3DIE GENERATION Ichor Cheong-juBlank:1st Ger,H:1st Gen. A:2nd Gen.HA:2nd Gen. 0:3rd Gen,HB:3rd Gen. C:4th Gen.HC:抽Gen, D:Sth Gen.HG::Sth Gen. E:6th Gen.2. H yn ix DDRAM : H Y5DU56822BT-HHYXXXXXXXXXXXXXXXXIIYNIX MEMORYPRODUCE FAMILY5D : DD^ SDRAMs5P : DD^-DPROCESS & POWER SUPPLYV : VDD = 3 3V &HDOQ=2,5VU : VDD-2.5V & VDDQ-2.5VW 1 VDD-2.SV & VDDQ-L.aVS ；VDD^I.&V & VDDQ-1.8VDFNSITYXi RFFRFSHS464M, 4K Ref.6664亂2K. Ref.2812SM, 4K RflL56256M「SK Ref”12512M f 3K Ref.1G1G SK 树.ORGANIZATIONPACKAGEI JSOPQ : LQFPF :FBGAS : Stack PkG^Fynix)K : Stack PKG+(M&T)J : Stack PKG^omers)All DDR 5 DRAM 5 fol low above Fart Num be line System s wee nt HY5DV65152 27C-senes POWER CONSUMPTIONINTERFACE1 : SSTL_32 : SSTL_23 ：SSTL_lflBlank : NormalL : LOW PowerDIE GENERATIONBlank : LstGen,A : 2nd Gen.& : 3rd Gen.C : 4th Gen.1 E:industnal leyipeiTitUR:Extended leTiperatureSPEED 2t5 :375MH204DDR400 3-4-42& : 350MHz043IDDR400 3-3-3 3044nDR401 4-4-4 33 ；W0MH7D54DPIR533 4-4-4 36 : 275MHz055DDR533 5-5-5 4:J50MHI J DOR333斗3 : 233Mdz M DDR266 2-2-2晒：222MHs r IDDR266A5:2DOM-IZ H DDR266B65 : 183M-II:166M-I21DDR200PACKAGF MATFRTAIBlank : NormalP : Pbfr&eH : HdlogEn freeR : Pb & halogen free4 : x48 : xe16 : xie32 : x32# Of Bank1 ; 25anks2 : Banks3 ; DDankiT^iniwAturt13.SAMSUNG SDRAM: K4S561632H-UC75Sync DRAM Code lnformation(1/2)Last Updated : August 2006K 4 XXXXXXXX - XXXXXXX1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1810. Generation M : 1st Generation A : 2nd Generation B : 3rd Generation C : 4th Generation D : 5in Generation E : 6th Generation F 7th Generation G : 8th Generation H 9th Generation 1:10th Generation K . 12lh Genera lion :11.12. Package 2 N : STSOP2 :T : TSOP2Li : TSOP2 (Lead-"ree) i V : STSOP2 (Lead-Free} 13. Temp, PowerC : Commercial, Normal ( 0^370 *C )；L : Commercial, Low ( Ot ； - 70 X ；)I: Industrial, Normal (-40 *85 D ! P : Industrial, Low ( -40 U - 85 9) E : Extended, Normal (-25 匸 * 85 匸) i N : Extended, Low ( 25Z - 85 X ：)-14^16. Speed (Wafer/Chip Biz / BGD : 00 } $ 50 : 5ns55 : 5.5ns j 60 : 6ns | 70 : 7 ns i 75:7 5ns, PC I33 80 : 8ns1. Memory (K)2. DRAM : 43. Small Classification S:SDRAM4-5. Density, Refresh 16 :16M t 2K/32ms 28 128M, 4K 64ms 51 :512M ?8K/64ms 50.256M, 8K 64H1S 64 J34M ?4K/64ms 1G: 1G. aKG4ms6-7 .Organization 04 ：x4 06 :x4 Stack 07 :x8 Stack 08 :x8 16 ：x16 32 :x32S. Bank 2 : 2 Banlk 3 ; 4 BurU9. IrUrfmc 创 VDD, VDDQ 2 : LVTTL. 3.3V r 3.3V L : ILVCMOS, 2 5V, 2.5V4.SAMSUNG DDRAM: K4H561638F-UCB3DDR SDRAM Code lnformation(1/2)Last Updated : August 2006K4XXXXXXXX 二XXXXXXX1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 181. Memory (K]2. DRAM: 43. Small Cla«*ificaticnH : DDR SDRAM46” Density, Refresh 28: 123Mb, 4K'64ms51 : 512 Mb, SK 64ms 56: 256Mb P 8K r64ms1G:1Gb, 8K/64ms2G ：2Gb, 8如msG^7. OrganizationOJ :x408:x816:X1632 : x3S06 : M Stack07 : x8 Stack8. Bank3 : ^BankInterface, VDD, VDDQ 8: SSTL 2, 2,5V, 2.5V 10. GenerationM : 1st GeneraticnA : 2nd GenerationB : 3rd GonorationC : 4th GenerationD : 5th GenerationE : 6th GonerationF : 7th Gererat onG : 8th GenerationH : 9th Generation 12. Package T： TSOP2U : TSOP2 I Lead Free )N : sTSOP2V : sTSOP2 ( Lead Free )G : FBGAZ : FEGA t Le^id Free13. Temp. PowerC : Commercial. Normal ・ 0匕FOPL : Commerciol, LowI: Industria, NormalP : Industnal, Low(Ot )(-40C 05C)(^01 - BE Y))14-16. Speed (Wafer Chip Biz/BCD: 00)CC : DDR4Q0 ( 200MHz © CL=3f 1RCD=3, tRP=3 ) B3 : DDR333 ( 166MHz @ CL=2 5 tRCD=3, tRP=3 ) M : DDR266 (133MHz @ CL=2, tRCDW tRP=2 ) A2 EDR266 ( 133MHz @CL=2. IRCD=3, tRP=3 ) E0 :DDR266 ( 133MHz @ CL=2.5 tRCD=3, tRP=3 )5.SPANSION: S29GL032M90TAIR30S20G 、阳 MW T A I HI 0L Packing Typ* 0 - T»y吉二 7'inch Tap? And 矗也 9-13-inch Tap* and R%---------- M «d«| N umbaiFil - ^'>16. V C , ^3O-J6V, h 巾诫試日曲却&5 鹽Mor 换恪出机1砧御 WP W 'AGG S V ILR2= M AA 怙 V cr =3.(i^ 3,6 V, U nrftxm wrtor fi^> ICQ IchM&ttaddws wstnr 卩心却胡 伸的WP*：ACC=V|LR3= xSiiie,先」亍3 0-3.6 X Top bwt j«dor 如top two 问dr ・i* 詢加「* prabKt#d wh«riWP#>0C=V|LFM M 肉Jk*氐 %尹Q ・33、Bottwn bwtiidor 曲ic 已 b^n<v 1*0 add 冲即p 闻beebed 麻n WP ^ACCiV| L理能 KlE t Vcc-2.7 - 3甫 v €6-bdl FBGA, tep boot “Mor cMw * W4= K 16T V (JQ =2.7 *3.6 * S&bkll FBGA, bottom boot MCtcxW arrJ W4 日權 htcympHUt 畑曲*鬱M hi valkJ 谕 han-,fe<?1i wly------------------ T smp»r atur» Ran^aI - IrKiKtiial t-<rv ID +4■尹5-------------------------- P ackage Maierial SetA =曲Mid F = PI>F TB ®--------------------------------- P ackage TypeT = Thin Simsdl CXrlliria Packaf]^ (TSOP) Slsndand PinoulB - Fin^pilch B P II Grid Aney Hackege F m F“「t 初d BfllL-Grid M 紗 R JI *科*------------------------------------------ S peed OptionSee Prwd'ucr口r 总wde on 闫gm Q and V B I M I CombiiEdontE belcw--------- Devie* NijmlwrjDvteviprioH32 U ■淨 bit Ppfl&T Mod? Fl* eh Mnciry Mflrxjf9^tui?d icir*g NX 1 nm Mirror Bit™ Pioc&ii TeUinology, 3.0 Vi-lt- :-nk R?ftd,Program* Er*和T&b-le I. S29GL032M Ordering Option*S29GL032N90 T A I 01X PACK ING TYPE0 = Tea/2 = 7-inch Tape «nd Reel3 = 13-inch Tape and Reel --------- M ODEL NUMBER01 s M 8/X 16. V QQS V IQS 2.7-3 6 V. Unrtocm sector. WP 仰AGC = V tL protects highest addrewed sector 2 = x&/x 怡.s V QS 2.7 V. IWfocm sector. WP"A8 = pvot^cts lox 叙 acHr^s^d wclor 03 = x8/x 16, Vcc =27 - 3 6 V. Top boot sector. WP^'ACC = prolocts top Uo dddr^Md wctocs 04 = x8/x 16, V QQ = 2.7-3.6 V, Bottom bootsector, WR*/ACC = V|Lprotects ixrttcxn two addressed &ecfexs V1 = x&x 16, V^c = 2.7 - 3.6 V Vjo = 1 65 - 3.6 Uribcnn eector. WP*ACC = Vn pfotecls hi ghedsector V2 = x&/x 16. V QC = 2.7 -3.6 V Vio= 1.65 - 3.6 V, Uniform sector, WP^ACC = Y|L protectsaddressed sector---------------- T EMPERATURE RANGEI = lrdustrial(^0e Cto^ft5°C) ---------------------- PACK AGE MATERIA L SET A = Suif>tard(htote4)F = Pb ・Fw---------------------------- P ACKAGE TYPET ■ Thin Sn \All Outtn^ Package (TSOP) StAhdftrd PinoutB ■ Fint -pitch Bell-GrrtArray Pewka 旷 F ■ F^rtrfi«l B A II -Grid Army P M I CAO & ------------------------------------ S PEED OPTIONSee Product Sdecior Gude and Vfilid C^tnbnaitore (90«®0 ne, 11 «110 n®----------- DEYICE NUMBER/DESGRIPTIONS29GL032N32 Mejabit P»g?-IAxle* Flash Memory Manufeetiured using 110 rm MhrcxBiP ProoeessTechr»bgy. 9.0 Volt-coly R 心.Program, ard E IQMMoips1. Type 0is standard gdfgZw TSOPgG0 Z(电d inTypes 0 and3; BGAs can bepadredm 知w 0, 2, or 3.2. TSOPpAckpge o 祕6 pa&M 〃网naftv fro/n ar 如yparf number.3. BGA package making emits leading S29 and pecRMip fype teemoftiering pan numbet.4. Contact bca/ safes for o/aiiabiUfy Ibr Leaded •知 mo parts.Valid Combin&tiomV A M ConbinAtions list configurations ptann^d to be supported in glume tor this device. Consdt your local &ako office lo confirm availability ci specific valid axibinatfons and lo cheGk ca newly released Gcmbmaticfis.02 2PACKING TYPE 0 = Tray2 = 7-inch Tap 老 ad 3=13-inch Tape and R«lMODEL NUMBER01 = x&«x1 & Vg= V JQ = 2.7 — 3.G V, Uniform sector, WPdACC = % protects highest a<Hre^sed sector =xA^xIG. Vcc= Vi© =2.7-3.6 V, Uniform sector, WP*AGC = % protects lo ・wsiaUr^sscd wctor =x&*x1^ V Q ^= 5.7 —3.6 V, T>p boot sector, WP ・MCC =\7|^ protects top two addressed sectors =xflrtdG. V QC =2.7 -3.6 V, Bottom boot sector, WPWAGC =Y|L protects two acWre<s8iKl sectors =xl€y V QQ = 27 -3.6 V, Uniform sector, WP ・=V|L protects hi^ecst addressed sector =K 1& Vc*= 27 -3.6 V. Unifoimsector, WP ・=V|Lprotecte lowestacMfeesed $@cto«=K 8/X (§ V QQ =2.7-3.6V, V JQ = 1.65 - 3.6 V f Unitorm aectoc, WP*/ACC = Vg_ pfotecls highest addressed sector =V QQ = 27- 3.6 V, V|O = 1.6S ・ 3.6 V. UnW&nn ftwtor. WP-4/ACC = V L wtwb I CAM 削 Ml&z 輛 sector =Vcc s 2.7 -3.6 X ><10 = 1.66 - 3.6 V, Uniform sector. WP* =Y|L pr^ecto highest addfewe^l $ectx =xlG Vcc *2.7 ・ 3.G M V|(> = i 65 - 3.6 V. Umltorm<«tor. WP* =V|L pn>t4cte hwKt AddrM$«l swtorTEMPERATURE RANGE I = Incb&tr tai (-40°G to -f65e C)PACKAGE MATERIAL SET A = Standard i.Note 4) F = Pb-Free PACKAGE TYPET = Thin Small Outline Package (TSOP) Standard Pirout B = AriG-pitch EaM rd Array Pack age F = ForifiR Ball ・G 『id Array PackageSPEED OPTION&&& Predict SolectorGukte A M Malid Ccmbirwtions. (00 = 00 M . 11 = 110 ns)DEVICE NUMBERJDESCR1PTION S29GL064N, 64 Page-Mod* Fl»h MstnocyMftiuifAetu r «i using 1Wnm MirraBif 1 Procws Tichnol 咖 3.0 Wt-only Rxd, Prgwn, end ErwTable 7.1 S29GL064N Valid Combinations INote 4)S29GL064N Valid Combination*Package Detcripti^nDevice NumberOptwn Package ・ Material & Temperature Rm goModd Number Packing TypeS29GL064N9003,04,06,07TS048 (Mote 2) TSOP11 TFIV6.V7 9001,02 Q 2.3 (Ncxel)TS056(H^2) TSOP11 VI. V290 BFI 03,04 VBKCda (No(s3)Fin^-prtch BGA 90F 冋01. 02. 03, 04.LAA0&4»N C K€*3) Fortified BGA11VI. V2fk>a1. Type (fiss findard. Specify others as rdpuired; TSOPs can be peeked in Types 0 and 3: BGAs can he g 鈕d in 号阳0.2・<y 3. TSOFpQCkagQ rnanong omits poddng type dMignator from crd&ring pArtrvnt^r.BGA package tnarid^g omns i^adng S29 and pacing type afeaynaror from orcferirp pact number. Conner iocai ssCes fcx a/adatw 吟 for /ead-fram e parts.ce8 2 X07WV2V6V7Valid CombihationsValid Combinatois ist ocnfigurations planned to b4 supported 次 vdum© tor ihlg Consult your locel aekM olfce to confirm of specific valid con )tmafc>n$ wd b check on wmbinalk-ns.2 3. 4. S29GL0G4N 90 TSST39 VF 6402 ・70 XX XX 4CXXEXTKXTExx-nEnvironmental AttributeE1 = non・PbPackage ModifierK = 48 balls or leadsPackage TypeE = TSOP (typel f die up, 12mm x 20mm) B3 =TFBGA (6mm x 8mm, 0.8mm pitch) B1 =TFBGA (8mm x 10mm, 0.8mm pitch)Temperature RangeC = Commercial = 0°C to +70°CI = Industrial = -40°C to +85°CMinimum Endurance4 = 10,000 cyclesRead Access Speed70 = 70 ns90 = 90 nsHardware Block Protection1 = Bottom Boot-Block2 = lop Boot-BlockDevice Density160 = 16 Mbit320 = 32 Mbit640 = 64 MbitVoltageV = 2.7-3.6VProduct Series39 = Multi-Purpose Flash1. Envlronmental suffix “E" denotes non-Pb solder.SST non-Pb solder devices are “RoHS Complian仁。

三星F L A S H命名规则Samsung nand flash ID spec三星在nand flash存储方面也是投入了很多精力，对于pure nand flash、OneNAND（带controller的nand flash模块）以及nand的驱动都有很深层的开发。

后面说的nand都会基于Samsung的产品，包括驱动。

三星的pure nand flash（就是不带其他模块只是nand flash存储芯片）的命名规则如下：1. Memory (K)2. NAND Flash : 93. Small Classification(SLC : Single Level Cell, MLC : Multi Level Cell,SM : SmartMedia, S/B : Small Block)1 : SLC 1 Chip XD Card2 : SLC 2 Chip XD Card4 : SLC 4 Chip XD CardA : SLC + Muxed I/ F ChipB : Muxed I/ F ChipD : SLC Dual SME : SLC DUAL (S/ B)F : SLC NormalG : MLC NormalH : MLC QDPJ : Non-Muxed One NandK : SLC Die StackL : MLC DDPM : MLC DSPN : SLC DSPQ : 4CHIP SMR : SLC 4DIE STACK (S/ B)S : SLC Single SMT : SLC SINGLE (S/ B)U : 2 STACK MSPV : 4 STACK MSPW : SLC 4 Die Stack4~5. Density12 : 512M 16 : 16M 28 : 128M32 : 32M 40 : 4M 56 : 256M64 : 64M 80 : 8M 1G : 1G2G : 2G 4G : 4G 8G : 8GAG : 16G BG : 32G CG : 64GDG : 128G 00 : NONE6~7. organization00 : NONE 08 : x88. VccA : 1.65V~3.6VB : 2.7V (2.5V~2.9V)C : 5.0V (4.5V~5.5V)D : 2.65V (2.4V ~ 2.9V)E : 2.3V~3.6V R : 1.8V (1.65V~1.95V)Q : 1.8V (1.7V ~ 1.95V) T : 2.4V~3.0VU : 2.7V~3.6V V : 3.3V (3.0V~3.6V)W : 2.7V~5.5V, 3.0V~5.5V 0 : NONE9. Mode0 : Normal1 : Dual nCE & Dual R/ nB4 : Quad nCE & Single R/ nB5 : Quad nCE & Quad R/ nB9 : 1st block OTPA : Mask Option 1L : Low grade10. GenerationM : 1st GenerationA : 2nd GenerationB : 3rd GenerationC : 4th GenerationD : 5th Generation11. "─"12. PackageA : COB B : TBGAC : CHIP BIZD : 63-TBGAE : TSOP1 (Lead-Free, 1217)F : WSOP (Lead-Free)G : FBGAH : TBGA (Lead-Free)I : ULGA (Lead-Free) J : FBGA (Lead-Free)K : TSOP1 (1217) L : LGAM : TLGA N : TLGA2P : TSOP1 (Lead-Free)Q : TSOP2 (Lead-Free)R : TSOP2-R S : SMART MEDIAT : TSOP2 U : COB (MMC)V : WSOP W : WAFERY : TSOP113. TempC : Commercial I : IndustrialS : SmartMediaB : SmartMedia BLUE0 : NONE (Containing Wafer, CHIP, BIZ, Exception handling code)3 : Wafer Level 3A : Apple Bad BlockB : Include Bad BlockD : Daisychain SampleK : Sandisk BinL : 1~5 Bad BlockN : ini. 0 blk, add. 10 blkS : All Good Block0 : NONE (Containing Wafer, CHIP, BIZ, Exceptionhandling code)15. NAND-Reserved0 : Reserved16. Packing Type- Common to all products, except of Mask ROM- Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately)17~18. Customer "Customer List Reference"。

常见内存芯⽚命名常见内存芯⽚命名三星（Samsung）内存具体含义解释：例：SAMSUNGK4S283232E-TC60 SDRAMK4H280838B-TCB0 DDRK4T51163QE-HCE6 DDR2K4B1G164E-HCE7 DDR3主要含义：第1位——芯⽚功能K，代表是内存芯⽚。

第2位——芯⽚类型4，代表DRAM。

9代表NAND FLASH第3位——芯⽚的更进⼀步的类型说明，S代表SDRAM、H代表DDR、T代表DDR2、B代表DDR3、G代表SGRAM。

第4、5位——容量和刷新速率，容量相同的内存采⽤不同的刷新速率，也会使⽤不同的编号。

64、62、63、65、66、67、6A代表64Mbit的容量；28、27、2A代表128Mbit的容量；56、55、57、5A代表256Mbit的容量；51代表512Mbit的容量。

第6、7位——数据线引脚个数，08代表8位数据；16代表16位数据；32代表32位数据；64代表64位数据。

第11位——连线“-”。

第14、15位——芯⽚的速率，如60为6ns；70为7ns；7B为7.5ns(CL=3)；7C为7.5ns(CL=2)；80为8ns；10为10ns(66MHz)。

知道了内存颗粒编码主要数位的含义，拿到⼀个内存条后就⾮常容易计算出它的容量。

例如⼀条三星DDR内存，使⽤18⽚SAMSUNGK4H280838B-TCB0颗粒封装。

颗粒编号第4、5位“28”代表该颗粒是128Mbits，第6、7位“08”代表该颗粒是8位数据带宽，这样我们可以计算出该内存条的容量是128Mbits（兆数位）×16⽚/8bits=256MB（兆字节）。

注：“bit”为“数位”，“B”即字节“byte”，⼀个字节为8位则计算时除以8。

关于内存容量的计算，⽂中所举的例⼦中有两种情况：⼀种是⾮ECC内存，每8⽚8位数据宽度的颗粒就可以组成⼀条内存；另⼀种ECC内存，在每64位数据之后，还增加了8位的ECC校验码。

各种品牌存储IC简单命名介绍存储颗粒主要有这样的一些品牌：美国的Micron（美光）、德国的Infineon （英飞凌）；韩国的SAMSUNG（三星）、HY（现代）；日本的NEC（日本电气）、Hitachi(日立)、Mitsubishi(三菱)、Toshiba(东芝)；台湾的EilteMT、ESMT （晶豪）、EtronTech（钰创）、Winbond（华邦）、Mosel（茂矽）、Vanguard （世界先进）、Nanya（南亚）。

有的品牌现在已经没有被采用了，只有在SDRAM时代采用过，有的品牌在DDR 时代采用的也不多了。

显存种类主要分SD和DDR两种，有时候，他们可以从编号上区分，DDR的可能会注明“D”，SDRAM的注明“S”或者其他字母。

另外主要从管角数量上来区分，以TSOP封装来说，SDRAM的管脚数量是27x2＝54，DDR 的管脚数量为33X2=66。

美光（Micron）图1 美光芯片颗粒美光是美国第一大、全球第二大内存芯片厂商，目前显卡厂商采用它显示芯片较少，它主要供应内存OEM商，下面用上图的实例对Micron（美光）颗粒编号的简单含义作介绍：MT——Micron的厂商名称。

48——内存的类型。

48代表SDRAM；46 代表DDR。

LC——供电电压。

LC代表3V；C 代表5V；V 代表2.5V。

8M8——内存颗粒容量为8M。

A2——内存内核版本号。

TG——封装方式，TG即TSOP封装。

-75——内存工作速率，-75即133MHz；-65即150MHz。

颗粒编号MT 48LC8M8A2 TG-75，从编号上的48很容易知道这是SDRAM颗粒，采用TSOP封装方式，速度为7.5ns，单颗粒为8M，位宽8bit。

亿恒（In fineon）图2 Infineon（亿恒）颗粒Infineon是德国西门子的一个分公司，它主要生产内存颗粒。

目前，Infineon在全球排名已经跃居为第四位，超过了韩国的Hynix。

规格说明：CL=积层陶瓷电容03=0201(0603) 21=0805(2012) 42=1808(4520)05=0402(1005) 31=1206(3216) 43=1812(4532)10=0603(1608) 32=1210(3225) 55=2220(5750)14=0504(1410) 01=0306(0816) 12=0508(1220)电容容量用三位数表示，前面两位为有效数字，第三位为有效数字后"O"的位数如：105 = 10 00000 （单位pF）如果中间一位为R 则表示"."如：3R3 = 3.3pFA=常规产品 钯/银/镍屏蔽/锡 100% N=常规产品 镍/铜/镍屏蔽/锡100%G=常规产品 铜/铜/镍屏蔽/锡 100% L=低侧面产品 镍/铜/镍屏蔽/锡 100%A =阵列(2-元素) L =LICCB =阵列(4-元素) N =常规 P =自动 C=高频预留的用途第1页规格事例:I类符号EIA编码工作温度范围（℃）温度系数范围（ppm/℃）C C0G -55～+125 0±30P P2H -55～+125 -150±60R R2H -55～+125 -220±60S S2H -55～+125 -330±60T T2H -55～+125 -470±60U U2J -55～+125 -750±120L S2L -55～+125 -1000～+350II类符号EIA编码工作温度范围（℃）电容变化（?C%）A X5R -55～+85 ±15B X7R -55～+125 ±15X X6S -55～+105 ±22F Y5V -30～+85 -82～+22**系列TC电容步骤***第2页外型尺寸：特征.尺寸的大小从：从0402到2220；.PCB高可靠公差和高速自动芯片更换；.大电容范围；.大温度补偿和电压范围：从COG到Y5V和从6.3V到50V；.高可靠性性能；.高电阻端子金属；.表面贴装组件的带料和料盘尺寸表示图（值见下表）鈀 MLCC(MLCC=A鈀零件编码第12号).I类电容<10pF（I类。

nandflash及闪存命名规则大全（三星，海力士，美光等）U盘存储技术nandflash命名规则大全（三星，海力士，美光等）今天找三星闪存资料,发现了他的命名规则,发上来与大家分享下.三星的pure nand flash（就是不带其他模块只是nand flash存储芯片）的命名规则如下：1. Memory (K)2. NAND Flash : 93. Small Classification(SLC : Single Level Cell, MLC : Multi Level Cell,SM : SmartMedia, S/B : Small Block)1 : SLC 1 Chip XD Card2 : SLC 2 Chip XD Card4 : SLC 4 Chip XD CardA : SLC + Muxed I/ F ChipB : Muxed I/ F ChipD : SLC Dual SME : SLC DUAL (S/ B)F : SLC NormalG : MLC NormalH : MLC QDPJ : Non-Muxed OneNandK : SLC Die StackL : MLC DDPM : MLC DSPN : SLC DSPQ : 4CHIP SMR : SLC 4DIE STACK (S/ B)S : SLC Single SMT : SLC SINGLE (S/ B)U : 2 STACK MSPV : 4 STACK MSPW : SLC 4 Die Stack4~5. Density（注：实际单位应该是bit，而不是Byte）12 : 512M16 : 16M28 : 128M32 : 32M40 : 4M56 : 256M64 : 64M80 : 8M1G : 1G2G : 2G4G : 4G8G : 8GAG : 16GBG : 32GCG : 64GDG : 128G00 : NONE6~7. organization00 : NONE08 : x816 : x168. VccA : 1.65V~3.6VB : 2.7V (2.5V~2.9V)C : 5.0V (4.5V~5.5V)D : 2.65V (2.4V ~ 2.9V)E : 2.3V~3.6VR : 1.8V (1.65V~1.95V)Q : 1.8V (1.7V ~ 1.95V)T : 2.4V~3.0VU : 2.7V~3.6VV : 3.3V (3.0V~3.6V)W : 2.7V~5.5V, 3.0V~5.5V0 : NONE9. Mode0 : Normal1 : Dual nCE & Dual R/ nB4 : Quad nCE & Single R/ nB5 : Quad nCE & Quad R/ nB9 : 1st block OTPA : Mask Option 1L : Low grade10. GenerationM : 1st GenerationA : 2nd GenerationB : 3rd GenerationC : 4th GenerationD : 5th Generation11. "─"12. PackageA : COBB : TBGAC : CHIP BIZD : 63-TBGAE : TSOP1 (Lead-Free, 1217)F : WSOP (Lead-Free)G : FBGAH : TBGA (Lead-Free)I : ULGA (Lead-Free)J : FBGA (Lead-Free)K : TSOP1 (1217)L : LGAM : TLGAN : TLGA2P : TSOP1 (Lead-Free)Q : TSOP2 (Lead-Free)R : TSOP2-RS : SMART MEDIAT : TSOP2U : COB (MMC)V : WSOPW : WAFERY : TSOP113. TempC : CommercialI : IndustrialS : SmartMediaB : SmartMedia BLUE0 : NONE (Containing Wafer, CHIP, BIZ, Exception handling code)3 : Wafer Level 314. Bad BlockA : Apple Bad BlockB : Include Bad BlockD : Daisychain SampleK : Sandisk BinL : 1~5 Bad BlockN : ini. 0 blk, add. 10 blkS : All Good Block0 : NONE (Containing Wafer, CHIP, BIZ, Exceptionhandling code)15. NAND-Reserved0 : Reserved16. Packing Type- Common to all products, except of Mask ROM- Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately)【举例说明】K 9 G A G 0 8 U 0 M - P C B 01 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 17 18K9GAG08U0M 详细信息如下:1. Memory (K)2. NAND Flash : 93. Small Classification(SLC : Single Level Cell, MLC : Multi Level Cell,SM : SmartMedia, S/B : Small Block)G : MLC Normal4~5. DensityAG : 16G (Note: 这里单位是bit而不是byte，因此实际大小是16Gb=2GB)6. Technology0 : Normal (x8)7. Organization0 : NONE 8 : x88. VccU : 2.7V~3.6V9. Mode0 : Normal10. GenerationM : 1st Generation11. "─"12. PackageP : TSOP1 (Lead-Free)13. TempC : Commercial14. Customer Bad BlockB : Include Bad Block15. Pre-Program Version0 : None整体描述就是：K9GAG08U0M是，三星的MLC Nand Flash，工作电压为2.7V~3.6V，x8（即I/O是8位），大小是2GB（16Gb），TSOP1封装。

内存条可以通过查看内存颗粒的型号来确认其容量大小。

下面就以几个大厂的内存颗粒编码规则为例来说明内存容量的辨识方法。

三星内存颗粒目前使用三星的内存颗粒来生产内存条的厂家非常多，在市场上有很高的占有率。

由于其产品线庞大，所以三星内存颗粒的命名规则非常复杂。

三星内存颗粒的型号采用一个16位数字编码命名的。

这其中用户更关心的是内存容量和工作速率的识别，所以我们重点介绍这两部分的含义。

编码规则：K 4 X X X X X X X X - X X X X X主要含义：第1位——芯片功能K，代表是内存芯片。

第2位——芯片类型4，代表DRAM。

第3位——芯片的更进一步的类型说明，S代表SDRAM、H代表DDR、G代表SGRAM。

第4、5位——容量和刷新速率，容量相同的内存采用不同的刷新速率，也会使用不同的编号。

64、62、63、65、66、67、6A代表64Mbit 的容量；28、27、2A代表128Mbit的容量；56、55、57、5A代表256Mbit 的容量；51代表512Mbit的容量。

第6、7位——数据线引脚个数，08代表8位数据；16代表16位数据；32代表32位数据；64代表64位数据。

第11位——连线“-”。

第14、15位——芯片的速率，如60为6ns；70为 7ns；7B为7.5ns (CL=3)；7C为7.5ns (CL=2) ；80为 8ns；10 为10ns (66MHz)。

知道了内存颗粒编码主要数位的含义，拿到一个内存条后就非常容易计算出它的容量。

例如一条三星DDR内存，使用18片SAMSUNG K4H280838B-TCB0颗粒封装。

颗粒编号第4、5位“28”代表该颗粒是128Mbits，第6、7位“08”代表该颗粒是8位数据带宽，这样我们可以计算出该内存条的容量是128Mbits（兆数位）× 16片/8bits=256MB（兆字节）。

注：“bit”为“数位”，“B”即字节“byte”，一个字节为8位则计算时除以8。

Standard NAND Flash Part Numbering SystemMicron's part numbering system is available at Standard NAND Flash*MT 29F 2G 08 A A A WP - xx xx xx xx ES : AMicron Technology Design Revision (shrink)A = 1st design revision1. Single-Supply Flash29F = Single-Supply NAND Flash Production Status29H = High Speed NAND Blank = ProductionES = Engineering samples2. Density QS = Qualification samples1G = 1Gb MS = Mechanical samples2G = 2Gb4G = 4Gb Operating Temperature Range8G = 8Gb Blank = Co mmercial (0°C to +70°C)16G = 16Gb ET = Extended (–40°C to +85°C)32G = 32Gb WT = Wireless (–25°C to +85°C)64G = 64Gb128G = 128Gb Block Option (Reserved for use)256G = 256Gb Blank = Standard device3. Device Width Flash Performance08 = 8 bits Blank = Full specification16 = 16 bits4. Speed Grade (MT29H Only)Classification 15 = 133 MT/s12 = 166 MT/s5. Mark Bit/cell Die RnBA SLC 1 1 Package CodeB SLC 2 1 WP = 48-pin TSOP I (CPL version) (Pb-free)C SLC 2 1 WC = 48-pin TSOP I (OCPL version) (Pb-free)D SLC 2 2 H1 = 100-ball VFBGA (Pb-free), 12 x 18 x 1.0E SLC 2 2 H2 = 100-ball TFBGA (Pb-free), 12 x 18 x 1.2F SLC 4 2 HC = 63-ball VFBGA, 10.5 x 13 x 1.0G SLC 4 2 C2 = 52-pad ULGA, 12 x 17 x 0.4 (use TBD)J SLC 4 + 4 2 + 2 C3 = 52-pad ULGA, 12 x 17 x 0.65K SLC 8 4 C4 = 52-pad VLGA, 12 x 17 x 1.0 (SDP/DDP/QDP) Z SLC 1 NA C5 = 52-pad VLGA, 14 x 18 x 1.0 (SDP/DDP/QDP)C6 = 52-pad LLGA, 14 x 18 x 1.47 (8DP, QDP, DDP)M MLC 1 1 C7 = 48-pad LLGA, 12 x 20 x 1.47 (8DP)N MLC 2 1 SWC = 48-pin Stacked TSOP (OCPL version) (Pb-free)P MLC 2 1 SWP = 48-pin Stacked TSOP (CPL version) (Pb-free)Q MLC 2 2R MLC 2 2 Generation (M29 only)/Feature SetT MLC 4 2 A = 1st set of device featuresU MLC 4 2 B = 2nd set of device features (rev only if different than 1st set)V MLC 4 + 4 2 + 2 C = 3rd set of device features (rev only if different) W MLC 8 4 D = 4th set of device features (rev only if different)Y MLC 8 4 etc.6. Operating Voltage RangeA = 3.3V (2.70–3.60V), VccQ 3.3V (2.70–3.60V)B = 1.8V (1.70–1.95V)C = 3.3V (2.70–3.60V), VccQ 1.8V (1.70–1.95V)*Contact Micron for help differentiating between standard andnext-generation NAND offerings。

NAND Flash Code Information(1/3)Last Updated : August 2009K9XXXXXXXX - XXXXXXX11. Memory (K) 2. NAND Flash : 9 3. Small Classification (SLC : Single Level Cell, MLC : Multi Level Cell, SM : SmartMedia, S/B : Small Block) 1 : SLC 1 Chip XD Card 2 : SLC 2 Chip XD Card 3 : 4bit MLC Mono 4 : SLC 4 Chip XD Card 5 : MLC 1 Chip XD Card 6 : MLC 2 Chip XD Card 7 : SLC moviNAND 8 : MLC moviNAND 9 : 4bit MLC ODP A : 3bit MLC MONO B : 3bit MLC DDP C : 3bit MLC QDP F : SLC Normal G : MLC Normal H : MLC QDP K : SLC Die Stack L : MLC DDP M : MLC DSP N : SLC DSP O : 3bit MLC ODP P : MLC ODP Q : SLC ODP R : MLC 12-die stack S : MLC 6 Die Stack T : SLC SINGLE (S/B) U : MLC 16 Die Stack W : SLC 4 Die Stack 4~5. Density 12 : 512M 32 : 32M 64 : 64M 2G : 2G AG : 16G DG : 128G GG : 384G NG : 96G23456789 10 11 12 13 14 15 16 17 186. Technology 0 : Normal (x8) C : Catridge SIP M : moviNAND P : moviMCP Z : SSD 7. Organization 0 : NONE 6 : x161 : Normal (x16) D : DDR N : moviNAND FAB T : Premium eSSD8 : x88. Vcc A : 1.65V~3.6V B : 2.7V (2.5V~2.9V) C : 5.0V (4.5V~5.5V) D : 2.65V (2.4V ~ 2.9V) E : 2.3V~3.6V R : 1.8V (1.65V~1.95V) Q : 1.8V (1.7V ~ 1.95V) T : 2.4V~3.0V S : 3.3V (3V~3.6V/ VccQ1.8V (1.65V~1.95V) U : 2.7V~3.6V V : 3.3V (3.0V~3.6V) W : 2.7V~5.5V, 3.0V~5.5V 0 : NONE 9. Mode 0 : Normal 1 : Dual nCE & Dual R/nB 3 : Tri /CE & Tri R/B 4 : Quad nCE & Single R/nB 5 : Quad nCE & Quad R/nB 6 : 6 nCE & 2 RnB 7 : 8 nCE & 4 RnB 8 : 8 nCE & 2 RnB 9 : 1st block OTP A : Mask Option 1 L : Low grade 10. Generation M : 1st Generation A : 2nd Generation B : 3rd Generation C : 4th Generation D : 5th Generation E : 6th Generation Y : 25th Generation Z : 26th Generation16 : 16M 40 : 4M 80 : 8M 4G : 4G BG : 32G EG : 256G HG : 512G ZG : 48G28 : 128M 56 : 256M 1G : 1G 8G : 8G CG : 64G FG : 256G LG : 24G 00 : NONE-1-Part Number DecoderNAND Flash Code Information(2/3)Last Updated : August 2009K9XXXXXXXX - XXXXXXX1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1814. Customer Bad Block B : Include Bad Block D : Daisychain Sample K : Special Handling L : 1~5 Bad Block N : ini. 0 blk, add. 10 blk S : All Good Block 0 : NONE (Containing Wafer, CHIP, BIZ, Exception handling code)11. "─" 12. Package 8 : TSOP1 (Lead-Free, Halogen-Free, CU) 9 : 56TSOP1 (Lead-Free, Halogen-Free, CU) A : COB B : FBGA (Halogen-Free, Lead-Free) D : 63-TBGA E : ISM (Lead-Free, Halogen-Free) F : WSOP (Lead-Free) G : FBGA H : BGA (Lead-Free, Halogen-Free) I : ULGA (Lead-Free) (12*17) J : FBGA (Lead-Free) K : ULGA (Lead-Free, Halogen-Free) (12*17) L : ULGA (Lead-Free, Halogen-Free) (14*18) M : 52-ULGA (Lead-Free, Halogen-Free) (13*18) P : TSOP1 (Lead-Free) Q : TSOP2 (Lead-Free) R : 56-TSOP1 (Lead-Free, Halogen-Free) S : TSOP1 (Lead-Free, Halogen-Free) T : WSOP (Lead-Free, Halogen-Free) U : COB (MMC) V : WSOP W : Wafer Y : TSOP1 Z : WELP (Lead-Free) 13. Temp C : Commercial I : Industrial S : SmartMedia B : SmartMedia BLUE 0 : NONE (Containing Wafer, CHIP, BIZ, Exception handling code)15. Pre-Program Version 0 : None Serial (1~9, A~Z)-2-Part Number DecoderNAND Flash Code Information(3/3)Last Updated : August 2009K9XXXXXXXX - XXXXXXX116. Packing Type - Common to all products, except of Mask ROM - Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately) Divide Component Packing Type TAPE & REEL Other ( Tray, Tube, Jar ) Stack Module MODULE TAPE & REEL MODULE Other Packing T 0 ( Number) S P M New Marking23456789 10 11 12 13 14 15 16 17 1817~18. Customer "Customer List Reference"-3-Part Number Decoderzhangshengheng@三星 flash 命名规则如何根据 Samsung 的 Nand Flash 的芯片型号(Part Number)读懂芯片详细信息 + 举例 K9GAG08U0M 说明 【Samsung ：NAND Flash Code Information】 三星的 NAND Flash Code Information： /global/business/semiconductor/productInfo.do?fmly_id=672&partnum=K9 GAG08U0M 中的 Part Number Decoder拷贝出来如下：NAND Flash Code Information1. Memory (K) 2. NAND Flash : 9 3. Small Classification (SLC : Single Level Cell, MLC : Multi Level Cell, SM : SmartMedia, S/B : Small Block) 1 : SLC 1 Chip XD Card 2 : SLC 2 Chip XD Card 3 : 4bit MLC Mono 4 : SLC 4 Chip XD Card 5 : MLC 1 Chip XD Card 6 : MLC 2 Chip XD Card 7 : SLC moviNAND 8 : MLC moviNAND 9 : 4bit MLC ODP A : 3bit MLC MONO B : 3bit MLC DDP C : 3bit MLC QDP F : SLC Normal G : MLC Normal H : MLC QDP K : SLC Die Stack L : MLC DDP M : MLC DSP N : SLC DSP O : 3bit MLC ODP P : MLC ODP Q : SLC ODPzhangshengheng@R : MLC 12-die stack S : MLC 6 Die Stack T : SLC SINGLE (S/B) U : MLC 16 Die Stack W : SLC 4 Die Stack 4~5. Density（注：实际单位应该是 bit，而不是 Byte） 12 : 512M 16 : 16M 28 : 128M 32 : 32M 40 : 4M 56 : 256M 64 : 64M 80 : 8M 1G : 1G 2G : 2G 4G : 4G 8G : 8G AG : 16G BG : 32G CG : 64G DG : 128G EG : 256G FG : 256G GG : 384G HG : 512G LG : 24G NG : 96G ZG : 48G 00 : NONE 6. Technology 0 : Normal (x8) 1 : Normal (x16) C : Catridge SIP D : DDR M : moviNAND N : moviNAND FAB P : moviMCP T : Premium eSSD Z : SSD 7. Organization 0 : NONE 8 : x8 6 : x16 8. Vcc A : 1.65V~3.6V B : 2.7V (2.5V~2.9V) C : 5.0V (4.5V~5.5V) D : 2.65V (2.4V ~ 2.9V) E : 2.3V~3.6V R : 1.8V (1.65V~1.95V) Q : 1.8V (1.7V ~ 1.95V) T : 2.4V~3.0V S : 3.3V (3V~3.6V/ VccQ1.8V (1.65V~1.95V) U : 2.7V~3.6V V : 3.3V (3.0V~3.6V) W : 2.7V~5.5V, 3.0V~5.5V 0 : NONE 9. Mode 0 : Normal 1 : Dual nCE & Dual R/nB 3 : Tri /CE & Tri R/B 4 : Quad nCE & Single R/nB 5 : Quad nCE & Quad R/nB 6 : 6 nCE & 2 RnB 7 : 8 nCE & 4 RnB 8 : 8 nCE & 2 RnB 9 : 1st block OTP A : Mask Option 1 L : Low grade 10. Generation M : 1st Generation A : 2nd Generationzhangshengheng@B : 3rd Generation C : 4th Generation D : 5th Generation E : 6th Generation Y : 25th Generation Z : 26th Generation 11. "─" 12. Package 8 : TSOP1 (Lead-Free, Halogen-Free, CU) 9 : 56TSOP1 (Lead-Free, Halogen-Free, CU) A : COB B : FBGA (Halogen-Free, Lead-Free) D : 63-TBGA E : ISM (Lead-Free, Halogen-Free) F : WSOP (Lead-Free) G : FBGA H : BGA (Lead-Free, Halogen-Free) I : ULGA (Lead-Free) (12*17) J : FBGA (Lead-Free) K : ULGA (Lead-Free, Halogen-Free) (12*17) L : ULGA (Lead-Free, Halogen-Free) (14*18) M : 52-ULGA (Lead-Free, Halogen-Free) (13*18) P : TSOP1 (Lead-Free) Q : TSOP2 (Lead-Free) R : 56-TSOP1 (Lead-Free, Halogen-Free) S : TSOP1 (Lead-Free, Halogen-Free) T : WSOP (Lead-Free, Halogen-Free) U : COB (MMC) V : WSOP W : Wafer Y : TSOP1 Z : WELP (Lead-Free) 13. Temp C : Commercial I : Industrial S : SmartMedia B : SmartMedia BLUE 0 : NONE (Containing Wafer, CHIP, BIZ, Exception handling code) NAND Flash Code Information(2/3) K 9 X X X X X X X X - X X X X X X X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 14. Customer Bad Block B : Include Bad Block D : Daisychain Sample K : Special Handling L : 1~5 Bad Block N : ini. 0 blk, add. 10 blk S : All Good Block 0 : NONE (Containing Wafer, CHIP, BIZ, Exceptionzhangshengheng@handling code) 15. Pre-Program Version 0 : None Serial (1~9, A~Z) 16. Packing Type - Common to all products, except of Mask ROM - Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately17~18. Customer "Customer List Reference" 【举例说明】 K 9 G A G 0 8 U 0 M P C B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 K9GAG08U0M 详细信息如下: 1. Memory (K) 2. NAND Flash : 9 3. Small Classification (SLC : Single Level Cell, MLC : Multi Level Cell, SM : SmartMedia, S/B : Small Block) G : MLC Normal 4~5. Density AG : 16G (Note: 这里单位是 bit 而不是 byte， 因此实际大小是 16Gb=2GB) 6. Technology 0 : Normal (x8) 7. Organization 0 : NONE 8 : x8 8. Vcc U : 2.7V~3.6V 9. Mode 0 : Normal 10. Generation M : 1st Generation 11. "─" 12. Package P : TSOP1 (Lead-Free) 13. Temp C : Commercialzhangshengheng@14. Customer Bad Block B : Include Bad Block 15. Pre-Program Version 0 : None 整体描述就是： K9GAG08U0M 是，三星的 MLC Nand Flash，工作电压为 2.7V~3.6V，x8（即 I/O 是 8 位），大小是 2GB （16Gb），TSOP1 封装。

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.Rev 0.3 / Nov. 2006 1HY27UF(08/16)1G2A Series1Gbit (128Mx8bit / 64Mx16bit) NAND Flash1Gb NAND FLASHHY27UF081G2A HY27UF161G2ARev 0.3 / Nov. 200621Gbit (128Mx8bit / 64Mx16bit) NAND FlashDocument Title1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory Revision HistoryRevision No.History Draft DateRemark0.01Initial Draft.Dec. 28. 2005Preliminary0.11) Change NOP2) Change AC CharacteristicsMay. 18. 2006Preliminary0.21) Delete Memory array map 2) Change AC Characteristics3) Correct copy back function Oct. 02. 2006Preliminary0.31) Change 1Gb Package Type- FBGA package is added - Figure & dimension are changed 2) Delet PreliminaryNov. 23. 2006tOH Before 12After10tCStCEA tREA Before 253525After202520Rev 0.3 / Nov. 200631Gbit (128Mx8bit / 64Mx16bit) NAND FlashFEATURES SUMMARYHIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width.- Multiplexed Address/ Data- Pinout compatibility for all densitiesSUPPLY VOLTAGE- VCC = 2.7 to 3.6V : HY27UFxx1G2A Memory Cell Array= (2K+64) Bytes x 64 Pages x 1,024 Blocks = (1K+32) Bytes x 64 Pages x 1,024 BlocksPAGE SIZE- x8 device : (2K+64 spare) Bytes : HY27UF081G2A - x16 device : (1K+32 spare) Bytes : HY27UF161G2ABLOCK SIZE- x8 device: (128K + 4K spare) Bytes - x16 device: (64K + 2K spare) Words PAGE READ / PROGRAM - Random access: 25us (max.) - Sequential access: 30ns (min.) - Page program time: 200us (typ.)COPY BACK PROGRAM MODE- Fast page copy without external bufferingCACHE PROGRAM- Internal (2048+64) Byte buffer to improve the program throughputFAST BLOCK ERASE- Block erase time: 2ms (Typ.)STATUS REGISTER ELECTRONIC SIGNATURE - 1st cycle: Manufacturer Code - 2nd cycle: Device Code- 3rd cycle: Internal chip number , Cell Type, Number of Simultaneously Programmed Pages.- 4th cycle: Page size, Block size, Organization, Spare sizeSERIAL NUMBER OPTION CHIP ENABLE DON’T CARE - Simple interface sith microcontrollerDATA RETENTION- 100,000 Program/Erase cycles (with 1bit/528byte ECC) - 10 years Data RetentionPACKAGE- HY27UF(08/16)1G2A-T(P): 48-Pin TSOP1 (12 x 20 x 1.2 mm)- HY27UF(08/16)1G2A-T (Lead)- HY27UF(08/16)1G2A-TP (Lead Free)- HY27UF081G2A-S(P): 48-Pin USOP1 (12 x 17 x 0.65 mm)- HY27UF081G2A-S (Lead)- HY27UF081G2A-SP (Lead Free) - HY27UF081G2A-F(P): 63-Ball FBGA (9 x 11 x 1.0 mm)- HY27UF081G2A-F (Lead)- HY27UF081G2A-FP (Lead Free)Rev 0.3 / Nov. 200641Gbit (128Mx8bit / 64Mx16bit) NAND Flash1. SUMMARY DESCRIPTIONThe Hynix HY27UF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply.Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells.A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block.Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint.Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Pro-gram/Erase Controller automates all program and erase functions including pulse repetition, where required, and inter-nal verification and margining of data.The modify operations can be locked using the WP input pin or using the extended lock block feature described later .The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-ple memories the R/B pins can be connected all together to provide a global status signal.Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2A extended reliability of 100K pro-gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller , since the CE transitions do not stop the read operation.The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out.The HYNIX HY27UF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mmm, FBGA 9 x 11 mm.1.1 Product ListPART NUMBER ORIZATIONVCC RANGE PACKAGEHY27UF081G2A x8 2.7V - 3.6 Volt63FBGA / 48TSOP1 / 48USOP1HY27UF161G2Ax1648TSOP1Rev 0.3 / Nov. 200651Gbit (128Mx8bit / 64Mx16bit) NAND FlashIO15 - IO8Data Input / Outputs (x16 only)IO7 - IO0Data Inputs / Outputs CLE Command latch enable ALE Address latch enable CE Chip Enable RE Read Enable WE Write Enable WP Write Protect R/B Ready / Busy Vcc Power Supply Vss Ground NCNo ConnectionTable 1: Signal NamesRev 0.3 / Nov. 200661Gbit (128Mx8bit / 64Mx16bit) NAND FlashFigure 2. 48TSOP1 Contactions, x8 and x16 DeviceFigure 3. 48USOP1 Contactions, x8Rev 0.3 / Nov. 200671Gbit (128Mx8bit / 64Mx16bit) NAND FlashFigure 4. 63FBGA Contactions, x8 Device (Top view through package)Rev 0.3 / Nov. 200681Gbit (128Mx8bit / 64Mx16bit) NAND Flash1.2 PIN DESCRIPTIONPin Name DescriptionIO0-IO7IO8-IO15(1)DATA INPUTS/OUTPUTSThe IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.CLECOMMAND LATCH ENABLEThis input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE).ALEADDRESS LATCH ENABLEThis input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE).CECHIP ENABLEThis input controls the selection of the device. When the device is busy CE low does not deselect the memory.WEWRITE ENABLEThis input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WP WRITE PROTECTThe WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)operations.R/B READY BUSYThe Ready/Busy output is an Open Drain pin that signals the state of the memory.VCC SUPPLY VOLTAGEThe VCC supplies the power for all the operations (Read, Write, Erase). VSS GROUNDNCNO CONNECTIONTable 2: Pin DescriptionNOTE:1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.Rev 0.3 / Nov. 200691Gbit (128Mx8bit / 64Mx16bit) NAND FlashIO0IO1IO2IO3IO4IO5IO6IO71st Cycle A0A1A2A3A4A5A6A72nd Cycle A8A9A10A11L (1)L (1)L (1)L (1)3rd Cycle A12A13A14A15A16A17A18A194th CycleA20A21A22A23A24A25A26A27Table 3: Address Cycle Map(x8)NOTE:1. L must be set to Low.IO0IO1IO2IO3IO4IO5IO6IO7IO8-IO151st Cycle A0A1A2A3A4A5A6A7L (1)2nd Cycle A8A9A10L (1)L (1)L (1)L (1)L (1)L (1)3rd Cycle A11A12A13A14A15A16A17A18L (1)4th CycleA19A20A21A22A23A24A25A26L (1)Table 4: Address Cycle Map(x16)NOTE:1. L must be set to Low.FUNCTION1st CYCLE2nd CYCLE3rd CYCLE4th CYCLEAcceptable commandduring busyREAD 100h 30h --READ FOR COPY-BACK 00h 35h --READ ID 90h ---RESETFFh ---YesPAGE PROGRAM 80h 10h --COPY BACK PGM 85h 10h --BLOCK ERASE60h D0h --READ STATUS REGISTER 70h ---YesCACHE PROGRAM 80h 15h --RANDOM DATA INPUT 85h ---RAMDOM DATA OUTPUT 05h E0h --CACHE READ START 00h 31h --CACHE READ EXIT34h---Table 5: Command SetRev 0.3 / Nov. 2006101Gbit (128Mx8bit / 64Mx16bit) NAND FlashCLE ALE CE WE RE WP MODE H L L Rising H X Read ModeCommand Input L H L Rising H X Address Input(4 cycles)H L L Rising H H Write ModeCommand Input L H L Rising H HAddress Input(4 cycles)L L L Rising H H Data Input L L L (1)H Falling X Sequential Read and Data Output L L L H H X During Read (Busy)X X X X X H During Program (Busy)X X X X X HDuring Erase (Busy)X X X X X L Write Protect XXHXX0V/Vcc Stand ByTable 6: Mode SelectionNOTE:1. With the CE high during latency time does not stop the read operationRev 0.3 / Nov. 2006111Gbit (128Mx8bit / 64Mx16bit) NAND Flash2. BUS OPERATIONThere are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby.Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.2.1 Command Input.Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on IO7:0, disregarding the bus configuration (X8/X16).2.2 Address Input.Address Input bus operation allows the insertion of the memory address. To insert the 28 addresses needed to access the 1Gbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and table 16 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16).2.3 Data Input.Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 8 and table 13 for details of the timings requirements.2.4 Data Output.Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 9,10,12,13 and table 13 for details of the timings requirements.2.5 Write Protect.Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-tection even during the power up.2.6 Standby.In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.Rev 0.3 / Nov. 2006121Gbit (128Mx8bit / 64Mx16bit) NAND Flash3. DEVICE OPERATION3.1 Page Read.Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read operations, the second one does need 00h command, which four address cycles and 30h command initiates that operation. Second read operation always requires setup command if first read operation was executed using also random data out command.Two types of operations are available: random read. The random read mode is enabled when the page address is changed. The 2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time (3.3V device) by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.The device may output random data in a page instead of the consecutive sequential data by writing randomdata output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command.Random data output can be operated multiple times regardless of how many times it is done in a page.Random data output is not available in cache read.3.2 Page Program.The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle.The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 8; for example, 4 times for main array (X8 device:1time/512byte, X16 device:1time 256word) and 4 times for spare array (X8 device:1time/16byte ,X16 device:1time/8word).The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112 bytes (X8 device) or 1056 words (X16 device) of data may be loaded into the data register , followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may bechanged to the address which follows random data input command (85h). Random data input may be operated multi-ple times regardless of how many times it is done in a page.The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The P/E/R controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register . The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register . Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register . Figure 14 details the sequence.Rev 0.3 / Nov. 2006131Gbit (128Mx8bit / 64Mx16bit) NAND Flash3.3 Block Erase.The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A27 (X8) or A17 to A26 (X16) is valid while A12 to A17 (X8) or A11 to A16 (X16) are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not acci-dentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the P/E/R controller handles erase and erase-verify. Once the erase process starts, the Read Status Register command may be entered to read the status register . The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register . Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 18 details the sequence.3.4 Copy-Back Program.The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an exter-nal memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system perfor-mance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copyingprogram with the address of destination page. A read opera-tion with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or 1056word (X16 device) data into the internal data buffer .As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 16."When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."Figure 16 shows the command sequence for the copy-back operation.The Copy Back Program operation requires three steps:1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page Buffer .2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4bus cycles to input the target page address.3. Then the confirm command is issued to start the P/E/R Controller .Note:1. On the same plane.2. It’s prohibited to operate copy-back program from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages.Rev 0.3 / Nov. 2006141Gbit (128Mx8bit / 64Mx16bit) NAND Flash3.5 Read Status Register.The device contains a Status Register which may be read to find out whether read, program or erase operation is com-pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-mand register , a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 14 for specific Status Register definitions, and Figure 10 for specific timings requirements . The command reg-ister remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read dur-ing a random read cycle, the read command (00h) should be given before starting read cycles.3.6 Read ID.The device contains a product identification mode, initiated by writing 90h to the command register , followed by an address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and 3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence, while Tables 16 explain the byte meaning.3.7 Reset.The device offers a reset feature, executed by writing FFh to the command register . When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased.The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register . The R/B pin transitions to low for tRST after the Reset com-mand is written.Rev 0.3 / Nov. 2006151Gbit (128Mx8bit / 64Mx16bit) NAND Flash3.8 Cache programCache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16 device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-mand (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache- Busy status bit (I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state.When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming.If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked. See Fig. 18 for more details.NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However , if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.tPROG=Program time for the last page + Program time for the (last-1)page - (Program command cycle time + Last page data loading time)Rev 0.3 / Nov. 2006161Gbit (128Mx8bit / 64Mx16bit) NAND Flash3.9 Cache ReadCache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page.Start address of 1st page must be at page start (A<10:0>=00h) : in this way after 1st latency time (tr) , automatic data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device (50us for x16 device).Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using :- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device in ternally is active on n+1 page- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)To exit cache read operation, a cache read exit command (34h) must be issued. This command can be given any time (both device idle and reading).If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time shorter then tCBSY before becoming again idle and ready to accept any further commands. Figure 17 describes how to handle Cache Read through Status register .If user reads last byte/word of the memory array, then he has to stop by giving a cache read exit command. In general,if user wants to terminate a cache read, then he must give a cache read exit command (or reset command) before starting any new operation.Random data output is not available in cache read.Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.Rev 0.3 / Nov. 2006171Gbit (128Mx8bit / 64Mx16bit) NAND Flash4. OTHER FEATURES4.1 Data Protection for Power on/off SequenceThe device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V version). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 24. The two-step com-mand sequence for program/erase provides additional software protection.If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed the data. Power protection function is only available during the power on/off sequence.4.2 Ready/Busy.The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the P/E/R controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Figure 25). Its value can be determined by the following guidance.。