MAX4367EGA中文资料

元器件交易网ASAHI KASEI[AK4367]AK4367Low Power 24-Bit 2ch DAC with HP-AMP & Output MixerGENERAL DESCRIPTION The AK4367 is 24bit DAC with built-in Headphone Amplifier. The AK4367 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features “pop-free” power-on/off, a mute control and delivers 50mW of power at 16Ω. The AK4367 is housed in a 20pin QFN package, making it suitable for portable applications. FEATURE Multi-bit ∆Σ DAC Sampling Rate: 8kHz∼48kHz 64x Oversampling On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: ±0.02dB - Stopband Attenuation: 54dB Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz System Clock: 256fs/384fs/512fs - AC Couple Input Available Audio I/F Format: MSB First, 2’s Compliment - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified Digital ATT Analog Mixing Circuit Mono Lineout µP Interface: 3-wire/I2C Bass Boost Function Headphone Amplifier - Output Power: 50mW x 2ch @16Ω, 3.3V - S/N: 92dB@2.4V - Pop Noise Free at Power-ON/OFF and Mute Power Supply: 2.2V ∼ 3.6V Power Supply Current: 2.8mA@2.4V (@HP-AMP no-output) Ta: −40 ∼ 85°C Small Package: 20pin QFNMS0247-E-02 -1-2005/10元器件交易网ASAHI KASEI[AK4367]MCLKLINMINVDDBICK LRCK SDATAAudio InterfaceClock Divider VCOM HDP AmpVCOMDAC(Lch)MUTEHPLATT & Bass BoostDEM & Digital Filter DAC(Rch)MOUTHDP AmpMUTEHPRPDN I2C CAD0/CSN SCL/CCLK SDA/CDTI RIN VSS Serial I/F HVDD MUTETFigure 1. AK4367 Block DiagramMS0247-E-02 -2-2005/10元器件交易网ASAHI KASEI[AK4367]Ordering GuideAK4367VN AKD4367 −40 ∼ +85°C 20pin QFN (0.5mm pitch) Evaluation board for AK4367Pin LayoutMUTET 12HPR HPL MIN RIN LIN11151413VCOMHVDDVDDVSS16 17 18 19 20 1 2 3 4 510MOUT I2C PDN MCLK BICKAK4367Top View9 8 7 6CAD0/CSNSCL/CCLKSDA/CDTISDATAMS0247-E-02 -3-LRCK2005/10元器件交易网ASAHI KASEI[AK4367]PIN/FUNCTIONNo. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SDA CDTI SCL CCLK CAD0 CSN SDATA LRCK BICK MCLK PDN I2C MOUT VCOM MUTET VDD VSS HVDD HPR HPL MIN RIN LIN I/O I/O I I I I I I I I I I I O O O O O I I I Function Control Data Input/Output Pin (I2C pin = “H”) Control Data Input Pin (I2C pin = “L”) Control Data Clock Pin (I2C pin = “H”) Control Data Clock Pin (I2C pin = “L”) Chip Address 0 Select Pin (I2C pin = “H”) Control Data Chip Select Pin (I2C pin = “L”) Audio Serial Data Input Pin L/R Clock Pin This clock determines which audio channel is currently being input on SDATA pin. Serial Bit Clock Pin This clock is used to latch audio data. Master Clock Input Pin Power-down & Reset Pin When at “L”, the AK4367 is in power-down mode and is held in reset. The AK4367 should always be reset upon power-up. Control Mode Select Pin (Internal Pull-down Pin) “H”: I2C Bus, “L”: 3-wire Serial Mono Analog Output Pin Common Voltage Output Pin Normally connected to VSS pin with 0.1µF ceramic capacitor in parallel with a 2.2µF electrolytic capacitor. Mute Time Constant Control Pin Connected to VSS pin with a capacitor for mute time constant. Power Supply Pin Ground Pin Power Supply Pin for Headphone Amp Rch Headphone Amp Output Pin Lch Headphone Amp Output Pin Mono Analog Input Pin Rch Analog Input Pin Lch Analog Input PinNote: All digital input pins except analog input pins (MIN, RIN and LIN) and internal pull-down pin must not be left floating.Handling of Unused PinThe unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MOUT, MUTET, HPR, HPL, MIN, RIN, LIN CAD0 Setting These pins should be open. These pins should be connected to VSS.MS0247-E-02 -4-2005/10元器件交易网ASAHI KASEI[AK4367]ABSOLUATE MAXIMUM RATING (VSS=0V; Note 1) Parameter Symbol min Power Supplies Analog, Digital VDD −0.3 HP-AMP HVDD −0.3 Input Current (any pins except for supplies) IIN Input Voltage VIN −0.3 Ambient Temperature Ta −40 Storage Temperature Tstg −65 Note 1. All voltages with respect to ground.max 4.6 4.6 ±10 VDD+0.3 or 4.6 85 150Units V V mA V °C °CWARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.RECOMMEND OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog, Digital VDD 2.2 2.4 (Note 2) HP-AMP HVDD 2.2 2.4 Note 1. All voltages with respect to ground. Note 2. VDD should be same voltage as HVDD.* AKM assumes no responsibility for usage beyond the conditions in this datasheet.max 3.6 3.6Units V VMS0247-E-02 -5-2005/10元器件交易网ASAHI KASEI[AK4367]ANALOG CHARACTERISTICS (Ta=25°C; VDD=HVDD=2.4V, VSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16Ω and CL=220µF. (Refer to Figure 33); Mono output: RL =16Ω; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 3) Analog Output Characteristics THD+N dB −4.8dBFS Output, Po=10mW@16Ω, 2.4V −55 −45 dB −3dBFS Output, Po=28mW@16Ω, 3.3V −55 dB −3dBFS Output, Po=14mW@32Ω, 3.3V −57 D-Range −60dBFS Output, A-weighted, 2.4V 84 92 dB 94 dB −60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 84 92 dB A-weighted, 3.3V 94 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch 0.2 dB Gain Drift 200 ppm/°C Load Resistance (Note 4) 16 Ω Load Capacitance 300 Output Voltage (Note 5) 1.02 1.13 1.24 Vpp (−4.8dBFS Output) Max Output Power 26 mW RL=16Ω, 2.4V 50 mW RL=16Ω, 3.3V Mono Output: (MOUT pin) (Note 6) Analog Output Characteristics: THD+N (0dBFS Output) dB −60 −50 S/N (A-weighted) 84 92 dB DC Accuracy Gain Drift 200 ppm/°C Load Resistance (Note 4) 10 kΩ Load Capacitance 25 pF Output Voltage (Note 7) 1.42 1.58 1.74 Vpp Output Volume: (MOUT pin) Step Size 1 2 3 dB Gain Control Range 0 dB −30 Note 3. DACL=DACR bits = “1”, MINL=MINR=LINL=RINR bits = “0”, ATTL=ATTR=0dB. Note 4. AC Load Note 5. Output voltage is proportional to VDD voltage. Vout = 0.47 x VDD(typ)@−4.8dBFS. Note 6. DACM bit = “1”, DACL=DACR bits = “0”, LINM=RINM=MINM bits = “0”, ATTL=ATTR=ATTM=0dB, and common mode signal is input to L/Rch of DAC. Note 7. Output voltage is proportional to VDD voltage. Vout = 0.66 x VDD(typ).MS0247-E-02 -6-2005/10元器件交易网ASAHI KASEI[AK4367]Parameter min typ max LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (See Figure 31 and Figure 32.) LIN pin LINL bit = “1”, LINM bit = “1” 23 33 LINL bit = “1”, LINM bit = “0” 40 LINL bit = “0”, LINM bit = “1” 200 RIN pin RINR bit = “1”, RINM bit = “1” 23 33 RINR bit = “1”, RINM bit = “0” 40 RINR bit = “0”, RINM bit = “1” 200 MIN pin MINL bit = “1”, MINR bit = “1”, MINM bit = “1” 11 17 MINL bit = “1”, MINR bit = “0”, MINM bit = “0” 40 MINL bit = “0”, MINR bit = “1”, MINM bit = “0” 40 MINL bit = “0”, MINR bit = “0”, MINM bit = “1” 100 Gain LIN/RIN→MOUT −7 −6 −5 0 +1 MIN→MOUT −1 +0.8 +1.8 +2.8 LIN/MIN→HPL, RIN/MIN→HPR Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 8) VDD 1.8 3.0 HVDD 1.0 2.0 Power-Down Mode (PDN pin = “L”) (Note 9) 1 100 Note 8. PMDAC=PMHPL=PMHPR=PMMO bits = “1”, MUTEN bit = “1” and HP-Amp output is off. Note 9. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at VSS.UnitskΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ dB dB dBmA mA µAMS0247-E-02 -7-2005/10元器件交易网ASAHI KASEI[AK4367]FILTER CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”) Parameter Symbol min typ max Units DAC Digital Filter: (Note 10) Passband PB 0 20.0 kHz −0.05dB (Note 11) 22.05 kHz −6.0dB Stopband (Note 11) SB 24.1 kHz Passband Ripple PR dB ±0.02 Stopband Attenuation SA 54 dB Group Delay (Note 12) GD 20.8 1/fs Group Delay Distortion 0 µs ∆GD DAC Digital Filter + Analog Filter: (Note 10) (Note 13) Frequency Response FR dB 0 ∼ 20.0kHz ±0.5 Analog Filter: (Note 14) Frequency Response FR dB 0 ∼ 20.0kHz ±1.0 BOOST Filter: (Note 13) (Note 15) Frequency Response 20Hz FR dB 5.76 MIN 100Hz dB 2.92 1kHz dB 0.02 20Hz FR dB 10.80 MID 100Hz dB 6.84 1kHz dB 0.13 20Hz FR dB 16.06 MAX 100Hz dB 10.54 1kHz dB 0.37 Note 10. BOOST OFF (BST1-0 bit = “00”) Note 11. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.05dB), SB=0.546*fs(@−54dB). Note 12. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 24bit data of both channels to the input registers to the output of the analog signal. Note 13. DAC HPL, HPR, MOUT Note 14. MIN HPL/HPR/MOUT, LIN HPL/MOUT, RIN HPR/MOUT Note 15. These frequency responses scale with fs. If high-level signal is input, the AK4367 clips at low frequency.Boost Filter (fs=44.1kHz) 20 15 Level [dB] MID 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000MAXFigure 2. Boost Frequency (fs=44.1kHz)MS0247-E-02 -8-2005/10元器件交易网ASAHI KASEI[AK4367]DC CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 16) VAC 1.0 Low-Level Output Voltage (Iout = 3mA) VOL Input Leakage Current (Note 17) Iin Note 16. Only MCLK pin. (Figure 33) Note 17. I2C pin has internal pull-down device, nominally 100kΩ.typ -max 30%DVDD 0.4 ±10Units V V Vpp V µASWITCHING CHARACTERISTICS (Ta=25°C; VDD, HVDD=2.2 ∼ 3.6V; CL = 20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency fCLK 2.048 24.576 MHz Pulse Width Low (Note 18) tCLKL 0.4/fCLK ns Pulse Width High (Note 18) tCLKH 0.4/fCLK ns AC Pulse Width (Note 21) tACW 20 ns LRCK Timing Frequency fs 8 44.1 48 kHz Duty Cycle: Duty 45 55 % Serial Interface Timing (Note 19) BICK Period tBCK 1/(64fs) ns BICK Pulse Width Low tBCKL 130 ns Pulse Width High tBCKH 130 ns (Note 20) tLRB 50 ns LRCK Edge to BICK “↑” (Note 20) tBLR 50 ns BICK “↑” to LRCK Edge SDATA Hold Time tSDH 50 ns SDATA Setup Time tSDS 50 ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTI Setup Time tCDS 40 ns CDTI Hold Time tCDH 40 ns CSN “H” Time tCSW 150 ns tCSS 50 ns CSN “↑” to CCLK “↑” tCSH 50 ns CCLK “↑” to CSN “↑” Note 18. Except AC coupling. Note 19. Refer to “Serial Data Interface”. Note 20. BICK rising edge must not occur at the same time as LRCK edge. Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.)MS0247-E-02 -9-2005/10元器件交易网ASAHI KASEI[AK4367]Parameter Control Interface Timing (I2C Bus mode): (Note 22) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 23) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 24)Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP tPDmin 4.7 4.0 4.7 4.0 4.7 0.25 4.0 0 150typ -max 100 1.0 0.3 50 -Units kHz µs µs µs µs µs µs µs µs µs µs ns nsNote 22. I2C is a registered trademark of Philips Semiconductors. Note 23. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 24. The AK4367 can be reset by bringing PDN pin = “L” to “H” only upon power up.Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.MS0247-E-02 - 10 -2005/10ASAHI KASEI [AK4367]Timing DiagramMCLK Input Measurement PointVSS1000pFFigure 3. MCLK AC Coupling TimingVIHMCLKVILVIH LRCKVILVIH BICKVILFigure 4. Clock TimingLRCKVIH BICKVILVIH SDATAVIL VIH VILFigure 5. Serial Interface TimingASAHI KASEI [AK4367]CSNVIH CCLKVILVIH CDTI VILVIHVILFigure 6. WRITE Command Input TimingCSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0Figure 7. WRITE Data Input TimingVIHVILVIHVILFigure 8. I 2C Bus Mode TimingVILPDNFigure 9. Power-down & Reset TimingASAHI KASEI [AK4367]OPERATION OVERVIEWSystem ClockThe external clocks required to operate the AK4367 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1 shows system clock example.LRCK MCLK (MHz) BICK (MHz) fs 256fs 384fs 512fs 64fs 8kHz 2.048 3.072 4.096 0.512 11.025kHz 2.8224 4.2336 5.6448 0.7056 12kHz 3.072 4.608 6.144 0.768 16kHz 4.096 6.144 8.192 1.024 22.05kHz 5.6448 8.4672 11.2896 1.4112 24kHz 6.144 9.216 12.288 1.536 32kHz 8.192 12.288 16.384 2.048 44.1kHz 11.2896 16.9344 22.5792 2.8224 48kHz 12.288 18.432 24.576 3.072Table 1. System Clock ExampleAll external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4367 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling, the MCKAC bit should be set to “1”.For low sampling rates, DR and S/N degrade because of the outband noise. DR and S/N are improved by setting DFS1 bit to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS1 bit is “1”, MCLK needs 512fs.S/N (fs=8kHz, A-weighted) DFS1 DFS0 Over SampleRate fs MCLKHP-amp MOUT0 0 64fs 8kHz ∼48kHz 256fs/384fs/512fs 56dB 56dB Default 0 1 128fs 8kHz ∼24kHz 256fs/384fs/512fs 75dB 75dB 1 x 256fs 8kHz ∼12kHz512fs 92dB 90dB Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUTASAHI KASEI [AK4367]Serial Data InterfaceThe AK4367 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are available and are selected by setting DIF2, DIF1 and DIF0 bits (Table 3). Mode 0 is compatible with existing 16bit DACs and digital filters. Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I 2S serial data protocol. In Modes 2 and 3 with BICK ≥48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format.DIF2 bit DIF1 bit DIF0 bit MODE BICK Figure 0 0 0 0: 16bit, LSB justified 32fs ≤ BICK ≤ 64fs Figure 10 0 0 1 1: 20bit, LSB justified 40fs ≤ BICK ≤ 64fs Figure 11 0 1 0 2: 24bit, MSB justified 48fs ≤ BICK ≤ 64fsFigure 12Default 0 1 1 3: I 2S Compatible BICK=32fs or 48fs ≤ BICK ≤ 64fs Figure 13 1 0 0 4: 24bit, LSB justified 48fs ≤ BICK ≤ 64fsFigure 11 Table 3. Audio Data FormatSDATA BICK LRCKSDATA BICK (32fs)Mode 0Mode 0Figure 10. Mode 0 TimingSDATA LRCK BICK Mode 1SDATA Mode 4Figure 11. Mode 1, 4 TimingASAHI KASEI [AK4367]LRCKBICK SDATA 16bitSDATA 20bit SDATA 24bitFigure 12. Mode 2 TimingLRCK BICKSDATA 16bit SDATA 20bit SDATA 24bit BICK SDATA 16bit(32fs) Figure 13. Mode 3 TimingASAHI KASEI [AK4367]Digital AttenuatorThe AK4367 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 4). At DATTC bit = “1”, ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the Lch level and ATTR7-0 bits control the Rch level. When HPM bit = “1”, (L+R)/2 summation is done after volume control.ATTL7-0AttenuationATTR7-0DefaultFFH 0dBFEH −0.5dBFDH −1.0dBFCH −1.5dB: :: :02H −126.5dB01H −127.0dB00H MUTE (−∞)Table 4. Digital Volume ATT valuesThe ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 5). When ATS bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs fade to their current value. Digital attenuator is independent of the soft mute function.ATT speedATS0dB to MUTE 1 stepDefault0 1061/fs 4/fs1 7424/fs 29/fsTable 5. Transition time between set values of ATT7-0 bitsMOUT volume is controlled by ATTM3-0 bits when MMUTE bit = “0” (Table 6). Pop noise occurs when ATT3-0 bits are changed.MMUTE ATTM3-0 Attenuation0FH 0dB0EH −2dB0DH −4dB0CH −6dB: :: :01H −28dB00H −30dBDefault1 x MUTETable 6. MOUT Volume ATT valuesASAHI KASEI [AK4367] Soft MuteSoft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ during ATT_DATA×ATT transition time (Table 5) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.Attenuation-∞Analog OutputFigure 14. Soft Mute FunctionNotes:(1) ATT_DATA×ATT transition time (Table 5). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit =“1” and ATT_DATA = “128”.(2) The analog output corresponding to the digital input has a group delay, GD.(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinuedand returned to ATT level by the same cycle.ASAHI KASEI [AK4367] De-emphasis FilterThe AK4367 includes a digital de-emphasis filter (tc = 50/15µs) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 7).DEM1 bit DEM0 bit De-emphasis44.1kHz0 0Default0 1 OFF48kHz1 01 132kHzTable 7. De-emphasis Filter Frequency SelectBass Boost FunctionBy controlling BST1-0 bits, the low frequency boost signal can be output from DAC. The setting value is common in Lch and Rch (Table 8).BST1 bit BST0 bit BOOSTDefault0 0 OFF0 1 MIN1 0 MID1 1 MAXTable 8. Low Frequency Boost SelectSystem ResetThe AK4367 should be reset once by bringing PDN pin “L” upon power-up. After exiting reset, VCOM, DAC, HPL, HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is done.DAC exits reset and power down state by MCLK after PMDAC bit is changed to “1”, and then DAC is powered up and the internal timing starts clocking by LRCK “↑”. DAC is in power-down mode until MCLK and LRCK are input.ASAHI KASEI [AK4367]Headphone OutputPower supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the MUTET voltage. The Headphone-amp output load resistance is min.16Ω. When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the common voltage rises to 0.45 x VDD. When the MUTEN bit is “0”, the common voltage of Headphone-amp falls and the outputs (HPL and HPR pins) go to VSS.A capacitor between the MUTET pin and ground reduces pop noise at power-up/down. It isrecommended that the capacitor with small variation of capacitance and low ESR (Equivalent Series Resistance) over all temperature range, since the rise and fall time in Table 9 depend on the capacitance and ESR of the external capacitor at MUTET pin. In case only one path is connected, DAC or LIN/RIN/MIN. In case both paths are connected,DAC and LIN/RIN/MIN.t r : Rise Time up to VCOM/2 100k x C (typ) 120k x C (typ) t f : Fall Time down to 0V 200k x C (typ) 150k x C (typ)Table 9. Headphone-Amp Rise/Fall Time[Example] : A capacitor between the MUTET pin and ground = 1.0µF, and only DAC path is connected:Time constant of rise time: t r = 100k Ω x 1µF = 100ms(typ) Time constant of fall time: t f = 200k Ω x 1µF = 200ms(typ)When PMHPL and PMHPR bits are “0”, the Headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to VSS.MUTEN bitPMHPL/R bitHPL/R pin(1) (2)(4)(3)t rt f VCOM/2VCOMFigure 15. Power-up/Power-down Timing for Headphone-amp(1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still VSS.(2) Headphone-amp common voltage rises up (MUTEN bit = “1”). Common voltage of Headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is t r = 100k x C(typ) when the capacitor value on MUTET pin is “C”.(3) Headphone-amp common voltage falls down (MUTEN bit = “0”). Common voltage of Headphone-amp is falling to VSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to 0V is t f = 200k x C(typ) when the capacitor value on MUTET pin is “C”.(4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are VSS. If the power supply is switched off or Headphone-amp is powered-down before the common voltage goes to VSS, some pop noise occurs.ASAHI KASEI [AK4367]The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 10 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R L is 16Ω. Output powers are shown at HVDD = 2.4, 3.0 and 3.3V. The output voltage of headphone is 0.47 x VDD (Vpp) @−4.8dBFS.Figure 16. External Circuit Example of HeadphoneOutput Power [mW]R [Ω] C [µF] fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN 2.4V 3.0V 3.3V220 45 170 100 100 43 15 24 28100 70 286.8 47 149 78 7 12 14100 50 191647 106 474 6 7Table 10. Relationship of external circuit, output power and frequency responseASAHI KASEI [AK4367]Power-Up/Down Sequence1) DAC → HP-ampPower Supply PDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State HPL/R pinPMHPL, PMHPR bit ATTL7-0 ATTR7-0 bitMUTEN bitDACL, DACR bitFigure 17. Power-up/down sequence of DAC and HP-amp(1) PDN pin should be set to “H” at least 150ns after the power is supplied.(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes to “H”.(3) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can bestopped. Headphone amp can operate without these clocks.(4) DACL and DACR bits should be changed to “1” after PMDAC bit is changed to “1”.(5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pinis 2.2µF) after DACL and DACR bits are changed to “1”.(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 ist r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t f =200k x C(typ). When C=1µF, time constant is 200ms(typ).PMHPL, PMHPR, DACL and DACR bits should be changed to “0” after HPL and HPR pins go to VSS. (8) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz). (9) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).(10) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).ASAHI KASEI [AK4367]2) DAC → MOUTPower SupplyPDN pinPMVCM bitClock InputSDTI pin PMDAC bit DAC Internal State PMMO bit ATTL/R7-0 bit MOUT pinMMUTE, ATTM3-0 bitDACM bitFigure 18. Power-up/down sequence of DAC and MOUT(1) PDN pin should be set to “H” at least 150ns after the power is supplied. (2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) DACM bit should be changed to “1” after PMVCM bit is changed to “1”.(4) PMDAC and PMMO bits should be changed to “1” after DACM bit is changed to “1”.(5)External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = “0”, these clocks can be stopped. MOUT buffer can operate without these clocks.(6) When PMMO bit is changed, pop noise is output from MOUT pin.(7) Analog output corresponding to digital input has the group delay (GD) of 20.8/fs(=472µs@fs=44.1kHz). (8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).ASAHI KASEI [AK4367]3) LIN/RIN/MIN → HP-ampPower SupplyPDN pinPMVCM bitHPL/R pinLIN/RIN/MIN pinPMHPL/R bitMUTEN bitFigure 19. Power-up/down sequence of LIN/RIN/MIN and HP-amp(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stoppedwhen DAC is not used.(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”.(4) When LINL, MINL, RINR or MINR bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pinis 2.2µF) after LINL, MINL, RINR and MINR bits are changed to “1”.(6) Rise time of headphone amp is determined by external capacitor (C) of MUTET pin. The rise time up to VCOM/2 ist r = 100k x C(typ). When C=1µF, time constant is 100ms(typ).(7) Fall time of headphone amp is determined by external capacitor (C) of MUTET pin. The fall time down to 0V is t f =200k x C(typ). When C=1µF, time constant is 200ms(typ).PMHPL, PMHPR, LINL, MINL, RINR and MINR bits should be changed to “0” after HPL and HPR pins go to VSS.ASAHI KASEI [AK4367]4) LIN/RIN/MIN → MOUTPower SupplyPDN pinPMVCM bitMOUT pinMMUTE, ATTM3-0 bitLIN/RIN/MIN pin MUTEN bitPMMO bitFigure 20. Power-up/down sequence of LIN/RIN/MIN and MOUT(1) PDN pin should be set to “H” at least 150ns after the power is supplied. MCLK, BICK and LRCK can be stoppedwhen DAC is not used.(2) PMVCM bit should be changed to “1” after PDN pin goes to “H”.(3) LINM, RINM and MINM bits should be changed to “1” after PMVCM bit is changed to “1”.(4) When LINM, RINM or MINM bit is changed to “1”, LIN, RIN or MIN pin is biased to 0.45 x VDD voltage.(5) MUTEN and PMMO bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2µF)after LINM, RINM and MINM bits are changed to “1”.(6) When PMMO bit is changed, pop noise is output from MOUT pin.。

Driver Input Voltage (DI).............................-0.5V to (VCC + 0.5V)
Driver Output Voltage (Y, Z; A, B) ..........................-8V to +12.5V
Receiver Input Voltage (A, B).................................-8V to +12.5V
元器件交易网
MAX481E/MAX483E/MAX485E/MAX487E–MAX491E/MAX1487E
±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 Transceivers
ABSOLUTE MAXIMUM RATINGS
General Description
The MAX481E, MAX483E, MAX485E, MAX487E– MAX491E, and MAX1487E are low-power transceivers for RS-485 and RS-422 communications in harsh environments. Each driver output and receiver input is protected against ±15kV electro-static discharge (ESD) shocks, without latchup. These parts contain one driver and one receiver. The MAX483E, MAX487E, MAX488E, and MAX489E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E are not limited, allowing them to transmit up to 2.5Mbps.

________________General DescriptionThe MAX4617/MAX4618/MAX4619 are high-speed, low-voltage, CMOS analog ICs configured as an 8-channel multiplexer (MAX4617), two 4-channel multiplexers (MAX4618), and three single-pole/double-throw (SPDT)switches (MAX4619).These CMOS devices can operate continuously with a +2V to +5.5V single supply. Each switch can handle Rail-to-Rail ®analog signals. The off-leakage current is only 1nA at T A = +25°C and 10nA at T A = +85°C.All digital inputs have 0.8V to 2.4V logic thresholds,ensuring TTL/CMOS-logic compatibility when using a single +5V supply.________________________ApplicationsBattery-Operated Equipment Audio/Video Signal RoutingLow-Voltage Data-Acquisition Systems Communications Circuits____________________________Featureso Fast Switching Times15ns t ON 10ns t OFFo Pin Compatible with Industry-Standard 74HC4051/74HC4052/74HC4053 and MAX4581/MAX4582/MAX4583o Guaranteed On-Resistance10Ωmax (+5V Supply)20Ωmax (+3V Supply)o Guaranteed 1Ω On-Resistance Match Between Channels (single +5V supply)o Guaranteed Low Off-Leakage Current:1nA at +25°Co Guaranteed Low On-Leakage Current:1nA at +25°Co +2V to +5.5V Single-Supply Operation o TTL/CMOS-Logic Compatible o Low Crosstalk: <-96dB o High Off-Isolation: <-93dBo Low Distortion: <0.017% (600Ω)MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________Maxim Integrated Products1____________________________________Pin Configurations/Functional Diagrams19-1502; Rev 0; 7/99_______________Ordering InformationOrdering Information continued at end of data sheet.Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.For free samples & the latest literature: , or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.16 Plastic DIP16 Narrow SO 16 TSSOP PIN-PACKAGE TEMP. RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°CMAX4617CPEMAX4617CSE MAX4617CUE PARTM A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS—Single +5V Supply(V CC = +4.5V to +5.5V, V _H = 2.4V, V _L = 0.8V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Voltages Referenced to GNDV CC, A, B, C, or Enable...........................................-0.3V to +6V Voltage into Any Analog Terminal(Note 1).........................................................-0.3V to (V CC + 0.3V)Continuous Current into Any Terminal..............................±75mA Peak Current, X_, Y_, Z_(pulsed at 1ms, 10% duty cycle).................................±200mA Continuous Power Dissipation (T A = +70°C)TSSOP (derate 6.7mW/°C above +70°C)......................533mWNarrow SO (derate 8.70mW/°C above +70°C)..............696mW Plastic DIP (derate 10.53mW/°C above +70°C)..............842mW Operating Temperature RangesMAX461_C_ _ ......................................................0°C to +70°C MAX461_E_ _....................................................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10sec).............................+300°CNote 1:Voltages exceeding V CC or GND on any analog signal terminal are clamped by internal diodes. Limit forward-diode currentto maximum current rating.MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)(V CC = +4.5V to +5.5V, V _H = 2.4V, V _L = 0.8V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 2)M A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 4_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS—Single +3.3V Supply(V CC = +3V to +3.6V, V _H = 2.0V, V _L = 0.5V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 2)MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches_______________________________________________________________________________________5Note 2:The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.Note 3:∆R ON = R ON(MAX)- R ON(MIN).Note 4:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specifiedanalog signal ranges; i.e., V X_, V Y_, V Z_= 3V to 0 and 0 to -3V.Note 5:Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation at T A = +25°C.Note 6:Guaranteed by design, not production tested.ELECTRICAL CHARACTERISTICS—Single +2.5V Supply(V CC = +2.5V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 2)M A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 6_______________________________________________________________________________________252015105002.53.0 3.54.0 4.50.5 1.0 1.5 2.05.0ON-RESISTANCE vs. V X , V Y , V ZV X , V Y , V Z (V)O N -R E S I S T A N C E (Ω)02.53.01.52.00.51.03.54.04.55.002.01.50.5 1.0 2.53.0 3.54.0 4.55.0ON-RESISTANCE vs.V X , V Y , V ZAND TEMPERATUREV X , V Y , V Z (V)R O N (Ω)10000.01-4010020406080-20OFF-LEAKAGE vs. TEMPERATURE1010.1100TEMPERATURE (°C)O F F -L E A K A G E (p A )0.1110100-40-2020406080100ON-LEAKAGE vs. TEMPERATUREM A X 4617 t o c 04TEMPERATURE (°C)O N -L E A K A G E (p A )042681416181210201.0 1.52.0 2.50.53.0 3.54.0 4.55.0CHARGE INJECTION vs. V X , V Y , V ZM A X 4617 t o c 05V X , V Y , V Z (V)C H A R G E I N J E C T I O N (p C )SUPPLY CURRENT vs. TEMPERATURE10,0001-40206040-201008010TEMPERATURE (°C)I C C (p A )10010000SUPPLY CURRENT vs.LOGIC VOLTAGE2.5V A , V B , V C , V ENABLE (V)I C C (m A )2.01.50.51.05.02.01.00.5 1.53.53.02.54.54.0Typical Operating Characteristics(V CC = +5V, GND = 0, T A = +25°C, unless otherwise noted.)MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches_______________________________________________________________________________________700.0050.010.0150.020.0258104621214161820TOTAL HARMONIC DISTORTIONvs. FREQUENCYFREQUENCY (kHz)()42861210142.0 3.0 3.52.5 4.0 4.5 5.0 5.5SWITCHING TIME vs. VOLTAGEM A X 4617 t o c 11V+ (V)S W I T C H I N G T I M E S (n s )1.01.41.21.61.82.02.53.04.03.54.55.0INPUT HIGH LOGIC THRESHOLDvs. SUPPLY VOLTAGEM A X 4617 t o c 08V CC (V)V A , V B , V C , V E N A B L E (V )10k100k1M10M100M500MFREQUENCY RESPONSEFREQUENCY (Hz)G A I N (d B )P H A S E (°)-100-70-80-90-60-50-40-30-20-100-180-72-108-144-3603672108144180Typical Operating Characteristics (continued)(V CC = +5V, GND = 0, T A = +25°C, unless otherwise noted.)M A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 8_________________________________________________________________________________________________Applications InformationPower-Supply ConsiderationsOverviewThe MAX4617/MAX4618/MAX4619 construction is typi-cal of most CMOS analog switches. They have two sup-ply pins: V CC and GND. V CC and GND are used to drive the internal CMOS switches and set the limits of the ana-log voltage on any switch. Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V CC and GND. If any analog signal exceeds V CC or GND, one of these diodes conducts.During normal operation, these and other reverse-biased ESD diodes leak, forming the only current drawn from V CC or GND.Virtually all the analog leakage current comes from the ESD diodes. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V CC or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V CC and GND pins con-stitutes the analog-signal-path leakage current. All ana-log leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.This is why both sides of a given switch can show leak-age currents of either the same or opposite polarity.V CC and GND power the internal logic and set the input logic limits. Logic inputs have ESD-protection diodes to ground.in both directions.Pin DescriptionMAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches_______________________________________________________________________________________9The logic-level thresholds are TTL/CMOS compatible when V CC is +5V. As V CC rises, the threshold increas-es; as V CC falls, the threshold decreases. For example,when V CC = +3V the guaranteed minimum logic-high threshold decreases to 2.0VPower SupplyThese devices operate from a single supply between +2.5V and +5.5V. All of the bipolar precautions must be observed. At room temperature, they actually “work”with a single supply near or below +2V, although as supply voltage decreases, switch on-resistance becomes very high.Overvoltage ProtectionProper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maxi-mum ratings because stresses beyond the listed rat-ings can cause permanent damage to the devices.Always sequence V CC on first, followed by the logic inputs and analog signals. If power-supply sequencing is not possible, add two small signal diodes (D1, D2) in series with the supply pins for overvoltage protection (Figure 1).Adding diodes reduces the analog-signal range to one diode drop below V CC and one diode drop above GND, but does not affect the devices’ low switch resis-tance and low leakage characteristics. Device opera-tion is unchanged, and the difference between V CC and GND should not exceed 6V. These protection diodes are not recommended if signal levels must extend to ground.High-Frequency PerformanceIn 50Ωsystems, signal response is reasonably flat up to 50MHz (see Typical Operating Characteristics ).Above 20MHz, the on-response has several minor peaks that are highly layout dependent. The problem is not turning the switch on, but turning it off. The off-state switch acts like a capacitor and passes higher frequen-cies with less attenuation. At 10MHz, off-isolation is about -50dB in 50Ωsystems, becoming worse (approx-imately 20dB per decade) as frequency increases.Higher circuit impedances also degrade off-isolation.Adjacent channel attenuation is about 3dB above that of a bare IC socket and is entirely due to capacitive coupling.Pin NomenclatureThe MAX4617/MAX4618/MAX4619 are pin compatible with the industry-standard 74HC4051/74HC4052/74HC4053 and the MAX4581/MAX4582/MAX4583. In single-supply applications, they function identically and have identical logic diagrams, although these parts dif-fer electrically.The pin designations and logic diagrams in this data sheet conform to the original 1972 specifications pub-lished by RCA for the CD4051/CD4052/CD4053. These designations differ from the standard Maxim switch and mux designations found on other Maxim data sheets (including the MAX4051/MAX4052/MAX4053) and may cause confusion. Designers who feel more comfortable with Maxim’s standard designations are advised that the pin designations and logic diagrams on the MAX4051/MAX4052/MAX4053 data sheet may be freely applied to the MAX4617/MAX4618/MAX4619.Figure 1. Overvoltage Protection Using External Blocking DiodesM A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 10______________________________________________________________________________________X = Don’t care*C not present on MAX4618.Note:Input and output pins are identical and interchangeable. Either may be considered an input or output; signals pass equallywell in either direction.MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches______________________________________________________________________________________11Figure 2. Address Transition Times______________________________________________Test Circuits/Timing DiagramsM A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches 12______________________________________________________________________________________Figure 3. Enable Switching Times_________________________________Test Circuits/Timing Diagrams (continued)MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches______________________________________________________________________________________13Figure 4. Break-Before-Make IntervalFigure 5. Charge Injection_________________________________Test Circuits/Timing Diagrams (continued)M A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches14______________________________________________________________________________________Figure 6. Off-Isolation, On-Loss, and CrosstalkFigure 7. Capacitance _________________________________Test Circuits/Timing Diagrams (continued)MAX4617/MAX4618/MAX4619High-Speed, Low-Voltage, CMOS AnalogMultiplexers/Switches______________________________________________________________________________________15___________________Chip Information_Ordering Information (continued)TRANSISTOR COUNT: 244M A X 4617/M A X 4618/M A X 4619High-Speed, Low-Voltage, CMOS Analog Multiplexers/Switches Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.16____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©1999 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.________________________________________________________Package Information。

For free samples & the latest literature: , or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.General DescriptionThe MAX4370 is a circuit-breaker IC designed to offer protection in hot-swap applications using Maxim’s DualSpeed/BiLevel™ detection. This controller,designed to reside either on the backplane or on the removable card, is used to protect a system from start-up damage when a card or board is inserted into a rack with the main system power supply turned on. The card’s discharged filter capacitors provide a low impedance that can momentarily cause the main power supply to collapse. The MAX4370 prevents this start-up condition by providing inrush current regulation during a programmable start-up period, allowing the system to stabilize safely. In addition, two on-chip comparators provide DualSpeed/BiLevel short-circuit protection and overcurrent protection during normal operation.The MAX4370 provides protection for a +3V to +12V single supply. An internal charge pump generates the controlled gate drive for an external N-channel MOS -FET power switch. The MAX4370 latches the switch off after a fault condition until an external reset signal clears the device. Other features include a status pin to indicate a fault condition, an adjustable overcurrent response time, and a power-on reset comparator.The MAX4370 is specified for the extended-industrial temperature range (-40°C to +85°C) and is available in an 8-pin SO package.ApplicationsHot Board InsertionSolid-State Circuit BreakerFeatureso DualSpeed/BiLevel Protection During Normal Operation o Inrush Current Regulated at Start-Up o Resides Either on the Backplane or on the Removable Card o Programmable Start-Up Period and Response Time o Allows Safe Board Insertion and Removal from Live Backplane o Protection for +3V to +12V Single Supplies o Latched Off After Fault Condition o Status Output Pino Internal Charge Pump Generates Gate Drive for External N-Channel MOSFETMAX4370Current-Regulating Hot-Swap Controller withDualSpeed/BiLevel Fault Protection________________________________________________________________Maxim Integrated Products1Typical Operating Circuit19-1472; Rev 0; 4/99Ordering InformationPin Configuration appears at end of data sheet.M A X 4370Current-Regulating Hot-Swap Controller with DualSpeed/BiLevel Fault Protection 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V IN = +2.7V to +13.2V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V IN = +5V and T A = +25°C.) (Note 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Note 1:ON can be pulled below ground. Limiting the current to 2mA ensures that this pin is never lower than about -0.8V.V IN to GND...........................................................................+15V STAT to GND..........................................................-0.3V to +14V GATE to GND ..............................................-0.3V to (V IN + 8.5V)ON to GND (Note 1).................................................-1V to +14V CSPD to GND.............-0.3V to the lower of (V IN + 0.3V) or +12V VSEN, CTIM to GND....................................-0.3V to (V IN + 0.3V) Current into ON...................................................................±2mACurrent into Any Other Pin................................................±50mA Continuous Power Dissipation (T A = +70°C)SO (derate 5.9mW/°C above +70°C)...........................471mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10sec)............................+300°CMAX4370Current-Regulating Hot-Swap Controller withDualSpeed/BiLevel Fault Protection_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V IN = +2.7V to +13.2V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V IN = +5V and T A = +25°C.) (Note 2)Note 2:All devices are 100% tested at T A = +25°C. All temperature limits are guaranteed by design.Note 3:The start-up period (t START ) is the time during which the slow comparator is ignored and the device acts as a current limiterby regulating the sense current with the fast comparator. It is measured from ON rising above 0.6V to STAT rising.Note 4:The current available at GATE is a function of V GATE (see Typical Operating Characteristics.)M A X 4370Current-Regulating Hot-Swap Controller with DualSpeed/BiLevel Fault Protection 4_______________________________________________________________________________________Typical Operating Characteristics(Circuit of Figure 7, V IN = 5V, R SENSE = 100m Ω, M1 = FDS6670A, C BOARD = 470µF, C GATE = 0, R S = 0, T A = +25°C, unless other-wise noted.)00.30.20.10.50.40.90.80.70.61.02468101214SUPPLY CURRENT vs. INPUT VOLTAGEV IN (V)S U P P L Y C U R R E N T (m A )-40-1510356085SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)00.30.20.10.50.40.90.80.70.61.0S U P P L Y C U R R E N T (m A )49.049.649.449.250.049.850.850.650.450.251.002468101214SLOW COMPARATOR THRESHOLDvs. INPUT VOLTAGEV IN (V)V S C , T H (m V )2001004003006005007001101001000FAST COMPARATOR RESPONSE TIMEvs. OVERDRIVE VOLTAGEV OD (mV)t F C D (n s )182019222123241820192221232406824101214SLOW COMPARATORRESPONSE TIME vs. INPUT VOLTAGEV IN (V)t C S P D (µs )t C S P D (m s)190196194192200198108206204202210FAST COMPARATOR THRESHOLDvs. INPUT VOLTAGEV F C , T H (m V )02468101214V IN (V)400430420410450440490480470460500-40-2020406080100FAST COMPARATOR RESPONSE TIMEvs. TEMPERATURETEMPERATURE (°C)t F C D (n s )2502703102903303504268101214START-UP TIME vs. INPUT VOLTAGEV IN (V)t S T A R T (µs )252731293335t S T A R T (m s )MAX4370Current-Regulating Hot-Swap Controller withDualSpeed/BiLevel Fault Protection_______________________________________________________________________________________506040208010012008624101214161820GATE CHARGE CURRENT vs. GATE VOLTAGEV GATE (V)I G A T E (µA )502510075125150-40-1035-156085GATE CHARGE CURRENT vs. TEMPERATURETEMPERATURE (°C)I G A T E (µA )5151020254268101214GATE VOLTAGE vs. INPUT VOLTAGEV IN (V)V G A T E (V )01005015030035025020040004681021214161820GATE DISCHARGE CURRENTvs. GATE VOLTAGEV GATE (V)I G A T E (µA)C BOARD = 0, R SENSE = 100m Ω,C TIM = 10nF, C GATE = 0V OUT (2V/div)V GATE (2V/div)ON 100µs/divSTART-UP TIME (C BOARD = 0)MAX4370-1610050200150350300250400GATE DISCHARGE CURRENTvs. TEMPERATURETEMPERATURE (°C)I G A T E (µA)C BOARD = 470µF, R SENSE = 100m Ω,C TIM = 10nF, C GATE= 0I LOAD (1A/div)V OUT (2V/div)V GATE (2V/div)ON 500µs/divSTART-UP TIME (C BOARD = 470µF)MAX4370-15C BOARD = 470µF, R SENSE = 100m Ω,C GATE= 22nF, C TIM = 10nF, R S = 0I LOAD (1A/div)V OUT (2V/div)V GATE (2V/div)ON 1ms/divSTART-UP TIME(EXTERNAL C GATE = 22nF, C BOARD = 470µF)MAX4370-17C BOARD = 470µF, R SENSE = 100m Ω,C GATE = 0I LOAD (1A/div)V OUT (2V/div)V GATE (2V/div)0A50µs/divTURN-OFF TIME (C BOARD = 470µF)MAX4370-18ON0VTypical Operating Characteristics (continued)(Circuit of Figure 7, V IN = 5V, R SENSE = 100m Ω, M1 = FDS6670A, C BOARD = 470µF, C GATE = 0, R S = 0, T A = +25°C, unless other-wise noted.)M A X 4370Current-Regulating Hot-Swap Controller with DualSpeed/BiLevel Fault Protection 6_______________________________________________________________________________________Typical Operating Characteristics (continued)(Circuit of Figure 7, V IN = 5V, R SENSE = 100m Ω, M1 = FDS6670A, C BOARD = 470µF, C GATE = 0, R S = 0, T A = +25°C, unless other-wise noted.)C BOARD = 0, R SENSE = 100m Ω,C GATE = 0, R S = 0I LOAD(1A/div)V OUT(2V/div)V GATE (2V/div)050µs/divTURN-OFF TIME (C BOARD = 0)MAX4370-19ONA0VC BOARD = 470µF, R SENSE = 100m Ω,C GATE = 22nF, R S = 0ILOAD (1A/div)V OUT (2V/div)V GATE (2V/div)0A0V200µs/divTURN-OFF TIME(EXTERNAL C GATE = 22nF, C BOARD = 470µF)MAX4370-20ON 0.010.11101001000TIME TO CHARGE GATEvs. C GATEC GATE (nF)T I M E T O C H A R G E G A T E (m s )10000.0010.0110.1100100.010.11101001000TIME TO DISCHARGE GATEvs. C GATEC GATE (nF)T I M E T O D I S C H A R G E G A T E (m s )10000.00110.10.01101000.5950.5970.6010.5990.6030.60504268101214ON COMPARATOR THRESHOLDvs. INPUT VOLTAGEV IN (V)O N C O M P A R A T O R T H R E S H O L D D (V )0.59500.60000.59750.60500.60250.60750.6100-403560-151085ON COMPARATOR THRESHOLDvs. TEMPERATURETEMPERATURE (°C)O N C O M P A R A T O R T H R E S H O L D (V )R I S I N GF A L L I NG 2.302.402.352.502.452.552.60-403560-151085UVLO THRESHOLD VOLTAGEvs. TEMPERATURETEMPERATURE (°C)U V L O T H R E S H O L D (V )140145150155160UVLO DELAY vs. TEMPERATURETEMPERATURE (°C)U V L O D E L A Y (m s )-403560-151085MAX4370Current-Regulating Hot-Swap Controller withDualSpeed/BiLevel Fault Protection_______________________________________________________________________________________7Pin DescriptionPIN Supply Voltage Input. Connect to 2.7V to 13.2V.V IN 1FUNCTIONNAME Current-Sense Resistor Voltage Input. R SENSE is connected from V IN to VSEN.VSEN 2GroundGND 4Gate Drive Output. Connect to gate of external N-channel MOSFET.GATE 3Start-Up Timer Setting. Leave floating or connect the timing capacitor from CTIM to GND. See Start-Up Timing Capacitor section.CTIM 6ON Comparator Input. Connect high for normal operation; connect low to force the MOSFET off. Comparator threshold V TH,ON = 0.6V allows for precise control over shutdown feature. Pulse ON low for at least 20µs,then high to restart after a fault.ON8Status Output—open drain. High indicates start-up completed with no fault. See Table 1.STAT 7Slow Comparator Speed Setting. Leave floating or connect the timing capacitor from CSPD to GND. See Slow Comparator Response Time section.CSPD 5Figure 1. Functional DiagramM A X 4370Current-Regulating Hot-Swap Controller with DualSpeed/BiLevel Fault Protection 8_______________________________________________________________________________________Detailed DescriptionThe MAX4370 is a circuit-breaker IC designed for hot-swap applications where a card or board is to be inserted into a rack with the main system power supply turned on. Normally, when a card is plugged into a live backplane, the card is discharged filter capacitors pro-vide a low impedance, which can momentarily cause the main power supply to collapse. The MAX4370 is designed to reside either in the backplane or in the removable card to provide inrush-current limiting and short-circuit protection. This is achieved using a charge pump as gate drive for an external N-channel MOSFET,an external current-sense resistor, and two on-chip comparators. Figure 1 shows the device’s functional diagram.The slow comparator response time and the start-up timer can be adjusted with external capacitors. The tim-ing components are optional; without them the part is set to its nominal values, as shown in the Electrical Characteristics.Start-Up PeriodCTIM sets the start-up period. This mode starts when the power is first applied to V IN if ON is connected to V IN , or at the rising edge of ON. In addition, the voltage at V IN must be above the undervoltage lockout for 150ms (see Undervoltage Lockout ).During start-up, the slow comparator is disabled and current limiting is provided two different ways:1)Slow ramping of the current to the load by controlling the external MOSFET gate voltage.2)Limiting the current to the load by regulating the volt-age across the external current-sense resistor.Unlike other circuit-breaker ICs, the MAX4370 hot-swap controller regulates the current to a preset level instead of completely turning off if an overcurrent occurs during start-up.In start-up mode, the gate drive current is limited to 100µA and decreases with the increase of the gate voltage (see Typical Operating Characteristics ). This allows the MAX4370 to slowly enhance the MOSFET. If the fast comparator detects an overcurrent, the gate voltage is momentarily discharged with a fixed 80µA current until the load current through the sense resistor (R SENSE ) decreases below its threshold point. This effectively regulates the turn-on current during start-up.Figure 2 shows the start-up waveforms. STAT goes high at the end of the start-up period if no fault condi-tion is present.Normal Operation (DualSpeed/BiLevel)In normal operation (after the start-up period has expired), protection is provided by turning off the exter-nal MOSFET when a fault condition is encountered.DualSpeed/BiLevel fault protection incorporates two comparators with different thresholds and response times to monitor the load current:1)Slow Comparator. This comparator has an externally set response time (20µs to seconds) and a fixed 50mV threshold voltage. The slow comparator ignores low-amplitude momentary current glitches.After an extended overcurrent condition, a fault is detected and the MOSFET gate is discharged.2)Fast Comparator. This comparator has a fixed response time and a higher 200mV threshold volt -age. The fast comparator turns off the MOSFET immediately after it detects a large amplitude event such as a short circuit.In each case, when a fault is encountered, the status pin (STAT) goes low and the MAX4370 stays latched off. Figure 3 shows the waveforms after a fault condi -tion.Figure 2. Start-Up WaveformsMAX4370Current-Regulating Hot-Swap Controller withDualSpeed/BiLevel Fault Protection_______________________________________________________________________________________9Slow ComparatorThe slow comparator is disabled at start-up while the external MOSFET is turning on. This allows the part to ignore the higher-than-normal inrush current charging the board capacitors (C BOARD ) when a card is first plugged in.If the slow comparator detects an overload current while in normal operation (after start-up is completed),it turns off the external MOSFET by discharging the gate capacitance with a 200µA current. The slow com-parator threshold is set at 50mV and has a default delay of 20µs (CSPD floating), allowing it to ignore power-supply glitches and noise. The response time can be lengthened with an external capacitor at CSPD (Figure 8).If the overcurrent condition is not continuous, the dura-tion above the threshold minus the duration below it must be greater than 20µs (or the external programmed value) for the device to trip. When the current is above the threshold, CSPD is charged with a 6µA current source; when the current is below the threshold, CSPD is discharged with a 6µA current source. A fault is detected when CSPD is charged to the trip point of 1.2V. A pulsing current with a duty cycle greater than50% (i.e., > 50% of the time the current is above the threshold level) will be considered a fault condition even if it is never higher than the threshold for more than the slow comparator’s set response time.Once the fault condition is detected, the STAT pin goes low and the device goes into latched mode. The GATE voltage discharge rate depends on the gate capaci-tance and the external capacitance at GATE.Fast ComparatorThe fast comparator behaves differently according to the operating mode. During start-up, the fast compara-tor is part of a simple current regulator. When the sensed current is above the threshold (V FC,TH =200mV), the gate is discharged with a 80µA current source. When the sensed current drops below the threshold, the charge pump turns on again. The sensed current will rise and fall near the threshold due to the fast comparator and charge-pump propagation delay.The gate voltage will be roughly saw-tooth shaped, and the load current will present a 20% ripple. The ripple can be reduced by adding a capacitor from GATE to GND. Once C BOARD is completely charged, the load current drops to its normal operating levels. If the sensed current is still high after the start-up timer expires, the MOSFET gate is discharged completely.In normal operation (after start-up), the fast comparator is used as an emergency off switch. If the load current reaches the fast comparator threshold, the device immediately forces the MOSFET off completely by dis-charging the GATE with a 200µA current. This can occur in the event of a serious current overload or a dead short. Given a 1000pF gate capacitance and 12V gate voltage, the MOSFET will be off in less than 60µs.Any additional capacitance connected between GATE and GND to slow down the turn-on time also increases the turn-off time.Latched Mode and ResetThe MOSFET driver of the MAX4370 stays latched off after a fault condition until it is reset by a negative-going pulse on the ON pin. Pulse ON low for 20µs (min), then high to restart after a fault. During start-up, a negative-going edge on ON will force the device to turn off the MOSFET and place the device in latched mode.Keep ON low for 20µs (min) to restart.Figure 3. Response to a Fault ConditionM A X 4370Current-Regulating Hot-Swap Controller with DualSpeed/BiLevel Fault Protection 10______________________________________________________________________________________Status OutputThe status output is an open-drain output that goes low when the part is:1)in start-up2)forced off (on = GND)3)in an overcurrent condition, or 4)latched off.STAT is high only if the part is in normal mode and no faults are present (Table 1). Figure 4 shows the STAT timing diagram.Over/Undervoltage LockoutsThe undervoltage lockout prevents the MAX4370 from turning on the external MOSFET until the input voltage at V IN exceeds the lockout threshold (2.25V min) for at least 150ms. The undervoltage lockout protects the external MOSFET from insufficient gate drive voltage.The 150ms timeout ensures that the board is fully plugged into the backplane and that V IN is stable.Voltage transients at V IN with voltages below the UVLO will reset the device and initiate a start-up sequence.The device also features a gate overvoltage lockout that prevents the device from restarting after a fault condition if the discharge has not been completed.V GATE must be discharged to below 0.1V before restarting. Since the MAX4370 does not monitor the output voltage, a start-up sequence can be initiated while the board capacitance is still charged.Gate Overvoltage ProtectionNewer-generation MOSFETs have an absolute maxi -mum rating of ±8V for the gate-to-source voltage (V GS ).To protect these MOSFETs, the MAX4370 limits the gate-to-drain (V GD ) to +7.5V with an internal zener diode. No protection is provided for negative V GD . If GATE can be discharged to GND faster than the output voltage, an external small-signal protection diode (D1)can be used, as shown in Figure 5.Table 1. Status Output Truth TableFigure 4. Status Output (STAT) Timing DiagramFigure 5. External Gate-Source ProtectionX = Don’t care分销商库存信息:MAXIMMAX4370ESA+MAX4370ESA+T。