mt933tp1n中文资料_数据手册_IC数据表

MT933MT9333.3V 10/100 Fast Ethernet Transceiver to MIIFeaturesGIntegrated 10/100 Mbps Ethernet in a Single ChipSolutionGSingle 3.3V Power SupplyGHalf Duplex and Full Duplex in both 10BASE-Tand 100BASE-TXGFull MII for a Glueless MAC ConnectionGExtended Register SetGIntegrated 10BASE-T Transceivers and Receive /Transmit FiltersGIntegrated Adaptive Equaliser and Base LineWander Correction (for FDDI Killer Packet)GFull Auto-Negotiation Support for 10BASE-T and100BASE-TX both Half and Full DuplexGLink Status Change InterruptGParallel Detection for Supporting Non AutoNegotiation in Legacy Link PartnersGLow Dynamic CurrentGDeep Sleep Low Power Mode <1mAGInternal Power on ResetG64 pin 1mm thick TQFP PackageGSingle Magnetics for 10BASE-T and 100BASE-TXOperation for a Single RJ45 ConnectorGSupport for Flow Control 802.3 SpecificationGIntegrated 6 LED DriverDS5029 Issue no 3.0 June 2000Ordering InformationMT933/CG/TP1N

DescriptionThe MT933 is a single chip 3.3V CMOS physicallayer solution from MII to the magnetics. It is designedfor 10BASE-T and 100BASE-TX Ethernet, basedon the IEEE 802.3 specifications.The MT933 is compatible with the Auto Negotiationsection of IEEE 802.3u and provides all the supportneeded for the 802.3 Full duplex specification.

RJ45Switch or MACMT933IsolationMagnetics

Figure 1 System block diagramGLow External Component CountGLoop-back mode for diagnosticsGIntelligent power management(auto shutdown, auto wake)GLow Transmit Jitter

https://www.ichunt.comMT933

Figure 2Pin connections

TP6448 MINT47 DVDD346 MDC45 MDIO44 DGND343 RefCLK42 OSCVDD41 XTAL140 XTAL239 OSCGND38 TXGND437 TXVDD436 TXREF10035 TXREF1034 TXVDD333 TXGND3

SUBGND1 32PA0 31PA1 30PA2 29TXON 28TXVDD1 27TXGND1 26TXGND2 25TXVDD2 24TXOP 23ANEN 22RXVDD1 21RXIN 20 RXIP 19RXGND1 18PA3 17RXGND2 16 RXVDD2 15RESETN 14PA4 13SPDST 12FDST 11RXGND3 10RXVDD3 9DVDD1 8COLST 7ACTST 6LNKST 5TX_EN 4DGND1 3TX_ER 2SUBGND2 164 TX_CLK63 TX0362 TXD261 TXD160 TXD059 RX_ER58 RXD357 RXD256 RXD155 RXD054 DVDD253 RX_CLK52 DGND251 RX_DV50 CRS49 COL

Functional DescriptionThe MT933 has three basic modes of operation:10BASE-T, 100BASE-TX and LOW POWER modes.The Control block is designed to manage thesemodes by starting and stopping the 10M and 100Mtransceivers in a well-controlled manner such that nospurious signals are output on either the MII ortwisted-pair interfaces. Furthermore, it continuouslymonitors the behaviour of the transceivers and takescorrective action if a fault is detected.Other modes described herein are repeater modeand reset mode.25MHz Reference ClockThe MT933 requires a 25MHz +/-100ppm timingreference for 802.3 compatible operation. This maybe supplied either from the integrated oscillator orfrom an external source. When the integrated oscillatoris used, a suitable crystal must be connected acrossthe XTAL1 & XTAL2 pins (see “External Components”)and REFCLK must be tied low. When an externalsource is used, it must be input to the REFCLK pinand XTAL1 must be tied low. XTAL2 must beunconnected.10Base-T Operation10Mb/s Data Transfer on the MII10Mb/s data is transferred across the MII with clockspeeds of 2.5MHz. The MAC outputs data to theMT933 via the MII interface, on the TXD[3:0] bus.This data is synchronised to the rising edge ofTX_CLK. To indicate that there is valid data fortransmission on the MII, the MAC sets the TX_ENsignal active. This forces the MT933 device to take inthe data on the TXD[3:0] bus. This is serialised anddirectly encoded as Manchester data, before beingoutput on the TXOP/TXON differential output fortransmission through 1:Ö2 magnetics and onto thetwisted-pair.The transmit current is governed by the current throughthe TXREF10 pin, which must be grounded througha resistor as described in “External Components”.RX10 Clock RecoveryThe MT933 employs a digital delay line controlled bythe 100MHz Synthesizer DLL to derive a samplingclock from the incoming signal. The recovered clockruns at twice the data rate (nominally 20MHz). Whena signal is received from the Signal Detect block, it isused to strobe Link Pulses and Manchester encodedserial data.https://www.ichunt.com MT933The Manchester data stream will be decoded into a 4-bit parallel data bus, RXD[3:0]. The RXD bus isclocked out on RX_CLK rising. The MT933 mustdetect the first 4 bits of pre-amble before RX_DV isset high. When RX_DV is high, any Manchestercoding violation will set RX_ER high. RX_DV is resetby a continuous sequence of zeroes, or by the end-of-packet IDLE terminator (11 11 00 00). Whilst RX_DVis low, the data is invalid.100MHz SynthesizerThis synthesizer employs a delay-locked loop (DLL)to generate a 100MHz timing reference from the25MHz reference clock. This 100MHz reference isused by the 10BASE-T transmit and receive functionsand is divided by 5 to provide a 20MHz data strobe.The 20MHz clock is used to derive the 2.5 MHzTX_CLK in 10BASE-T mode. The synthesizer isdisabled when not in 10BASE-T mode.TX10 Pulse Shaper & FilterThe Pulse Shaper & Filter employs a digital FiniteImpulse Response filter (FIR) to pre-compensate forline distortion and to remove high frequencycomponents in accordance with the 802.3 Standard.The Pulse Shaper & Filter is disabled when not in10BASE-T mode.TX10 LatencyWhen connected to appropriate magnetics the latencythrough the TX10 path is less than 2BT (200ns) fordata transmissions. This timing is measured from therising edge of TX_CLK to the output of the transmitmagnetics. The TX10 path will not transmit up to thefirst two Manchester encoded bits of a datatransmission, as permitted by the 802.3 Standard.RX10 Filter & RX10 Signal DetectThese blocks work in unison to remove noise and toblock signals that do not achieve the voltage levelsspecified in 802.3. Signals that do not achieve therequired level are not sampled in the Clock Recoveryblock and are not passed to the outputs.RX10 LatencyWhen connected to appropriate magnetics the latencythrough the RX10 path is less than 6BT (600ns). Thistiming is measured from the input of the receivemagnetics to the rising edge of RX_CLK. The RX10path may ignore up to three Manchester encoded bitsat the start of data reception (802.3 allows up to 5bits).100Base-TX Operation100Mb/s Data Exchange on the MII Interface100Mb/s data is transferred across the MII with clockspeeds of 25MHz. The MAC outputs data to theMT933 via the MII interface, on the TXD[3:0] bus.This data is synchronised to the rising edge of TX_CLK.To indicate that there is valid data for transmission onthe MII, the MAC sets the TX_EN signal active. Thisforces the MT933 device to take in the data on theTXD[3:0] bus and replace the first octet of the MACpreamble with Start-of-Stream Delimiter (SSD)symbols to indicate the start of the Physical LayerStream.When the data transfer across the MII is complete,the MAC deasserts the TX_EN signal and the MT933adds End-of-Stream Delimiters (ESD) symbols ontothe end of the data stream. The complete data stream(the Physical Layer Stream) is encoded from 4 bitsinto 5 bits, scrambled, converted to MLT3 and drivento the TXOP and TXON pin differentially.The TX100 path is disabled when not in 100BASE-TXmode and, with the exception of the RX100 SignalDetect, the RX100 Receive Path is disabled when notin 100BASE-TX mode.125MHz SynthesizerThis synthesizer employs a phase-locked loop (PLL) togenerate a 125MHz timing reference from the 25MHzreference clock. This 125MHz reference is used by the100BASE-TX transmit function and is divided by 5 toprovide a 25MHz data strobe on TX_CLK. TX_CLK isfrequency and phase locked to the 25MHz referencewith a small phase offset. The synthesizer is disabledwhen not in 100BASE-TX mode.https://www.ichunt.com