mt8985apr中文资料_数据手册_IC数据表

1Zarlink Semiconductor Inc.Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.Features•256 x 256 channel non-blocking switch •Programmable frame integrity for wideband channels•Automatic identification of ST-BUS/GCI interface backplanes•Per channel tristate control•Patented message mode•Non-multiplexed microprocessor interface•Single +5 volt supply•Available in DIP-40, PLCC-44 and QFP-44 packages•Pin compatible with MT8980 deviceApplications•Medium size digital switch matrices•Hyperchannel switching (e.g., ISDN H0)•ST-BUS/MVIP™ interface functions•Serial bus control and monitoring•Centralized voice processing systems•Data multiplexerDescriptionThe MT8985 Enhanced Digital Switch device is anupgraded version of the popular MT8980D DigitalSwitch (DX). It is pin compatible with the MT8980D andretains all of the MT8980D's functionality. This VLSIdevice is designed for switching PCM-encoded voiceor data, under microprocessor control, in digitalexchanges, PBXs and any ST-BUS/MVIPenvironment. It provides simultaneous connections forup to 256 64kb/s channels. Each of the eight serialinputs and outputs consist of 32 64 kbit/s channelsmultiplexed to form a 2048 kbit/s stream. As the mainfunction in switching applications, the device providesper-channel selection between variable or constantthroughput delays. The constant throughput delayfeature allows grouped channels such as ISDN H0 tobe switched through the device maintaining itssequence integrity. The MT8985 is ideal for mediumsized mixed voice/data switch and voice processingapplications.September 2005Ordering InformationMT8985AE40 Pin PDIPTubesMT8985AP44 Pin PLCCTubesMT8985AL44 Pin MQFPTraysMT8985APR44 Pin PLCCTape & ReelMT8985AP144 Pin PLCC*TubesMT8985APR144 Pin PLCC*Tape & ReelMT8985AE140 Pin PDIP*TubesMT8985AL144 Pin MQFP*Trays*Pb Free Matte Tin-40°C to +85°CCMOS ST-BUSTM FamilyMT8985 Enhanced Digital SwitchData Sheet

Figure 1 - Functional Block Diagram

STo0STo1STo2STo3STo4STo5STo6STo7SerialtoParallelConverterDataMemoryFrameCounter

Control Register

Control InterfaceOutputMUX

ConnectionMemoryParalleltoSerialConverter

CSR/WA5/A0DTAD7/D0CSToC4iF0iVDDVSSODE

STi0STi1STi2STi3STi4STi5STi6STi7

DShttps://www.ichunt.comMT8985Data Sheet

2Zarlink Semiconductor Inc.Changes SummaryThe following table captures the changes from the May 2005 issue.

Figure 2 - Pin ConnectionsPageItemChange7Figure 3 - “Address Memory Map“•corrected Address Memory Map

DTASTi0STi1STi2STi3STi4STi5STi6STi7VDDF0iC4iA0A1A2A3A4A5DSCSToODESTo0STo1STo2STo3STo4STo5STo6STo7VSSD0D1D2D3D4D5D6D7CS1654324443424140789101112131415163938373635343332313023181920212224252627281729STi3STi4STi5STi6STi7VDDF0iC4iA0A1A2STo3STo4STo5STo6STo7VSSD0D1D2D3D4NCSTi1DTAODESTo1NCSTi2STi0CSToSTo0STo2

NCA4DSCSD6NCA3A5R/WD7

40 PIN PLASTIC DIP44 PIN PLCC2345678910111213141516171819201

R/W4039383736353433323130292827262524232221D53944434241403837363534123456789103332313029282726252417121314151618192021221123

44 PIN QFPSTi3STi4STi5STi6STi7VDDF0iC4iA0A1A2

NCA4DSCSD6NCA3A5R/WD7D5STo3STo4STo5STo6STo7VSSD0D1D2D3D4NCSTi1DTAODESTo1NCSTi2STi0CSToSTo0STo2

https://www.ichunt.comMT8985Data Sheet

3Zarlink Semiconductor Inc.Pin DescriptionPin #NameDescription40 DIP44PLCC44QFP1240DTAData Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.2-93-57-1141-431-5STi0-STi7ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 channels at data rates of 2.048 Mbit/s.10126VDD+5 Volt Power Supply rail. 11137F0iFrame Pulse (Input): This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. 12148C4iClock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.13-1815-1719-219-1113-15A0-A5Address 0 to 5 (Inputs). These lines provide the address to MT8985 internal registers.192216DSData Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. 202317R/WRead/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. 212418CSChip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories.22-2925-2729-3319-2123-27D7-D0Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data in the internal control register, connect memory high, connect memory low and data memory.303428VSSGround Rail.31-3835-3941-4329-3335-37STo7-STo0ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These streams are composed of 32 channels at data rates of 2.048 Mbit/s.394438ODEOutput Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control.40139CSToControl ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations.6, 18,28, 4012,2234, 44NCNo Connection.https://www.ichunt.com