BGY888中文资料

色码解析表0号色码：不织（空针）说明：不织。

自动翻针．．：前床编织，即前单面。

自动翻针1号色码：前床编织说明．．：后床编织，即后单面。

自动翻针2号色码：后床编织说明．．：前后床编织，即四平。

自动翻针3号色码：前后床编织说明．．：前床集圈。

不自动翻针4号色码：前吊目说明．．：后床集圈。

不自动翻针。

5号色码：后吊目说明．．：前床编织后床集圈。

自动翻针6号色码：前编织后吊目说明．．：前床集圈后床编织。

自动翻针7号色码：前吊目后编织说明．．：前床编织不自动翻针。

8号色码：前编织(无连接) 说明．．9号色码：后编织(无连接) 说明：后床编织不自动翻针。

．．：前后床都编织，即四平。

不自动翻针。

10号色码：前后编织(无连接) 说明．．11号色码：前粗目12号色码：后粗目13号色码：前后粗目(两边)注：11、12、13三个色码为二段度目色码(暂不使用)：前后床都集圈。

不自动翻针14号色码：前后吊目说明．．15号色码：前落布说明：将前床线圈落掉。

单独一行时不自动翻针．．：只带纱嘴，无编织动作。

不自动翻针16号色码：无选针说明．．17号色码：后落布说明：将后床线圈落掉。

单独一行时不自动翻针．．：将前床线圈翻到后床，不编织。

不自动翻针100号色码：翻针至后(无编织) 说明．．110号色码：翻针至前(无编织) 说明：将后床线圈翻到前床，不编织。

不自动翻针．．同时编织和翻针色码：前床编织，再把前床线圈翻到后床。

不自动翻针20号色码：前编织翻针至后说明．．：前床编织，再把后床线圈翻到前床。

不自动翻针30号色码：前编织翻针至前说明．．：后床编织，再把后床线圈翻到前床。

不自动翻针40号色码：后编织翻针至前说明．．：后床编织，再把前床线圈翻到后床。

不自动翻针50号色码：后编织翻针至后说明．．：先把后床线圈翻到前床，再前床编织。

自动翻针70号色码：翻针至前且前编织说明．．90号色码：翻针至后且后编织说明：先把前床线圈翻到后床，再后床编织。

BY448GPVishay General SemiconductorDocument Number: 88543For technical questions within your region, please contact one of the following:Miniature Clamper/Damper Glass Passivated RectifierFEATURES•Superectifier structure for high reliability application •Cavity-free glass-passivated junction •Low forward voltage drop •Typical I R less than 0.1 µA •High forward surge capability•Meets environmental standard MIL-S-19500 •Solder dip 260 °C, 40 s•Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/EC TYPICAL APPLICATIONSFor use in high voltage rectification of power supplies,inverters, converters and freewheeling diodes specially designed for clamping circuits, horizontal deflection systems and damper applications.MECHANICAL DATACase: DO-204AC, molded epoxy over glass body Epoxy meets UL 94V-0 flammability ratingTerminals: Matte tin plated leads, solderable per J-STD-002 and JESD22-B102E3 suffix for consumer grade, meets JESD 201 class 1A whisker test, HE3 suffix for high reliability grade (AEC Q101 qualified), meets JESD 201 class 2whisker testPolarity:Color band denotes cathode endPRIMARY CHARACTERISTICSI F(AV) 1.5 A V RRM 1650 V I FSM 40 A I R 5.0 µA V F 1.6 V T J max.175 °CMAXIMUM RATINGS (T A = 25 °C unless otherwise noted)PARAMETER SYMBOL BY448GP UNITMaximum repetitive peak reverse voltage V RRM 1650V Maximum RMS voltage V RMS 1150V Maximum DC blocking voltageV DC1650VMaximum average forward rectified current 0.375" (9.5 mm)lead length at T A = 50 °CI F(AV) 1.5 A Peak forward surge current 8.3 ms single half sine wave superimposed on rated loadI FSM 40 A Maximum full load reverse current, full cycle average, 0.375" (9.5 mm) lead length at T A = 100 °CI R(AV) 50µA Operating junction and storage temperature rangeT J , T STG- 65 to + 175°C元器件交易网BY448GPVishay General Semiconductor For technical questions within your region, please contact one of the following:Document Number: 88543Note:(1) Pulse test: 300 µs pulse width, 1 % duty cycleNote:(1) Thermal resistance from junction to ambient at 0.375" (9.5 mm) lead length, P.C.B. mountedNote:(1) Automotive grade AEC Q101 qualifiedRATINGS AND CHARACTERISTICS CURVES(T A = 25 °C unless otherwise noted)ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAMETER TEST CONDITIONS SYMBOL BY448GP UNITMaximum instantaneous forward voltage (1)I F = 3.0 A V F 1.6V Maximum reverse current V R = 1650 VT A = 25 °C T A = 100 °CI R 5.0 100 µA Maximum reverse recovery time I F = 0.5 A, I R = 50 mA t rr 20µs Reverse recovery time I F = 0.5 A,I R = 1.0 A, I rr = 0.25 A typical maximumt rr 0.5 1.5 µs Typical junction capacitance 4.0 V , 1 MHzC J15pFTHERMAL CHARACTERISTICS (T A = 25°C unless otherwise noted)PARAMETER SYMBOL BY448GP U NITTypical thermal resistance (1) R θJA 55°C/WORDERING INFORMATION (Example)PREFERRED P/N UNIT WEIGHT (g)PREFERRED PACKAGE CODEBASE QUANTITYDELIVERY MODEBY448GP-E3/540.42554400013" diameter paper tape and reelBY448GP-E3/730.425732000Ammo pack packaging BY448GPHE3/54 (1)0.42554400013" diameter paper tape and reelBY448GPHE3/73 (1)0.425732000Ammo pack packagingFigure 1. Forward Current Derating Curve Figure 2. Maximum Non-Repetitive Peak Forward Surge Current元器件交易网BY448GPVishay General SemiconductorDocument Number: 88543For technical questions within your region, please contact one of the following:PACKAGE OUTLINE DIMENSIONS in inches (millimeters)Figure 3. Typical Instantaneous Forward Characteristics Figure 4. Typical Reverse CharacteristicsFigure 5. Typical Junction Capacitance元器件交易网Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

0.4 Ω CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP PackagesADG888Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.FEATURESFUNCTIONAL BLOCK DIAGRAMIN1S2B S2AS1B S1AIN2S4B S4AS3B S3A05432-001SWITCHES SHOWN FOR A LOGIC 1 INPUT1.8 V to 5.5 V operation Ultralow on resistance 0.4 Ω typical0.6 Ω maximum at 5 V supplyExcellent audio performance, ultralow distortion 0.07 Ω typical0.14 Ω maximum R ON flatness High current carrying capability 400 mA continuous600 mA peak current at 5 VAutomotive temperature range: −40°C to +125°C Rail-to-rail switching operationTypical power consumption (<0.1 μW)APPLICATIONSCellular phones PDAsMP3 players Power routingFigure 1.Battery-powered systems PCMCIA cards ModemsAudio and video signal routing Communication systems Data switchingGENERAL DESCRIPTIONThe ADG888 is available in a 4 × 4 bump, 2.0 mm × 2.0 mm WLCSP; a 4 mm × 4 mm, 16-lead LFCSP; and a 16-lead TSSOP . These packages make the ADG888 the ideal solution for space-constrained applications.The ADG888 is a low voltage, dual DPDT (double pole double throw) CMOS device optimized for high performance audio switching. With its low power and small physical size, it is ideal for portable devices.PRODUCT HIGHLIGHTSThis device offers ultralow on resistance of less than 0.8 Ω over the full temperature range making it an ideal solution for applications requiring minimal distortion through the switch. The ADG888 also has the capability of carrying large amounts of current, typically 400 mA at 5 V operation.1. <0.6 Ω over full temperature range of −40°C to +125°C.2. High current handling capability (400 mA continuous current at 5 V).3. Low THD + N (0.008% typical).When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The ADG888 exhibits break-before-make switching action. 4. Tiny 2 mm × 2 mm, 16-ball WLCSP package, and 16-lead LFCSP and TSSOP packages.ADG888Rev. 0 | Page 2 of 16TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Product Highlights...........................................................................1 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................5 ESD Caution..................................................................................5 Pin Configuration and Function Descriptions..............................6 Truth Table.....................................................................................6 Typical Performance Characteristics..............................................7 Test Circuits........................................................................................9 Terminology....................................................................................11 Outline Dimensions.......................................................................12 Ordering Guide.. (13)REVISION HISTORY7/05—Revision 0: Initial VersionADG888Rev. 0 | Page 3 of 16SPECIFICATIONSV DD = 4.2 V to 5.5 V , GND = 0 V , unless otherwise noted.1Table 1.−40°C −40°CParameter +25°C to +85°C to+125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (R ON ) 0.4 Ω typ V DD = 4.2 V, V S = 0 V to V DD , I DS = 100 mA; 0.48 0.55 0.6 Ω max See Figure 16On Resistance Match Between 0.04 Ω typ V DD = 4.2 V, V S = 2.2 V, I DS = 100 mA Channels (∆R ON ) 0.06 0.07 0.075 Ω max On Resistance Flatness (R FLAT (ON)) 0.07 Ω typ V DD = 4.2 V, V S = 0 V to V DD , 0.11 0.13 0.14 Ω max I DS = 100 mA LEAKAGE CURRENTS V DD = 5.5 V Source Off Leakage I S (OFF) ±0.2 nA typ V S = 1 V/4.5 V, V D = 4.5 V/1 V; see Figure 17Channel On Leakage I D , I S (ON) ±0.2 nA typ V S = V D = 1 V or 4.5 V; see Figure 18DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.8 V max Input Current I INL or I INH 0.005 μA typ V IN = V INL or V INH ±0.1 μA max C IN , Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS 2 t ON 22 ns typ R L = 50 Ω, C L = 35 pF 30 33 35 ns max V S = 3 V/0 V; see Figure 19t OFF 13 ns typ R L = 50 Ω, C L = 35 pF 17 18 19 ns max V S = 3 V/0 V; see Figure 19Break-Before-Make Time Delay (t BBM ) 9 ns typ R L = 50 Ω, C L = 35 pF 5 ns min V S1 = V S2 = 3 V; see Figure 20Charge Injection 70 pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF; see Figure 21Off Isolation −67 dB typ R L = 50 Ω, C L = 5 pF, f = 100 kHz; see Figure 22Channel-to-Channel Crosstalk −99 dB typ Adjacent channel; R L = 50 Ω, C L = 5 pF,f = 100 kHz; see Figure 25−67 dB typ Adjacent switch; R L = 50 Ω, C L = 5 pF , f = 100 kHz;see Figure 23Total Harmonic Distortion (THD + N) 0.008 % R L = 32 Ω, f = 20 Hz to 20 kHz, V S = 3 V p-p Insertion Loss −0.03 dB typ R L = 50 Ω, C L = 5 pF; see Figure 24−3 dB Bandwidth 29 MHz typ R L = 50 Ω, C L = 5 pF; see Figure 24C S (OFF) 58 pF typ C D , C S (ON) 110 pF typ POWER REQUIREMENTS V DD = 5.5 V I DD 0.003 μA typ Digital inputs = 0 V or 5.5 V 1 4 μA max1 Temperature range, Y version: −40°C to +125°C.2Guaranteed by design, not subject to production test.ADG888Rev. 0 | Page 4 of 16V DD = 2.7 V to 3.6 V , GND = 0 V , unless otherwise noted 1. Table 2.−40°C −40°C Parameter +25°C to +85°C to +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (R ON ) 0.5 Ω typ V DD = 2.7 V, V S = 0 V to V DD , 0.7 0.75 0.8 Ω max I S = 100 mA; see Figure 16On Resistance Match Between 0.045 Ω typ V DD = 2.7 V, V S = 1 V, Channels (∆R ON ) 0.065 0.07 0.075 Ω max I S = 100 mA On Resistance Flatness (R FLAT (ON)) 0.16 Ω typ V DD = 2.7 V, V S = 0 V to V DD , 0.25 Ω max I S = 100 mA LEAKAGE CURRENTS V DD = 3.6 V Source Off Leakage I S (OFF) ±0.2 nA typ V S = 1 V/2.6 V, V D = 2.6 V/1 V; see Figure 17Channel On Leakage I D , I S (ON) ±0.2 nA typ V S = V D = 1 V or 2.6 V; see Figure 18DIGITAL INPUTS Input High Voltage, V INH 1.3 V min Input Low Voltage, V INL 0.8 V max Input Current I INL or I INH 0.005 μA typ V IN = V INL or V INH ±0.1 μA max C IN , Digital Input Capacitance 2 pF typ DYNAMIC CHARACTERISTICS 2 t ON 28 ns typ R L = 50 Ω, C L = 35 pF; see Figure 19 43 47 50 ns max V S = 1.5 V/0 V t OFF 13 ns typ R L = 50 Ω, C L = 35 pF; see Figure 19 20 21 22 ns max V S = 1.5 V/0 V Break-Before-Make Time Delay (t BBM ) 14 ns typ R L = 50 Ω, C L = 35 pF 5 ns min V S1 = V S2 = 1.5 V; see Figure 20Charge Injection 50 pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF; see Figure 21Off Isolation −67 dB typ R L = 50 Ω, C L = 5 pF, f = 100 kHz; see Figure 22Channel-to-Channel Crosstalk −99 dB typ Adjacent channel; R L = 50 V, C L = 5 pF, f = 100 kHz;see Figure 25−67 dB typ Adjacent switch; R L = 50 Ω, C L = 5 pF, f = 100 kHz;see Figure 23Total Harmonic Distortion (THD + N) 0.01 % R L = 32 Ω, f = 20 Hz to 20 kHz, V S = 1 V p-p Insertion Loss −0.04 dB typ R L = 50 Ω, C L = 5 pF; see Figure 24–3 dB Bandwidth 29 MHz typ R L = 50 Ω, C L = 5 pF; see Figure 24C S (OFF) 60 pF typ C D , C S (ON) 115 pF typ POWER REQUIREMENTS V DD = 3.6 V I DD 0.003 μA typ Digital inputs = 0 V or 3.6 V 1 2 μA max1 Temperature range, Y version: −40°C to +125°C.2Guaranteed by design, not subject to production test.ADG888Rev. 0 | Page 5 of 16ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Parameter RatingV DD to GND−0.3 V to +6 VAnalog Inputs 1, Digital Inputs 1−0.3 V to V DD + 0.3 V or 10 mA, whichever occurs firstPeak Current, S or D600 mA (pulsed at 1 ms, 10% duty cycle max) Continuous Current, S or D 400 mA Only one absolute maximum rating may be applied at any one time. Operating Temperature RangeAutomotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C16-Lead TSSOP Package θJA Thermal Impedance (4-Layer Board)112°C/W θJC Thermal Impedance 27.6°C/W 16-Lead WLCSP PackageθJA Thermal Impedance (4-Layer Board) 130°C/W 16-Lead LFCSP Package θJA Thermal Impedance (4-Layer Board)30.4°C/W IR Reflow, Peak Temperature <20 sec235°C1Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ADG888Rev. 0 | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONSS1A D1S1B S2AD2S2B V DD S4AD4S4B S3A IN1IN2D3S3B GND 05432-004D1S1B S2B D211S4B 12D410S3B 9D35S 2A 6I N 17I N 28S 3A 15V D D16S 1A14G N D 13S 4A05432-003TOP VIEW(BUMP SIDE DOWN)Not to Scale05432-002Figure 4. 16-Lead TSSOP (RU-16)Figure 3. 16-Lead LFCSP_VQ (CP-16-4)TOP VIEW(Solder Bumps on Opposite Side) Figure 2. 16-Lead WLCSP (CB-16)Table 4. Pin Function DescriptionsBump No. WL CSP Pin No. LFCSP_VQ Pin No. TSSOP Mnemonic Description2c 15 1 V DD Most Positive Power Supply Potential. 2b 14 16 GND Ground (0 V) Reference.1b, 1c, 2a, 2d, 3a, 3d, 4b, 4c 2, 3, 5, 8, 10, 11, 13, 16 2, 4, 5, 7, 10, 12, 13, 15 S Source Terminal. May be an input or output. 1a, 1d, 4a, 4d 1, 4, 9, 12 3, 6, 11, 14 D Drain Terminal. May be an input or output. 3b, 3c 6, 7 8, 9 INLogic Control Input.TRUTH TABLETable 5.Logic (IN1/IN2) Switch 1A/2A/3A/4ASwitch 1B/2B/3B/4B0 Off On 1 OnOffADG888Rev. 0 | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS0.400505432-005V S ,V D (V)R O N (Ω)0.350.300.250.200.150.100.0512340.700 3.005432-008V S ,V D (V)R O N (Ω)0.60.50.40.30.20.10.5 1.0 1.5 2.0 2.5Figure 5. On Resistance vs. V D (V S ) V DD = 4.2 V to 5.5 VFigure 8. On Resistance vs. V D (V S ) for DifferentTemperature, V DD = 3 V0.605432-006V S ,V D (V)R O N (Ω)0.50.40.30.20.15010015020025030035040000.5 1.0 1.5 2.02.53.0 3.54.0 4.55.0V D (V)Q I N J (p C )05432-009Figure 6. On Resistance vs. V D (V S ) VDD = 2.7 V to 3.6 VFigure 9. Charge Injection vs. Source Voltage0.4500 5.005432-007V S ,V D (V)R O N (Ω)0.400.350.300.250.200.150.100.050.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5051015202530354045–40–20020406080100120TEMPERATURE (°C)T I M E (n s )05432-010Figure 7. On Resistance vs. V D (V S ) for DifferentTemperature, V DD = 5 VFigure 10. t ON /t OFF Times vs. TemperatureADG888Rev. 0 | Page 8 of 1600.0050.0100.0150.0200.0252k4k6k8k 10k 12k 14k 16k 18k 20kFREQUENCY (Hz)T H D + N (%)05432-014–10–9–8–7–6–5–4–3–2–1010k100k1M10M100MFREQUENCY (Hz)O N R E S P O N S E (d B )05432-011Figure 11. BandwidthFigure 14. Total Harmonic Distortion + Noise (THD + N)–100–80–60–40–20201001k 10k 100k 1M 10M 100MFREQUENCY (Hz)A T T E N U A T I O N (dB )–120–100–80–60–40–2001001k 10k 100k 1M 10M 100MFREQUENCY (Hz)A T T E N U A T I O N (dB )Figure 12. Off Isolation vs. FrequencyFigure 15. AC PSRR–140–120–100–80–60–40–2001001k10k 100k 1M10M 100MFREQUENCY (Hz)A T T E N U A T I O N (dB )05432-013Figure 13. Crosstalk vs. FrequencyADG888Rev. 0 | Page 9 of 16TEST CIRCUITSV SV05432-016V DNC05432-017Figure 16. On ResistanceFigure 17. Off LeakageFigure 18. On Leakage05432-018V V INVON , t OFFV OUTV IN50%50%0VV OUTV05432-019BBM05432-020V INV OUTV OUTNCFigure 21. Charge InjectionADG888Rev. 0 | Page 10 of 16INSERTION LOSS = 20 logV OUT WITH SWITCH V OUT WITHOUT SWITCH05432-02205432-021V OFF ISOLATION = 20 logV OUTVSFigure 22. Off Isolation Figure 24. Bandwidth05432-024V L ΩCHANNEL-TO-CHANNEL CROSSTALK = 20 logV OUT VS05432-025ΩCHANNEL-TO-CHANNEL CROSSTALK = 20 logV OUT VSFigure 25. Channel-to-Channel Crosstalk (S1A to S2A)Figure 23. Channel-to-Channel Crosstalk (S1A to S1B)TERMINOLOGYI DDPositive supply current.V D (V S)Analog voltage on Terminal D and Terminal S.R ONOhmic resistance between Terminal D and Terminal S.R FLAT (ON)Flatness is defined as the difference between the maximum and minimum value of on resistance as measured.ΔR ONOn resistance match between any two channels.I S (OFF)Source leakage current with the switch off.I D, I S (ON)Channel leakage current with the switch on.V INLMaximum input voltage for Logic 0.V INHMinimum input voltage for Logic 1.I INL (I INH)Input current of the digital input.C S (OFF)Off switch source capacitance. Measured with reference to ground.C D, C S (ON)On switch capacitance. Measured with reference to ground.C INDigital input capacitance. t ONDelay time between the 50% and the 90% points of the digital input and switch on condition.t OFFDelay time between the 50% and the 90% points of the digital input and switch off condition.t BBMOn or off time measured between the 80% points of both switches when switching from one to another.Charge InjectionA measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.Off IsolationA measure of unwanted signal coupling through an off switch. CrosstalkA measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. This is specified for two conditions:Adjacent channel, that is, S1A to S2A, S1B to S2B, S3A toS4A, or S3B to S4B.Adjacent switch, that is, S1A to S1B, S2A to S2B, S3A toS3B, or S4A to S4B.−3 dB BandwidthThe frequency at which the output is attenuated by 3 dB.On ResponseThe frequency response of the on switch.Insertion LossThe loss due to the on resistance of the switch.THD + NThe ratio of the harmonic amplitudes plus signal noise to the fundamental.OUTLINE DIMENSIONS1ABCD234Figure 26. 16-Ball Wafer Level Chip Scale Package [WLCSP](CB-16)Dimensions shown in millimetersCOPLANARITY0.10COMPLIANT TO JEDEC STANDARDS MO-153-ABFigure 27. 16-Lead Thin Shrink Small Outline Package [TSSOP](RU-16)Dimensions shown in millimetersCOMPLIANT TO JEDEC STANDARDS MO-220-VGGCPLANEFigure 28. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]4 mm × 4 mm Body, Very Thin Quad(CP-16-4)Dimensions shown in millimetersORDERING GUIDEModel Temperature Range Package Description Package Option Branding1 ADG888YRUZ2−40°C to +125°C 16 Lead Thin Shrink Small Outline Package (TSSOP) RU-16ADG888YRUZ-REEL2−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16ADG888YRUZ-REEL72−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16ADG888YCPZ-REEL2−40°C to +125°C 16- Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 S0D ADG888YCPZ-REEL72−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 S0D ADG888YCBZ-REEL2−40°C to +125°C 16-Ball Wafer Level Chip Scale Package (WLCSP) CB-16 S0D ADG888YCBZ-REEL72−40°C to +125°C 16-Ball Wafer Level Chip Scale Package (WLCSP) CB-16 S0D1 Branding on these packages is limited to three characters due to space constraints.2 Z = Pb-free part.NOTESNOTESNOTES©2005 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.D05432-0-7/05(0)。