U637H256DK25G1中文资料

1
Rev 1.1
元器件交易网
U637H256
Block Diagram
A5 A6 A7 A8 A9 A11 A12 A13 A14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Input Buffers
Row Decoder
EEPROM Array 512 x (64 x 8)
Signal Name A0 - A14 DQ0 - DQ7 E G W VCC VSS
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
STORE
SRAM Array
RECALL
512 Rows x 64 x 8 Columns
Column I/O Column Decoder
A0 A1 A2 A3 A4 A10
Power Control
Store/ Recall Control
VCC VSS
VCC
Software Detect
A0 - A13
STK Control #ML0056
2
Rev 1.1
August 15, 2006
元器件交易网
Recommended Operating Conditions Power Supply Voltage
Input Low Voltage
Input High Voltage
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode
25 ns Access Time
and nonvolatile mode. In SRAM
10 ns Output Enable Access
mode, the memory operates as an
Software initiated STORE
cally erasable PROM (EEPROM)
Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in
element incorporated in each static memory cell. The SRAM can be read and written an unlimited num-
G
E W
Truth Table forSRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
Internal Read
L
H
H
High-Z High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
VCC
-0.5
7
V
Input Voltage
VI
-0.3
VCC+0.5
V
Output Voltage
VO
-0.3
VCC+0.5
V
Power Dissipation
PD
1
W
Operating Temperature
The U637H256 is pin compatible with standard SRAMs and standard battery backed SRAMs.
Pin Configuration
A14 A12
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
28
0 to 70 °C
capacitor. Transfers from the
-40 to 85°C QS 9000 Quality Standard
EEPROM to the SRAM (the RECALL operation) take place
(MIL STD 883C M3015.7)
Unlimited RECALL cycles from SRAM to the EEPROM (the
EEPROM
Single 5 V ± 10 % Operation Operating temperature range:
STORE operation) take place automatically upon power down using charge stored in an integrated
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
2
27
3
Hale Waihona Puke 26425
5
24
6
23
7
22
8 PDIP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Top View
August 15, 2006
STK Control #ML0056
Pin Description
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
U637H256
Symbol
Conditions
VCC
VIL
-2 V at Pulse Width 10 ns permitted
VIH
Min. 4.5 -0.3 2.2
Max. 5.5 0.8 VCC+0.3
Unit V V V
DC Characteristics
Operating Supply Currentb
automatically on power up. The
RoHS compliance and Pb- free U637H256 combines the high per-
Package: PDIP28 (600 mil)
formance and ease of use of a fast
EEPROM
ber of times, while independent
Automatic RECALL on Power Up nonvolatile data resides in
Software RECALL Initiation
EEPROM. Data transfers from the
Time
ordinary static RAM. In nonvolatile
ICC = 15 mA typ. at 200 ns Cycle operation, data is transferred in
Time
parallel from SRAM to EEPROM or
Unlimited Read and Write Cycles from EEPROM to SRAM. In this
Average Supply Current duringc STORE
Operating Supply Currentb at tcR = 200 ns (Cycling CMOS Input Levels)
Standby Supply Currentd (Cycling TTL Input Levels)
元器件交易网
Not Recommended For New Designs
U637H256
CapStore 32K x 8 nvSRAM
Features
Description
High-performance CMOS non- The U637H256 has two separate
SRAM with nonvolatile data inte-
grity. STORE cycles also may be initiated under user control via a software sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.