MYC-AM335X核心板引脚定义说明列表

Board Porting\Bring up using Processor SDK RTOS for AM335xProcessor SDK RTOS component known as board library consolidates all the board-specific information so that all the modifications made when moving to a new custom platform using the SOC can be made in the source of this library.There are three different components in PRSDK that help in porting and bring up of a custom board:∙Board library updatesa.PLL Clocking and PRCMb.Pin mux Updatec.DDR Configurationd.Peripheral instances updates∙Diagnostics tests∙Boot loader updatesBoard Library Updates in Processor SDK RTOS:PLL ClockingThere are two places where the device PLL configurations are performed when using Processor SDK RTOS and CCS.Debug environment:Debug environment refers to development setup where code is debugged using JTAG emulator on the SOC. The PRSDK software relies on the GEL file that is part of the target configuration to setup the clocks and the DDR for the device. The CCS GEL file for AM335x platforms is located in the CCS package at the location ccsv7\ccs_base\emulation\boards\<boardName>For example for beagle bone black, the files can be found atccsv7\ccs_base\emulation\boards\beaglebone\gelThe GEL is the first piece of software that should be brought up on a custom board.Production environment:Production environment refers to the setup when the base application is booted from a boot media like a flash memory or host interface. In this environment, the bootloader sets performs all the SOC and board initialization and copies the application from flash memory to the device memory.The clock setup in the bootloader code can be located atpdk_am335x_x_x_x\packages\ti\starterware\bootloader\src\am335xUsers can choose to use the platform clocking similar to one of TI reference platforms or can modify them as per their application requirements. By default the PLL settings are setup for OPP_NOM settings (MPU= 600 MHz.)TI provides Clock Tree tool to allow users to simulate the clocking on the SOC. For quick reference of the multiplier and divider settings to change the PLL setting is provided in the spreadsheetAM335x_DPLL_CALCv3.xlsx.After modifying the clocking in the bootloader, users need to rebuild the bootloader using instructions provided in Processor_SDK_RTOS_BOOT_AM335x/AM437xPRCM Modules Enable:PRCM Module Enable is required to turn on the power domain and the clocking to each of the modules on the SOC. The PRCM Enable calls to enable each module are made from the functionBoard_moduleClockInit which is found in the location.pdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\bbbAM335x.cCheck every instance and peripheral required in the application platform and enable the module in the board library.For example to use three UARTs 0, 1 and 4, ensure that you have the following code as part of the board library setup:/* UART */status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 0U, 0U);status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 1U, 0U);status = PRCMModuleEnable(CHIPDB_MOD_ID_UART, 4U, 0U);Note: PRCMEnable function is defined in pdk_am335x_1_0_9\packages\ti\starterware\soc\am335x Pinmux updates in the Board library:Generating a New PinMux Configuration Using the PinMux Utility: This procedure uses the cloud-based pinmux utilityNavigate to ${PDK_INSTALL_DIR}\packages\ti\starterware\tools\pinmux_config\am335x and Load beaglebone_black_configAdd and remove peripheral instances and select the appropriate use cases required for development based on the application platform requirements and resolve all conflicts.Refer Pin_Mux_Utility_for_ARM_MPU_ProcessorsPost Processing steps:1.Change the Category filter to starterware and download the pinmux files am335x_pimnmux.hand am335x_pinmux_data.c2.At the bottom of am335x_pinmux.h change extern pinmuxBoardCfg_t gAM335xPinmuxData[];to extern pinmuxBoardCfg_t gBbbPinmuxData[];3.Change am335x_pinmux_data.c to am335x_beagleboneblack_pinmux_data.c.4.Change gAM335xPinmuxData to gBbbPinmuxData at the end of the file in file5.am335x_beagleboneblack_pinmux_data.c.Replace the existing files with the new files and rebuild the board library using the instructions in the section Rebuilding board Library in Processor SDK RTOS:Updating DDR settings:Similar to clock and PLL settings, DDR initialization is configured in the Debug environment through GEL files and in production environment using bootloader source files.TI provides AM335x_EMIF_Configuration_tips which contains a spreadsheet to enter the timing from the DDR datasheet to compute the EMIF timing number required to initialize DDR.We strongly recommend changing the value and testing using GEL files before using them in the bootloader software. For Sanity test, you can perform read/write tests using CCS Memory Browser or run the diagnostic memory read/write test that we provide in diagnostics package here:PDK_INSTALL_PATH\packages\ti\board\diag\memOnce the DDR timings have been confirmed, you can use the settings in the file:PDK_INSTALL_PATH \packages\ti\starterware\bootloader\src\am335x\sbl_am335x_platform_ddr.c Peripheral initialization:The board library is responsible for most of the SOC initialization but it also setup some board level components such as ethernet PHY and debug UART and I2C for reading board ID from EEPROM. All of the other peripheral instances and initialization needs to be done from the application level.For example for beagleboneblack, the peripheral initialization are performed from the source filepdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\bbbAM335x_lld_init.cThe debug UART instance, I2C Addresses are set using the file board_cfg.h found under:pdk_am335x_1_0_9\packages\ti\board\src\bbbAM335x\includeDefault UART instance is set to 0 in the board library. The Board initialization will configure the UART instance 0 to send binary log data to serial console using the Board_UARTInit function. If you wish to use more UART instances then we recommend linking in the UART driver in the application and using UART_open() and UART_stdioInit API calls from the application.Each peripheral driver in the Processor SDK RTOS has a SOC configuration that provides the interrupt numbers, base address, EDMA channels which can be updated using the file <peripheral>_soc.c file. This is used as default setup for initializing the driver instance. It can be overridden from the application using peripheral_getSOCInitCfg() and peripheral_setSOCInitCfg()For Example: All instances of UART for AM335x have been mapped in the filepdk_am335x_1_0_9\packages\ti\drv\uart\soc\am335x\UART_soc.cSystem integrators need to ensure that no interrupt numbers and EDMA resource conflicts exist in the SOC configuration for all drivers used in the system.To exercise three UARTs in the system, users can use the following code://Setup Debug UARTboardCfg = BOARD_INIT_PINMUX_CONFIG |BOARD_INIT_MODULE_CLOCK |BOARD_INIT_UART_STDIO;Board_init(boardCfg);// Open Additional UART Instances:/* UART SoC init configuration */UART_initConfig(false);/* Initialize the default configuration params. */UART_Params_init(&uartParams);// Open UART Instance 1uartTestInstance =1;uart1 = UART_open(uartTestInstance, &uartParams);//Open UART Instance 4uartTestInstance = 4;uart4 = UART_open(uartTestInstance, &uartParams);BoardID Detect:TI supports multiple evaluation and reference platforms for AM335x hence the hardware platforms are populated with an EEPROM which contains information that identifies the hardware and its revision. The board library and software components read the boardID and initialize the platform based on the boardID. The BoardID_detect function can be found in the source in the file bbbAM335x_info.c in the board library and board_am335x.c in the bootloader source at:<PDK_INSTALL_PATH>\packages\ti\starterware\board\am335xRebuilding board Library in Processor SDK RTOS:While Creating a new folder for the custom board is an option users can explore, TI recommends that users make there changes in existing board package using either bbbAM335x, evmAM335x oriceAM335x folder to avoid spending additional effort to modify the build files for including the customBord.Once all the update to the board library are completed, the board library can be updated using the following instructions.Instructions to rebuild board library:Setup Processor SDK build environment before following steps provided below.cd pdk_am335x_1_0_9\packagesgmake board_libFor a specific board users are required to provide the LIMIT_BOARDS argument.LIMIT_BOARDS : evmAM335x icev2AM335x iceAMIC110 bbbAM335x skAM335xFor Example for beagleboneblack, users can use the following build option:gmake board_lib LIMIT_BOARDS=bbbAM335xDiagnostics:After the board library is built, we highly recommend that you create a diagnostics package similar to one provided in board library to test different interfaces functionally during board bring up.The diagnostics package can be located at pdk_am335x_1_0_9\packages\ti\board\diag. These are simple bare-metal tests that use peripheral drivers to help functionally validate the pins and interfaces.Documentation for all available diagnostic tests is provided here:/index.php/Processor_SDK_RTOS_DIAGBootloader in Processor SDK RTOS:As part of the production flow, users are required to develop/port flashing and booting utilities so the application can be launched on the custom board with JTAG. TI provides a bootloader mechanism where the ROM bootloader loads a secondary bootloader on the onchip memory that initializes the SOC and DDR and then copies the application into DDR memory.The boot process and flashing tools have been described in detail in the following article that is part of processor SDK RTOS Software developer`s guide:/index.php/Processor_SDK_RTOS_BOOT_AM335x/AM437x#Building_the_B ootloader。

AM335XGPIO详解1、配置GPIO1的时钟CM_PER RegistersCM_PER_GPIO1_CLKCTRL该寄存器管理GPIO1时钟。

OPTFCLKEN_GPIO_1_GDBCLK 可选功能时钟控制0X0 = FCLK_DIS ：可选功能的时钟被禁止0x1 = FCLK_EN ：可选功能时钟使能IDLEST 模块为空闲状态0X0 =函数功能：模块功能齐全，包括OCP0x1 =反：模块进行转换：唤醒或休眠，或睡眠流产0X2 =空闲：模块处于空闲模式（仅OCP部分）。

它是功能，如果使用独立的时钟功能0x3的=禁止：禁止模块，不能访问CM_PER_L4LS_CLKSTCTRL该寄存器使能域功率状态转换。

它控制着SW监督时钟域状态ON- PER和ON- INPER状态之间的转换。

它也认为每个时钟输入1个状态位域。

CLKACTIVITY_GPIO_1_GDBCLK 该字段表示在该GPIO1_GDBCLK时钟的状态域。

0X0 = INACT ：对应的时钟门控0x1 =ACT：通讯时钟有效2、配置GPIO端口功能CONTROL_MODULE Registersconf_gpmc_a0-a11 设置内部上拉和管脚传输速率：快或慢3、重启GPIO模块GPIO_SYSCONFIG 寄存器1 SOFTRESET R/W Software reset.This bit is automatically reset by the hardware. During reads, it always returns 0.0x0 = Normal mode0x1 = The module is rese软件复位。

该位由硬件自动复位。

在读取时，它总是返回0 。

0X0 =普通模式为0x1 =该模块复位4、设置GPIO方向GPIO_OE[0-31] 寄存器输出数据使能0X0 =相应的GPIO端口被配置为输出。

0x1 =相应的GPIO端口配置为输入。

电源管理芯片引脚界说之老阳三干创作
1、 VCC 电源管理芯片供电
2、 VDD 门驱动器供电电压输入或低级控制信号供电源
3、VID-4 CPU与CPU供电管理芯片VID信号连接引脚, 主要指示
芯片的输出信号, 使两个场管输出正确的工作电压.
4、RUN SD SHDN EN 分歧芯片的开始工作引脚.
5、PGOOD PG cpu内核供电电路正常工作信号输出.
6、VTTGOOD cpu外核供电正常信号输出.
7、UGATE 高端场管的控制信号.
8、LGATE 低端场管的控制信号.
9、PHASE 相电压引脚连接过压呵护端.
10、VSEN 电压检测引脚.
11、FB 电流反馈输入即检测电流输出的年夜小.
12、COMP 电流赔偿控制引脚.
13、DRIVE cpu外核场管驱动信号输出.
14、OCSET 12v供电电路过流呵护输入端.
15、BOOT 次级驱动信号器过流呵护输入端.
16、VIN cpu外核...
CC：C=circuit 暗示电路的意思, 即接入电路的电压；。

[A8] am335x_starterware—GPIO demo学习本例程实现功能比较简单，实现LED灯的闪烁。

1、主流程图1-1 GPIO程序主流程像常见LED闪烁程序一样，都是先配置，然后采取：置高-延时-拉低-延时-置高-延时……的方式，实现闪烁。

2、各子函数说明2.1 GPIO1ModuleClkConfig()配置GPIO1寄存器CM_PER_GPIO1_CLKCTRL（或上0x00000002），使能该GPIO1模块。

等待配置完毕。

P1049。

配置GPIO1寄存器CM_PER_GPIO1_CLKCTRL（或上0x00040000），使能GPIO1模块时钟。

等待配置完毕。

P1049。

检测GPIO1是否处于闲置状态CM_PER_GPIO1_CLKCTRL[17-16]，若处于非fully functional状态，则等待。

P1049。

检测L4的CM_PER_L4LS_CLKSTCTRL的[19]位，查看GPIO1_GDBCLK时钟是否激活。

若未激活（Inact）则等待。

P1020。

2.2 GPIO1Pin23PinMuxSetup()GPIO1Pin23PinMuxSetup()配置GPMC_A7（GPIO1_23）引脚，配置为高速、下拉并使能。

Register=0x00000007。

p1278。

功能服用配置位为该寄存器[2:0]，配置为111b，还未搞清楚。

2.3 GPIOModuleEnable()GPIOModuleEnable(GPIO_INSTANCE_ADDRESS)配置GPIO1时钟使能，GPIO_CTRL。

GPIO_CTRL[0]=0，使能GPIO1模块。

P4524。

2.4 GPIOModuleReset()GPIOModuleReset(GPIO_INSTANCE_ADDRESS)复位GPIO1各端口。

GPIO_SYSCONFIG。

GPIO_SYSCONFIG[1]=1，软件写1复位，复位GPIO1各端口。

How to use the AM335x IBIS ModelsIntroductionThe AM335x External Memory Interface is a very flexible interface which can be used with LPDDR, DDR2, DDR3, and DDR3L. There are many settings available to fine-tune the signal timing on this interface. These settings include ODT options, pullups, pulldowns, slew rate, etc. IBIS modeling can be used to fine tune the set of options for a given PCB. That said, understanding the mapping between the various IBIS models and the corresponding register configuration options is critical to doing this correctly. This article is intended to help bridge that gap so that AM335x users can properly model their memory interface and program the best options in the AM335x registers. NOTE: TI does not support timing analysis with IBIS simulations. Rather, customers are encouraged to use the IBIS models for Signal Integrity (SI) analysis. As far as the timing goes, please follow the routing guidelines and length/skew matching requirements in the Data Manual.IBIS StructureEvery pin on the device is listed with a corresponding "Selector". For example:P1 DDR_DQS0 Selector_1If you then go and look at the definition of that Selector you will find all of the available models for that given I/O cell. For example:[Model Selector] Selector_1Model_1000 INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,DIFF_VREF_FULLTERM_8MA_5PER_1P5 Model_1001 INPUT,1.5V,Half Thevenin, 1.60*RExt,IND,5%,DIFF_VREF_HALFTERM_5MA_5PER Model_1002 INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5Each of the models above corresponds to the I/O cell behavior given a specific set of configuration options. Register MappingParameters for a typical modelEach model has the following structure:ReadsModel_xyz INPUT, <voltage>, <ODT>, <Impedance>, <Temperature>, <Voltage-tolerance> WritesModel_xyz 3-STATE, <voltage>, <ODT>, <slew>, <Impedance>, <Temperature>, <Voltage-tolerance>Parameter Options Register Setting TRM Reference<voltage>DDR3L (1.35V), DDR3 (1.5V), orDDR2/LPDDR (1.8V)<ODT>Reads:NOTERM_WEAK_PU_ON,NOTERM_WEAK_PD_ON,NOTERM_WEAK_PUPD_OFF,FULLTERM, Half TheveninWrites: ODT Off DDR_PHY_CTRL_1[reg_phy_rd_local_odt]Table 7-254.DDR_PHY_CTRL_1Register FieldDescriptions<slew>fastest, fast, slow, slowest ddr_cmd0_ioctrl, ddr_cmd1_ioctrl,ddr_cmd2_ioctrl, ddr_data0_ioctrl,ddr_data1_ioctrl ["sr" fields]Table 9-7. DDR Slew Rate Control Settings<Impedance>0.67*RExt0.73*RExt0.8*RExt0.88*RExt1.00*RExt1.14*RExt1.33*RExt1.6*RExt ddr_cmd0_ioctrl, ddr_cmd1_ioctrl,ddr_cmd2_ioctrl, ddr_data0_ioctrl,ddr_data1_ioctrl ["I" fields]Table 9-8. DDRImpedance ControlSettings<Temperature>IND = -40 to 125C, 25C nominal(In IBIS Comments)<Voltage-tolerance>(Power supply tolerance, not a register)5% or 10%Additional considerations for LPDDR vs DDR2LPDDR and DDR2 are both 1.8V interfaces. However, they use different signaling technologies:•LPDDR -> LVCMOS•DDR2 -> SSTLLet’s look at the pin DDR_D4 as an example…N3 DDR_D4 Selector_11So here is the corresponding snippet from Selector_11:|*****************************************************************************************| Usage I/O#1.35/1.5V/1.8V#X#X#BCSHTLTCSCDVPBFZ_SSDHV.PAD| Base model BCSHTLTCSCDVPBFZ_SSDHV|***************************************************************************************** [Model Selector] Selector_11<snip>Model_440 INPUT,1.8V,Pull-up/down off,IND,5%,VREF_NOTERM_PUPD_OFF_5PER_1P8<snip>Model_452 INPUT,1.8V,Pull-up/down off,IND,5%,LVCMOS_PUPD_OFF_5PER_1P8Model_440 and Model_452 above are nearly identical, but that is because both LPDDR and DDR2 are 1.8V interfaces. The final field holds the difference between them. Model_440 is of type VREF_NOTERM which3corresponds to DDR2 with no termination enabled (i.e. SSTL). Model_452 is of type LVCMOS, which is used for LPDDR.The register mapping that corresponds to this selection in the actual hardware is ddr_io_ctrl[mddr_sel]:•mddr_sel=0 -> DDR2/3 (SSTL)•mddr_sel=1 -> LPDDR (LVCMOS)Additional Notes on ioctrl Pin MappingThe ioctrl registers map to the actual pins as follows:Register[bits]Signalsddr_cmd0_ioctrl[9:5]ddr_ck, ddr_cknddr_cmd0_ioctrl[4:0]ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]ddr_cmd1_ioctrl[4:0]ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasnddr_cmd2_ioctrl[4:0]ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1ddr_data0_ioctrl[9:5]ddr_dqs1, ddr_dqsn1ddr_data0_ioctrl[4:0]ddr_d[15:8], ddr_dqm1ddr_data1_ioctrl[9:5]ddr_dqs0, ddr_dqsn0ddr_data1_ioctrl[4:0]ddr_d[7:0], dqm0ExampleIn AM335x EMIF Configuration tips the recommendation is to set all the IOCTRL registers to a value of 0x18B which breaks down as:•SR[9:8] = 01 slow•I[7:5] = 100 0.88*RExt•SR[4:3] = 01 slow•I[2:0] = 011 1.00*RExtAs an example, let's assume you would like to model this type of configuration for your own hardware. And let's assume for this example that you're using DDR3 (1.5V). Finally, we'll do this modeling using 5% power supply tolerance, though it could similarly be modeled using 10% tolerance (i.e. just choose the corresponding model).The IOCTRL settings above correspond to the slew rate for ALL signals being set to "slow". The Impedance is being configured differently for some of the signals. The breakdown of signals controlled by these registers can be found in Table 9-9. DDR PHY to IO Pin Mapping. The register descriptions of the IOCTRL specifies which signals are affected by SR[9:8]/I[7:5]. So in particular, the following use 0.88*RExt:•DQS•DQSn•CK•CKnCorrespondingly the signals above should choose models with Impedance of 0.88*RExt. The others should use1.00*RExt. So in this scenario we would use the following:4Signal Model DescriptionDQS Model_6553-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADP_5PER_1P5DQS#Model_8473-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_PADN_5PER_1P5CK Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5CK#Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5DQ Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5DM Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5Note that the write models always have ODT off since in that scenario ODT would be a function of the memory onthe other side. For reads, ODT would be the responsibility of AM335x and so that parameter is configurable for reads:Signal Model DescriptionDQS Model_1002INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5DQS#Model_1002INPUT,1.5V,FULLTERM, 0.88*RExt,IND,5%,DIFF_VREF_FULLTERM_9MA_5PER_1P5CK Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5CK#Model_3433-STATE,1.5V,ODT off,slow, 0.88*RExt,IND,5%,SR01_9MA_5PER_1P5DQ Model_496INPUT,1.5V,FULLTERM, 1.00*RExt,IND,5%,VREF_FULLTERM_8MA_5PER_1P5DM Model_3523-STATE,1.5V,ODT off,slow, 1.00*RExt,IND,5%,SR01_8MA_5PER_1P5Note that the DDR_CK, DDR_CKN, and DDR_DQM pins are always driven by the AM335x (not the memory) which is why it is of type "3-STATE" (output) for both write and read operations above.Verifying DDR ConfigurationAfter investing the effort to determine the best models for your board, it will be up to the software team to actually make the necessary changes. This final and most critical step of the process is often done improperly! In order to simplify the process, a JTAG based script was created to read important registers on the device and parse the contents to show what's actually being used. Here's how to use download and use this script:1.Download am335x-ddr-analysis.dss [1].unch CCS.3.Create an appropriate target configuration file for connecting to your board.•File -> New -> Target Configuration File•Supply a name/location for the file.•View -> Target Configurations to see the available target configurations (yours should now be among them!).•Double-click your file in the Target Configurations panel to open it for editing.•Select your emulator and processor. Be sure to select a processor and not a board, as we don't want any gel files to be part of the configuration. Save.unch the debugger, but do not connect to any CPUs.•In the Target Configurations window, right-click on your ccxml file and select "Launch Selected Configuration"unch the scripting console by going to View -> Scripting Console.6.Load am335x-ddr-analysis.dss in the scripting console by executing "loadJSFile<path-to-dss-file>/am335x-ddr-analysis.dss".57.It will use the Debug Access Port (DAP) unobtrusively behind the scenes such that the Cortex A8 is never halted.It will generate a am335x-ddr-analysis_yyyy-mm-dd_hhmmss.txt file on your desktop.References[1]https:///sitara-dss-files/am335x-dss-files/blobs/raw/master/am335x-ddr-analysis.dss6 Article Sources and ContributorsHow to use the AM335x IBIS Models Source: /index.php?oldid=235642 Contributors: BradGriffis。

关于AM335系列的板卡和相关模块产品常见问题最近有客户在使用OK335x系列开发板中遇到了一些问题，所以在这里简单地总结了几点常见问题和解决方案，在这里分享一下。

如果您手中正好有飞凌的AM335x系列板卡，请仔细阅读，可能目前困扰您的问题答案就在这里！一．关于OK335x系列开发板，启动时，调试串口循环打印CCCCC问题分析以下为打印信息：建议从两方面进行问题排查：（1）OK335x系列开发板启动方式有2种：SD卡、nand. 请检查是否设置的SD卡启动，但是没有插SD卡或者SD卡中无程序。

底板上的拨码开关要拨到相应位置，参考以下说明：1. SD 卡启动设置：直接拨到 On2. NandFlash 启动设置：直接拨到 Off注：On 代表拨到上方，Off 代表拨到下方（2）飞凌OK335x系列开发板DI8-13的引脚，是boot启动项相关引脚。

如果您这几个引脚上接的外设模块电平跟uboot（下拉）启动电平相反，也可能会影响启动。

可以排查下是否是这几个引脚导致。

（3）如果排查以上两点还未解决问题，请联系飞凌技术支持************！二．关于OK335x系列开发板启动时，串口打印信息出现：please contact forlinx问题分析。

以下为打印信息：建议从两方面进行问题排查：（1）FET335x系列核心板上有个加密芯片：DS2406，通过IIC 接的CPU，这个芯片用户不能使用，因为出厂时里面已经写入了飞凌的加密信息，只有飞凌系统可以使用。

uboot在启动过程中会取读取保存在DS2460里的密码。

验证不通过的时候，会在串口打印信息里提示“Contact Forlinx….”，这种情况一般是加密芯片里的密码丢了，也可能是出厂没有烧写加密芯片。

（2）除了加密芯片用了一路IIC接口，核心板还支持2路，有些用户需要接自己的IIC外设模块。

如果您把设备挂载到加密芯片的这路IIC上，地址出现冲突，这样也可能会有影响，出现“please contact forlinx”信息。