EM48BM3244LBB-7FE中文资料
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Pb
Free
Extend temp. Free
* EOREX reserves the right to change products or specification without notice.
May. 2007 1/19
元器件交易网
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VDDQ VDDQ VSSQ VDD A1 A11 /RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
90ball BGA / (13mm x 8mm)ຫໍສະໝຸດ May. 2007 2/19
元器件交易网
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Pin J1 J8 Name CLK /CS
Rating -1 ~ +2.6 -1 ~ +2.6 Commercial Commercial Extended Extended -55 ~ +150 1
Units -1 ~ +2.6 -1 ~ +2.6 °C -55 ~ +150 1
IOS Short Circuit Current 50 50 Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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Features
Preliminary
EM488M3244LBB
256Mb (2M×4Bank×32) Synchronous DRAM
Description
The EM488M3244LBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages: BGA-90B (13mmx8mm)
Capacitance (VCC=3.3V, f=1MHz, TA=25°C)
Symbol CCLK CI CO Parameter Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance Min. 4 4 3 Typ. Max. 8 8 5 Units pF pF pF
Preliminary
EM488M3244LBB
3 A B C D E F G H J K L M N P R VDD
7 DQ23
8 DQ21 DQ19
9
VDDQ DQ22 DQ17 NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 VDDQ VDD
VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS /WE DQ7 DQ5 DQ3 VSSQ DQ0
Preliminary
EM488M3244LBB
Pin Description (Simplified)
Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers.
• Fully Synchronous to Positive Clock Edge • Single 1.8V ±0.1V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self Refresh) • Programmable Driver Strength Control – Full Strength or 1/2, 1/4 of Full Strength • 4,096 Refresh Cycles / 64ms (15.625us)
Pin Assignment
1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 2 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS
May. 2007
/WE DQM0~DQM3
DQ0~DQ31
(Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM.
VDD/VSS
(Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device.
