实验四数码管实验
一、实验目的：
1.进一步熟悉Modelsim和ISE仿真工具；
2.掌握7段数码管显示译码器；
3.掌握7段数码管数码管动态输出显示的方法。
二、实验内容:
1.实现按动开关键，在数码管上显示相应的十六进制数0~F。（参考给定的已有
工程文件Prep-IO）
2.实现开发板上的数码管动态显示0~F。
三、实验要求：
要求首先使用Modelsim软件进行功能仿真，然后使用ISE软件综合，并下载到开发板进行电路功能测试。
四、实验步骤:
1.采用VerilogHDL语言编程实现输入4位BCD码，输出是8位数码管显示码。
程序代码如下：
module Seg7BCD(out, in);
output [7:0] out;
input [3:0] in;
reg [7:0] out;
always@(in)
begin
case(in)
4'h0: out = 8'b00000011;
4'h1: out = 8'b10011111;
4'h2: out = 8'b00100101;
4'h3: out = 8'b00001101;
4'h4: out = 8'b10011001;
4'h5: out = 8'b01001001;
4'h6: out = 8'b01000001;
4'h7: out = 8'b00011111;
4'h8: out = 8'b00000001;
4'h9: out = 8'b00001001;
4'hA: out = 8'b00010001;
4'hB: out = 8'b11000001;
4'hC: out = 8'b01100011;
4'hD: out = 8'b10000101;
4'hE: out = 8'b01100001;
4'hF: out = 8'b01110001;
default: out = 8'hFE;
endcase
end
endmodule
2.用Modelsim进行功能仿真。
测试代码：
module Seg7BCD_tb;
reg [3:0] in;
wire [7:0] out;
Seg7BCD bcd(.in(in),.out(out));
initial
begin
in = 4'h0;
#20 in = 4'h1;
#20 in = 4'h2;
#20 in = 4'h3;
#20 in = 4'h4;
#20 in = 4'h5;
#20 in = 4'h6;
#20 in = 4'h7;
#20 in = 4'h8;
#20 in = 4'h9;
#20 in = 4'hA;
#20 in = 4'hB;
#20 in = 4'hC;
#20 in = 4'hD;
#20 in = 4'hE;
#20 in = 4'hF;
end
endmodule
仿真结果：
3.分别设计4位BCD码自动生成模块和BCD码的译码模块。4位BCD码生成模块：
module BCDCode( input clk,
input rst,
output reg [3:0] BCDCode
);
always @ (posedge clk)
if (rst) BCDCode = 0;
else BCDCode = BCDCode + 1; endmodule
BCD码的译码模块：
module Seg7BCD(out, in);
output [7:0] out;
input [3:0] in;
reg [7:0] out;
always@(in)
begin
case(in)
4'h0: out = 8'b00000011;
4'h1: out = 8'b10011111;
4'h2: out = 8'b00100101;
4'h3: out = 8'b00001101;
4'h4: out = 8'b10011001;
4'h5: out = 8'b01001001;
4'h6: out = 8'b01000001;
4'h7: out = 8'b00011111;
4'h8: out = 8'b00000001;
4'h9: out = 8'b00001001;
4'hA: out = 8'b00010001;
4'hB: out = 8'b11000001;
4'hC: out = 8'b01100011;
4'hD: out = 8'b10000101;
4'hE: out = 8'b01100001;
4'hF: out = 8'b01110001;
default: out = 8'hFE;
endcase
end
endmodule
4.在顶层文件将2个电路模块实例化，并进行相应的连线。
5.用ISE综合并将电路下载到开发板进行电路功能测试。
