module count60(qout,cout,data,load,reset,clk);
input load,clk,reset;input[7:0] data;
output reg[7:0] qout; output cout;
always @(posedge clk)
begin
if(reset) qout<=0;
count60 mycount(qout,cout,data,load,reset,clk);
always #(DELY/2) clk=~clk;
initial
begin clk=0;reset=0 ;load=0 ;data=58;
#DELY reset=1;
#DELY reset=0;
#DELY load=1;
end
end
assign cout=(qout==8'd59)?1:0;
endmodule
`include "count60.v"
module count;
reg clk,reset,load;
reg[7:0] data;
wire [7:0]qout;
wire cout;
parameter DELY=100;
verilog实现60计数器 modulecount60(qout,cout,data,load,reset,clk); input load,clk,reset;input[7:0] data; output reg[7:0] qout; output cout; always @(posedge clk) begin if(reset) qout<=0; else if(load) qout<=data; else begin if(qout[3:0]==9) begin qout[3:0]<=0; if(qout[7:4]==5) qout[7:4]<=0; else qout[7:4]<=qout[7:4]+1; end else qout[3:0]<=qout[3:0]+1; end end assign cout=(qout==8?d59)?1:0; endmodule `include "count60.v" module count; reg clk,reset,load; reg[7:0] data; wire [7:0]qout; wire cout; parameter dely=100; count60 mycount(qout,cout,data,load,reset,clk); always #(dely/2) clk=~clk; initial begin clk=0;reset=0 ;load=0 ;data=58; #dely reset=1; #dely reset=0; #dely load=1; #dely load=0; #(dely*60) $finish; end initial $monitor($time,,,"clk=%d reset=%d load=%d qout=%d cout=%d clk,reset,load,cout,qout);endmodule `timescale 1ns/1ns `include "vote.v" module vote; reg wirepass; parameter dely=100; vote vt(a,b,c,pass); initial begin #dely$finish; end initial $monitor($time,,,"a=%b pass=%b",a,b,c,pass);endmodule crx110
