CAT28C64BLI12;CAT28C64BWI-12T;CAT28C64BG12;CAT28C64BG-12T;CAT28C64BGI12;中文规格书,Datasheet资料

Atmel芯片新命名型号对照表ATTINY28L ATMEL ATMLU701 DIP ATTINY26L ATMEL ATMLU702 DIP ATTINY26 ATMEL ATMLU703 DIP ATTINY24 ATMEL ATMLU704 DIP ATTINY2313V ATMEL ATMLU705 DIP ATTINY2313 ATMEL ATMLU706 DIP ATTINY15L ATMEL ATMLU707 DIP ATTINY13V ATMEL ATMLU708 DIP ATTINY13 ATMEL ATMLU709 DIP ATTINY11L ATMEL ATMLU710 DIP ATMEGA8L ATMEL ATMLU711 DIP ATMEGA88V ATMEL ATMLU712 DIP ATMEGA88 ATMEL ATMLU713 DIP ATMEGA8535L ATMEL ATMLU714 DIP ATMEGA8535 ATMEL ATMLU715 DIP ATMEGA8515L ATMEL ATMLU716 DIP ATMEGA8515 ATMEL ATMLU717 DIP ATMEGA8 ATMEL ATMLU718 DIP ATMEGA64L ATMEL ATMLU719 DIP ATMEGA64 ATMEL ATMLU720 DIP ATMEGA640V ATMEL ATMLU721 DIP ATMEGA48V ATMEL ATMLU722 DIP ATMEGA48 ATMEL ATMLU723 DIP ATMEGA32L ATMEL ATMLU724 DIP ATMEGA325V ATMEL ATMLU725 DIP ATMEGA32 ATMEL ATMLU726 DIP ATMEGA16L ATMEL ATMLU727 DIP ATMEGA169V ATMEL ATMLU728 DIP ATMEGA169PV ATMEL ATMLU729 DIP ATMEGA169P ATMEL ATMLU730 DIP ATMEGA168V ATMEL ATMLU731 DIP ATMEGA168 ATMEL ATMLU732 DIP ATMEGA162V ATMEL ATMLU733 DIP ATMEGA162 ATMEL ATMLU734 DIP ATMEGA16 ATMEL ATMLU735 DIP ATMEGA128L ATMEL ATMLU736 DIP ATMEGA128 ATMEL ATMLU737 DIP ATMEGA1280V ATMEL ATMLU738 DIP ATJTAGICE2 ATMEL ATMLU739 DIPATF20V8B ATMEL ATMLU740 DIPATF16V8BQL ATMEL ATMLU741 DIP ATF16V8B ATMEL ATMLU742 DIPATF1508AS ATMEL ATMLU743 DIP ATF1502AS ATMEL ATMLU744 DIP ATAVRISP2 ATMEL ATMLU745 DIP ATAVRDRAGON ATMEL ATMLU746 DIP AT93C66A ATMEL ATMLU747 DIPAT93C56A ATMEL ATMLU748 DIPAT93C46DN ATMEL ATMLU749 DIPAT93C46DH ATMEL ATMLU750 DIPAT93C46 ATMEL ATMLU751 DIPAT91SAM ATMEL ATMLU752 DIPAT91SAM9263 ATMEL ATMLU801 DIP AT91SAM9261S ATMEL ATMLU802 DIP AT91SAM9261 ATMEL ATMLU803 DIP AT91SAM9260 ATMEL ATMLU804 DIP AT91SAM7X ATMEL ATMLU805 DIPAT91SAM7X256 ATMEL ATMLU806 DIP AT91SAM7SE32 ATMEL ATMLU807 DIP AT91SAM7S64 ATMEL ATMLU808 DIP AT91SAM7S32 ATMEL ATMLU809 DIP AT91SAM7S321 ATMEL ATMLU810 DIP AT91SAM7S256 ATMEL ATMLU811 DIP AT91RM9200 ATMEL ATMLU812 DIP AT91M55800A ATMEL ATMLU813 DIP AT91M40800 ATMEL ATMLU814 DIPAT90CAN32 ATMEL ATMLU815 DIPAT90CAN128 ATMEL ATMLU816 DIP AT89S8253 ATMEL ATMLU817 DIPAT89S58 ATMEL ATMLU818 DIPAT89S54 ATMEL ATMLU819 DIPAT89S52 ATMEL ATMLU820 DIPAT89S51 ATMEL ATMLU821 DIPAT89LV51 ATMEL ATMLU822 DIPAT89LS52 ATMEL ATMLU823 DIPAT89C55WD ATMEL ATMLU824 DIPAT89C52 ATMEL ATMLU825 DIPAT89C51RD2 ATMEL ATMLU826 DIP AT89C51RC2 ATMEL ATMLU827 DIP AT89C51RC ATMEL ATMLU828 DIPAT89C51RC2 ATMEL ATMLU829 DIPAT89C51ED2 ATMEL ATMLU831 DIPAT89C51CC01UA ATMEL ATMLU832 DIP AT89C51CC01CA ATMEL ATMLU833 DIP AT89C51AU2 ATMEL ATMLU834 DIPAT89C5131A ATMEL ATMLU835 DIPAT89C51 ATMEL ATMLU836 DIPAT89C4051 ATMEL ATMLU837 DIPAT89C2051 ATMEL ATMLU838 DIPAT88SC153 ATMEL ATMLU839 DIPAT88SC0104C ATMEL ATMLU840 DIP AT49BV512 ATMEL ATMLU841 DIPAT49BV322DT ATMEL ATMLU842 DIP AT49BV040B ATMEL ATMLU843 DIPAT47BV163A ATMEL ATMLU844 DIPAT45DB642DU ATMEL ATMLU845 DIP AT45DB321DU ATMEL ATMLU846 DIP AT45DB321D ATMEL ATMLU847 DIPAT45DB161DU ATMEL ATMLU848 DIP AT45DB161D ATMEL ATMLU849 DIPAT45DB081D ATMEL ATMLU850 DIPAT45DB041D ATMEL ATMLU851 DIPAT45DB021B ATMEL ATMLU852 DIPAT29LV512 ATMEL ATMLU901 DIPAT29LV040A ATMEL ATMLU902 DIPAT29LV020 ATMEL ATMLU903 DIPAT29C040A ATMEL ATMLU904 DIPAT29C020 ATMEL ATMLU905 DIPAT29C010A ATMEL ATMLU906 DIPAT28C64B ATMEL ATMLU907 DIPAT28C256 ATMEL ATMLU908 DIPAT28BV256 ATMEL ATMLU909 DIPAT27C512R ATMEL ATMLU910 DIPAT27C256R ATMEL ATMLH701 SOPAT27C040 ATMEL ATMLH702 SOPAT27C010 ATMEL ATMLH703 SOPAT27BV256 ATMEL ATMLH704 SOPAT26DF321 ATMEL ATMLH705 SOPAT26DF161 ATMEL ATMLH706 SOPAT26DF081A ATMEL ATMLH707 SOPAT25F512AN ATMEL ATMLH708 SOPAT25F1024AN ATMEL ATMLH709 SOPAT25256AN ATMEL ATMLH711 SOP AT25128A ATMEL ATMLH712 SOPAT24C64CN ATMEL ATMLH713 SOP AT24C64AN ATMEL ATMLH714 SOP AT24C64A ATMEL ATMLH715 SOP AT24C512N ATMEL ATMLH716 SOP AT24C512B ATMEL ATMLH717 SOP AT24C512BN ATMEL ATMLH718 SOP AT24C512 ATMEL ATMLH719 SOPAT24C32CN ATMEL ATMLH720 SOP AT24C32AN ATMEL ATMLH721 SOP AT24C32A ATMEL ATMLH722 SOP AT24C256N ATMEL ATMLH723 SOP AT24C256B ATMEL ATMLH724 SOP AT24C256BN ATMEL ATMLH725 SOP AT24C256B ATMEL ATMLH726 SOP AT24C16BN ATMEL ATMLH727 SOP AT24C16AN ATMEL ATMLH728 SOP AT24C16A ATMEL ATMLH729 SOP AT24C128N ATMEL ATMLH730 SOP AT24C128 ATMEL ATMLH731 SOPAT24C08AN ATMEL ATMLH732 SOP AT24C08A ATMEL ATMLH733 SOP AT24C04N ATMEL ATMLH734 SOP AT24C04BN ATMEL ATMLH735 SOP AT24C04 ATMEL ATMLH736 SOPAT24C02B ATMEL ATMLH737 SOP AT24C02BN ATMEL ATMLH738 SOP AT24C02B ATMEL ATMLH739 SOP AT24C01B ATMEL ATMLH740 SOP AT24C01BN ATMEL ATMLH741 SOP ATTINY28L ATMEL ATMLU701 SOP ATTINY26L ATMEL ATMLU702 SOP ATTINY26 ATMEL ATMLU703 SOP ATTINY24 ATMEL ATMLU704 SOP ATTINY2313V ATMEL ATMLU705 SOP ATTINY2313 ATMEL ATMLU706 SOP ATTINY15L ATMEL ATMLU707 SOP ATTINY13V ATMEL ATMLU708 SOP ATTINY13 ATMEL ATMLU709 SOP ATTINY11L ATMEL ATMLU710 SOPATMEGA88V ATMEL ATMLU712 SOP ATMEGA88 ATMEL ATMLU713 SOP ATMEGA8535L ATMEL ATMLU714 SOP ATMEGA8535 ATMEL ATMLU715 SOP ATMEGA8515L ATMEL ATMLU716 SOP ATMEGA8515 ATMEL ATMLU717 SOP ATMEGA8 ATMEL ATMLU718 SOP ATMEGA64L ATMEL ATMLU719 SOP ATMEGA64 ATMEL ATMLU720 SOP ATMEGA640V ATMEL ATMLU721 SOP ATMEGA48V ATMEL ATMLU722 SOP ATMEGA48 ATMEL ATMLU723 SOP ATMEGA32L ATMEL ATMLU724 SOP ATMEGA325V ATMEL ATMLU725 SOP ATMEGA32 ATMEL ATMLU726 SOP ATMEGA16L ATMEL ATMLU727 SOP ATMEGA169V ATMEL ATMLU728 SOP ATMEGA169PV ATMEL ATMLU729 SOP ATMEGA169P ATMEL ATMLU730 SOP ATMEGA168V ATMEL ATMLU731 SOP ATMEGA168 ATMEL ATMLU732 SOP ATMEGA162V ATMEL ATMLU733 SOP ATMEGA162 ATMEL ATMLU734 SOP ATMEGA16 ATMEL ATMLU735 SOP ATMEGA128L ATMEL ATMLU736 SOP ATMEGA128 ATMEL ATMLU737 SOP ATMEGA1280V ATMEL ATMLU738 SOP ATJTAGICE2 ATMEL ATMLU739 SOP ATF20V8B ATMEL ATMLU740 SOPATF16V8BQL ATMEL ATMLU741 SOP ATF16V8B ATMEL ATMLU742 SOPATF1508AS ATMEL ATMLU743 SOP ATF1502AS ATMEL ATMLU744 SOP ATAVRISP2 ATMEL ATMLU745 SOP ATAVRDRAGON ATMEL ATMLU746 SOP AT93C66A ATMEL ATMLU747 SOPAT93C56A ATMEL ATMLU748 SOPAT93C46DN ATMEL ATMLU749 SOPAT93C46DH ATMEL ATMLU750 SOPAT93C46 ATMEL ATMLU751 SOPAT91SAM ATMEL ATMLU752 SOPAT91SAM9261S ATMEL ATMLU802 SOP AT91SAM9261 ATMEL ATMLU803 SOP AT91SAM9260 ATMEL ATMLU804 SOP AT91SAM7X ATMEL ATMLU805 SOPAT91SAM7X256 ATMEL ATMLU806 SOP AT91SAM7SE32 ATMEL ATMLU807 SOP AT91SAM7S64 ATMEL ATMLU808 SOP AT91SAM7S32 ATMEL ATMLU809 SOP AT91SAM7S321 ATMEL ATMLU810 SOP AT91SAM7S256 ATMEL ATMLU811 SOP AT91RM9200 ATMEL ATMLU812 SOPAT91M55800A ATMEL ATMLU813 SOP AT91M40800 ATMEL ATMLU814 SOPAT90CAN32 ATMEL ATMLU815 SOPAT90CAN128 ATMEL ATMLU816 SOPAT89S8253 ATMEL ATMLU817 SOPAT89S58 ATMEL ATMLU818 SOPAT89S54 ATMEL ATMLU819 SOPAT89S52 ATMEL ATMLU820 SOPAT89S51 ATMEL ATMLU821 SOPAT89LV51 ATMEL ATMLU822 SOPAT89LS52 ATMEL ATMLU823 SOPAT89C55WD ATMEL ATMLU824 SOPAT89C52 ATMEL ATMLU825 SOPAT89C51RD2 ATMEL ATMLU826 SOPAT89C51RC2 ATMEL ATMLU827 SOPAT89C51RC ATMEL ATMLU828 SOPAT89C51RC2 ATMEL ATMLU829 SOPAT89C51RB2 ATMEL ATMLU830 SOPAT89C51ED2 ATMEL ATMLU831 SOPAT89C51CC01UA ATMEL ATMLU832 SOP AT89C51CC01CA ATMEL ATMLU833 SOP AT89C51AU2 ATMEL ATMLU834 SOPAT89C5131A ATMEL ATMLU835 SOPAT89C51 ATMEL ATMLU836 SOPAT89C4051 ATMEL ATMLU837 SOPAT89C2051 ATMEL ATMLU838 SOPAT88SC153 ATMEL ATMLU839 SOPAT88SC0104C ATMEL ATMLU840 SOP AT49BV512 ATMEL ATMLU841 SOPAT49BV322DT ATMEL ATMLU842 SOPAT47BV163A ATMEL ATMLU844 SOP AT45DB642DU ATMEL ATMLU845 SOP AT45DB321DU ATMEL ATMLU846 SOP AT45DB321D ATMEL ATMLU847 SOP AT45DB161DU ATMEL ATMLU848 SOP AT45DB161D ATMEL ATMLU849 SOP AT45DB081D ATMEL ATMLU850 SOP AT45DB041D ATMEL ATMLU851 SOP AT45DB021B ATMEL ATMLU852 SOP AT29LV512 ATMEL ATMLU901 SOP AT29LV040A ATMEL ATMLU902 SOP AT29LV020 ATMEL ATMLU903 SOP AT29C040A ATMEL ATMLU904 SOP AT29C020 ATMEL ATMLU905 SOPAT29C010A ATMEL ATMLU906 SOP AT28C64B ATMEL ATMLU907 SOPAT28C256 ATMEL ATMLU908 SOPAT28BV256 ATMEL ATMLU909 SOP AT27C512R ATMEL ATMLU910 SOP AT27C256R ATMEL ATMLH701 DIPAT27C040 ATMEL ATMLH702 DIPAT27C010 ATMEL ATMLH703 DIPAT27BV256 ATMEL ATMLH704 DIPAT26DF321 ATMEL ATMLH705 DIPAT26DF161 ATMEL ATMLH706 DIPAT26DF081A ATMEL ATMLH707 DIP AT25F512AN ATMEL ATMLH708 DIP AT25F1024AN ATMEL ATMLH709 DIP AT25DF041A ATMEL ATMLH710 DIP AT25256AN ATMEL ATMLH711 DIPAT25128A ATMEL ATMLH712 DIPAT24C64CN ATMEL ATMLH713 DIPAT24C64AN ATMEL ATMLH714 DIPAT24C64A ATMEL ATMLH715 DIPAT24C512N ATMEL ATMLH716 DIPAT24C512B ATMEL ATMLH717 DIPAT24C512BN ATMEL ATMLH718 DIP AT24C512 ATMEL ATMLH719 DIPAT24C32CN ATMEL ATMLH720 DIPAT24C32AN ATMEL ATMLH721 DIPAT24C32A ATMEL ATMLH722 DIPAT24C256B ATMEL ATMLH724 DIP AT24C256BN ATMEL ATMLH725 DIP AT24C256B ATMEL ATMLH726 DIP AT24C16BN ATMEL ATMLH727 DIP AT24C16AN ATMEL ATMLH728 DIP AT24C16A ATMEL ATMLH729 DIP AT24C128N ATMEL ATMLH730 DIP AT24C128 ATMEL ATMLH731 DIP AT24C08AN ATMEL ATMLH732 DIP AT24C08A ATMEL ATMLH733 DIP AT24C04N ATMEL ATMLH734 DIP AT24C04BN ATMEL ATMLH735 DIP AT24C04 ATMEL ATMLH736 DIPAT24C02B ATMEL ATMLH737 DIP AT24C02BN ATMEL ATMLH738 DIP AT24C02B ATMEL ATMLH739 DIP AT24C01B ATMEL ATMLH740 DIP AT24C01BN ATMEL ATMLH741 DIP 不全，不过我可是第一个回答的啊。

Features•Fast Read Access Time - 120 ns•Fast Byte Write - 200 µs or 1 ms•Self-Timed Byte Write CycleInternal Address and Data LatchesInternal Control TimerAutomatic Clear Before Write•Direct Microprocessor ControlREADY/BUSY Open Drain OutputDATA Polling•Low Power30 mA Active Current100 µA CMOS Standby Current•High ReliabilityEndurance: 104 or 105 CyclesData Retention: 10 Years•5V ± 10% Supply•CMOS and TTL Compatible Inputs and Outputs •JEDEC Approved Byte-Wide Pinout•Commercial and Industr ial Temperature RangesDescriptionThe AT28C64 is a low-power, high-performance 8,192 words by 8 bit nonvolatile Electrically Erasable and Programmable Read Only Memory with popular, easy to use features. The device is manufactured with Atmel’s reliable no nvolatile technol-ogy.(continuedPDIP, SOICTop ViewPin ConfigurationsTSOPTop ViewLCC, PLCCTop ViewNote: PLCC package pins 1 and 17 are DON’T CONNECT.AT28C64/X2-193Description(ContinuedBlock DiagramThe AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components.During a byte write, the address and data are latched in-ternally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cy-cle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin1 is N.C. and DATA POLLING of I/O 7. Once the end of a write cycle has been detected,a new access for a read or write can begin.The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 µA.Atmel’s 28C64 has additional features to ensure high quality and manufacturability. The device utilizes error cor-rection internally for extended endurance and for im-proved data retention characteristics. An extra 32-bytes of E 2PROM are available for device identification or tracking.*NOTICE: Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi-cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Absolute Maximum Ratings*2-194AT28C64/XDevice OperationREAD: The AT28C64 is accessed like a Static RAM.When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high im-pedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention.BYTE WRITE: Writing data into the AT28C64 is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively initi-ates a byte write. The address location is latched on the falling edge of WE (or CE; the new data is latched on the rising edge. Internally, the device performs a self-clear be-fore write. Once a byte write has been started, it will auto-matically time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation.FAST BYTE WRITE: The AT28C64E offers a byte write time of 200 µs maximum. This feature allows the entire device to be rewritten in 1.6 seconds.READY/BUSY: Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle.RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY line. Pin 1 is not connected for theAT28C64X.DATA POLLING: The AT28C64 provides DATA POLL-ING to signal the completion of a write cycle. During a write cycle, an attempted read of the data beingwritten results in the complement of that data for I/O 7 (the other outputs are indeterminate. When the write cycle is fin-ished, true data appears on all outputs.WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways. (a V CC sense— if V CC is below 3.8V (typical the write function is inhibited. (b V CC power on delay— once V CC h a s reached 3.8V the device will automatically time out 5 ms (typical before allowing a byte write. (c Write Inhibit—holding any one of OE low, CE high or WE high inhibits byte write cycles.CHIP CLEAR: The contents of the entire memory of the AT28C64 may be set to the high state by the CHIP CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low pulse is applied to WE.DEVICE IDENTIFICATION: A n e x t r a 32-by t es of E 2PROM memory are available to the user for device identification. By raising A9 to 12 ± 0.5V and using ad-dress locations 1FE0H to 1FFFH the additional bytes may be written to or read from in the same manner as the regu-lar memory array.AT28C64/X2-195DC CharacteristicsDC and AC Operating Range3. V H = 12.0V ± 0.5V.Notes: 1.X can be V IL or V IH .2.Refer to AC Programming Waveforms. Operating Modes2-196AT28C64/XAC Read CharacteristicsNotes: 1.CE may be delayed up to t ACC - t CE after the addresstransition without impact on t ACC .2.OE may be delayed up to t CE - t OEafter the falling edge of CE without impact on t CE or by t ACC - t OE after an address change without impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (C L = 5 pF.4.This parameter is characterized and is not 100% tested.AC Read Waveforms(1, 2, 3, 4t R , t F < 20 nsInput Test Waveforms andMeasurement LevelOutput Test LoadPin Capacitance (f = 1 MHz, T = 25°C (1Note: 1. This parameter is characterized and is not 100% tested. AT28C64/X2-197AC Write CharacteristicsAC Write WaveformsWEControlledCE Controlled2-198AT28C64/X(1Notes: 1.These parameters are characterized and not 100% tested.2.See AC Read Characteristics.Chip Erase Waveformst S = t H = 1 µsec (min.t W = 10 msec (min.V H = 12.0V ± 0.5V AT28C64/X2-1992-200AT28C64/XOrdering Information (1Note: 1.See Valid Part Number table below. AT28C64/X2-2012-202AT28C64/XAT28C64/X Ordering Information tACC (ns 150 ICC (mA Active 30 Standby 0.1 AT28C64X-15JC AT28C64X-15PC AT28C64X-15SC AT28C64X-15TC AT28C64X-15JI AT28C64X-15PI AT28C64X-15SI AT28C64X-15TI AT28C64X-20JCAT28C64X-20PC AT28C64X-20SC AT28C64X-20TC AT28C64X-20JI AT28C64X-20PI AT28C64X-20SI AT28C64X-20TI AT28C64X-25JC AT28C64X-25PCAT28C64X-25SC AT28C64X-25TC AT28C64X-25JI AT28C64X-25PI AT28C64X-25SI AT28C64X-25TI Ordering Code Package 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Operation Range Commercial (0°C to 70°C 45 0.1 Industrial (-40°C to 85°C 200 30 0.1 Commercial (0°C to 70°C 45 0.1 Industrial (-40°C to 85°C 250 30 0.1 Commercial (0°C to 70°C 45 0.1 Industrial (-40°C to 85°C Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers AT28C64 X AT28C64 X AT28C64 X AT28C64 X Speed 12 15 20 25 Package and Temperature Combinations JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI JC, JI, PC, PI, SC, SI, TC, TI Package Type 32J 28P6 28S 28T 32 Lead, Plastic J-Leaded Chip Carrier (PLCC 28 Lead, 0.600" Wide Plastic Dual Inline Package (PDIP 28 Lead, 0.300" Wide,Plastic Gull Wing Small Outline (SOIC 28 Lead, Plastic Thin Small Outline Package (TSOP 2-203。

音乐喷泉控制器的设计(硬件设计>摘要：音乐喷泉控制器是音乐喷泉的核心部分。

在音乐喷泉中，喷头的多姿造型和缤纷的水下灯光都受喷泉控制器的控制。

由于不同的喷泉对水泵和彩灯组数的要求各不相同，因此可以设计一种简单、通用、组数可灵活扩充的喷泉控制器。

本喷泉控制器采用全数字集成电路设计，可以灵活改变水泵和彩灯的组数。

本设计分为音控、程控两用的音乐喷泉控制器。

控制三组不同颜色的彩灯，五台不同喷泉造型的水泵。

音控、程控可用开关手动切换。

程控的速度可用电位器调节。

音控时，输入音乐的音量直接控制彩灯，音乐音量小则彩灯打开的组数少，音量大则彩灯打开的组数多，在音乐音量较长时间不变时，彩灯打开的组数不变，但各组应能循环打开，以避免灯光和造型的单调。

设计中主要用到的方法，音乐经过峰值检波后，得到和音量大小相关的控制电压，将此控制电压，经过简单的A/D转换变成数字信号后，去控制存储器芯片的高位地址，同时程控地址发生器也发出控制存储器芯片的地址信号，这两组地址信号经地址切换开关选择后去控制存储器的地址，该存储器地址对应的数据信号就会输出，输出信号经隔离驱动后就去推动彩灯工作。

关键字：峰值检波、A/D转换、EEPROM<AT28C64B）、程控地址发生器<CD4060）Abstract：The musical fountain controller is the musical fountain heart. In the musical fountain, the nozzle varied modeling and the riotous submarine light all receive the eruptive fountain controller the control. Is various as a result of the different eruptive fountain to the water pump and the color lamp bank number request, therefore designs the eruptive fountain controller which one kind simple, general, the group number may expand nimbly to become an eruptive fountain designer's topic. This eruptive fountain controller uses the entire digital circuit design, may change the water pump and the colored lantern group number nimbly.This design divides into the sound to control, the program control dual purpose musical fountain controller. Controls three groups of different colors the colored lanterns, five different eruptive fountain modeling water pump. The sound controls, the program control available switch silk thread business manual cut. Program control peed available potentiometer adjustment. then the volume the colored lantern opens greatly the group number are many, when music volume long time invariable, the colored lantern opens the group number is invariable, but each group ought to be able to circulate opens, avoids the light and modeling monotonous.In the design mainly uses the method, music after the peak detection, obtains with the volume size correlation control voltage, this control voltage, after passes through the simple A/D transformation to turn the digital signal, the control memory chip top digit address, simultaneously the program control address generator also sends out the control memory chip the address signal, these two group of address signal after the address cut switch choice the control memory address, this memory address correspondence data signal can output, the output signal on impels the colored lantern work after the isolation actuation.Keyword： peak detection A/D transformation引言音乐喷泉是近几年来出现的喷泉水景与音乐欣赏相结合的产物，它的出现改变了喷泉艺术单调不变的局面。

Features•Fast Read Access Time – 150 ns•Automatic Page Write Operation–Internal Address and Data Latches for 64 Bytes•Fast Write Cycle Times–Page Write Cycle Time: 10 ms Maximum (Standard)2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)–1 to 64-byte Page Write Operation•Low Power Dissipation–40 mA Active Current–100µA CMOS Standby Current•Hardware and Software Data Protection•DATA Polling and Toggle Bit for End of Write Detection•High Reliability CMOS Technology–Endurance: 100,000 Cycles–Data Retention: 10 Years•Single 5V ±10% Supply•CMOS and TTL Compatible Inputs and Outputs•JEDEC Approved Byte-wide Pinout•Industrial Temperature Ranges•Green (Pb/Halide-free) Packaging Option Only1.DescriptionThe AT28C64B is a high-performance electrically-erasable and programmable read-only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100µA.The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.Atmel’s AT28C64B has additional features to ensure high quality and manufacturabil-ity. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64bytes of EEPROM for device identification or tracking.BDTIC /ATMEL20270L–PEEPR–2/09AT28C64B2.Pin Configurations2.128-lead PDIP , 28-lead SOIC Top ViewPin Name Function A0 - A12Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7Data Inputs/Outputs NC No Connect DCDon’t Connect2.232-lead PLCC Top ViewNote:PLCC package pins 1 and 17 are Don’t Connect.2.328-lead TSOP Top View30270L–PEEPR–2/09AT28C64B3.Block Diagram4.Device Operation4.1ReadThe AT28C64B is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs.The outputs are put in the high-impedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus contention in their systems.4.2Byte WriteA low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-cally time itself to completion. Once a programming operation has been initiated and for the duration of t WC , a read operation will effectively be a polling operation.4.3Page WriteThe page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63additional bytes. Each successive byte must be loaded within 150 µs (t BLC ) of the previous byte.If the t BLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same.The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are spec-ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.40270L–PEEPR–2/09AT28C64B4.4DATA PollingThe AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle.4.5Toggle BitIn addition to DAT A Polling, the AT28C64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-gling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.4.6Data ProtectionIf precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel ® has incorporated both hardware and software features that will protect the memory against inadvertent writes.4.6.1Hardware Data ProtectionHardware features protect against inadvertent writes to the AT28C64B in the following ways: (a)V CC sense – if V CC is below 3.8 V (typical), the write function is inhibited; (b) V CC power-on delay – once V CC has reached 3.8V, the device will automatically time out 5 ms (typical) before allow-ing a write; (c) write inhibit – holding any one of OE low, CE high, or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not ini-tiate a write cycle.4.6.2Software Data ProtectionA software controlled data protection feature has been implemented on the AT28C64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP dis-abled.SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (see “Software Data Protection Algorithms”on page 10). After writing the 3-byte command sequence and waiting t WC , the entire AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled,the user may still perform a byte or page write to the AT28C64B by preceding the data to be writ-ten by the same 3-byte command sequence used to enable SDP.Once set, SDP remains active unless the disable command sequence is issued. Power transi-tions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation.After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device. However, for the duration of t WC , read operations will effectively be polling operations.4.7Device IdentificationAn extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-ing A9 to 12V ±0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.50270L–PEEPR–2/09AT28C64BNotes: 1.X can be V IL or V IH .2.See “AC Write Waveforms” on page 8.3.V H = 12.0V ±0.5V .5.DC and AC Operating RangeAT28C64B-15Operating T emperature (Case)-40°C - 85°C V CC Power Supply5V ±10%6.Operating ModesMode CE OE WE I/O Read V IL V IL V IH D OUT Write (2)V IL V IH V IL D IN Standby/Write Inhibit V IH X (1)X High ZWrite Inhibit X X V IH Write Inhibit X V IL X Output DisableX V IH XHigh Z Chip EraseV ILV H (3)V IL High Z7.Absolute Maximum Ratings*T emperature Under Bias................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityStorage T emperature.....................................-65°C to +150°C All Input Voltages(including NC Pins)with Respect to Ground...................................-0.6V to +6.25V All Output Voltageswith Respect to Ground.............................-0.6V to V CC + 0.6V Voltage on OE and A9with Respect to Ground...................................-0.6V to +13.5V8.DC CharacteristicsSymbol Parameter ConditionMinMax Units I LI Input Load Current V IN = 0V to V CC + 1V 10µA I LO Output Leakage Current V I/O = 0V to V CC10µA I SB1V CC Standby Current CMOS CE = V CC - 0.3V to V CC + 1V 100µA I SB2V CC Standby Current TTL CE = 2.0V to V CC + 1V 2mA I CC V CC Active Current f = 5 MHz; I OUT = 0 mA40mA V IL Input Low Voltage 0.8V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 2.1 mA 0.40V V OHOutput High VoltageI OH = -400 µA2.4V60270L–PEEPR–2/09AT28C64B10.AC Read Waveforms (1)(2)(3)(4)Notes:1.CE may be delayed up to t ACC - t CE after the address transition without impact on t ACC .2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE or by t ACC - t OE after an address changewithout impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (C L = 5 pF).4.This parameter is characterized and is not 100% tested.9.AC Read CharacteristicsSymbol ParameterAT28C64B-15Units MinMax t ACC Address to Output Delay 150ns t CE (1)CE to Output Delay 150ns t OE (2)OE to Output Delay 070ns t DF (3)(4)CE or OE to Output Float050ns t OHOutput Hold from OE, CE or Address, whichever occurred firstns70270L–PEEPR–2/09AT28C64B11.Input Test Waveforms and Measurement Level12.Output Test LoadNote:1.This parameter is characterized and is not 100% tested.R F 13.Pin Capacitancef = 1 MHz, T = 25°C (1)Symbol Typ Max Units Conditions C IN 46pF V IN = 0V C OUT 812pFV OUT = 0V80270L–PEEPR–2/09AT28C64B15.AC Write Waveforms15.1WE Controlled15.2CE Controlled14.AC Write CharacteristicsSymbol ParameterMin MaxUnits t AS , t OES Address, OE Setup Time 0ns t AH Address Hold Time 50ns t CS Chip Select Setup Time 0ns t CH Chip Select Hold Time 0ns t WP Write Pulse Width (WE or CE)100ns t DS Data Setup Time 50ns t DH , t OEHData, OE Hold Timens90270L–PEEPR–2/09AT28C64B17.Page Mode Write Waveforms (1)(2)Notes: 1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE).2.OE must be high only when WE and CE are both low.18.Chip Erase Waveformst S = t H = 1 µs (min.)t W = 10 ms (min.)V H = 12.0V ±0.5V16.Page Mode CharacteristicsSymbol Parameter MinMax Units t WC Write Cycle Time10ms t WC Write Cycle Time (option available – Ref. A T28HC64BF datasheet)2ms t AS Address Setup Time 0ns t AH Address Hold Time 50ns t DS Data Setup Time 50ns t DH Data Hold Time 0ns t WP Write Pulse Width 100ns t BLC Byte Load Cycle Time 150µs t WPHWrite Pulse Width High50ns100270L–PEEPR–2/09AT28C64B19.Software Data Protection EnableAlgorithm (1)Notes:1.Data Format: I/O7 - I/O0 (Hex);Address Format: A12 - A0 (Hex).2.Write Protect state will be activated at end of writeeven if no other data is loaded.3.Write Protect state will be deactivated at end of writeperiod even if no other data is loaded.4.1 to 64 bytes of data are loaded.20.Software Data Protection DisableAlgorithm (1)Notes:1.Data Format: I/O7 - I/O0 (Hex);Address Format: A12 - A0 (Hex).2.Write Protect state will be activated at end of writeeven if no other data is loaded.3.Write Protect state will be deactivated at end of writeperiod even if no other data is loaded.4. 1 to 64 bytes of data are loaded.21.Software Protected Write Cycle Waveforms (1)(2)Notes:1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the softwarecode has been entered.2.OE must be high only when WE and CE are both low.AT28C64BNotes:1.These parameters are characterized and not 100% tested. See “AC Read Characteristics” on page 6.23.Data Polling WaveformsNotes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics” on page 6.25.Toggle Bit Waveforms (1)(2)(3)Notes: 1.Toggling either OE or CE or both OE and CE will operate toggle bit.2.Beginning and ending state of I/O6 will vary.3.Any address location may be used but the address should not vary.22.Data Polling Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 0ns t OEH OE Hold Time 0ns t OE OE to Output Delay (1)ns t WR Write Recovery Time 0ns24.Toggle Bit Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 10ns t OEH OE Hold Time 10ns t OE OE to Output Delay (2)ns t OEHP OE High Pulse150ns t WR Write Recovery Timens26.Normalized I CC GraphsAT28C64B27.Ordering Information27.1Green Package Option (Pb/Halide-free)t ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby150400.1A T28C64B-15JU32JIndustrial(-40°C to 85°C) A T28C64B-15SU28SA T28C64B-15TU28TA T28C64B-15PU28P627.2Die ProductsContact Atmel Sales for die sales options.Package Type32J32-lead, Plastic J-leaded Chip Carrier (PLCC)28P628-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)28S28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T28-lead, Plastic Thin Small Outline Package (TSOP)28.Packaging Information 28.132J – PLCCAT28C64B 28.228P6 – PDIP28.328S – SOICAT28C64B 28.428T – TSOP。

实验题目存储器部件教学实验一、实验目的：1. 熟悉ROM芯片和RAM芯片在功能和使用方法等方面的相同和差异之处。

学习用编程器设备向EEPROM芯片内写入一批数据的过程和方法。

2. 理解并熟悉通过字、位扩展技术实现扩展存储器系统容量的方案。

3. 了解静态存储器系统使用的各种控制信号之间正常的时序关系。

4. 了解如何通过读、写存储顺的指令实现对58C65 ROM芯片的读、写操作。

加深理解存储器部件在计算机整机系统中的作用。

二、实验设备与器材：TEC-XP+教学实验系统和仿真终端软件PCEC。

三、实验说明和原理：1、内存储器原理内存储器是计算机中存放正在运行中的程序和相关数据的部件。

在教学计算机存储器部件设计中，出于简化和容易实现的目的，选用静态存储器芯片实现内存储器的存储体，包括唯读存储区和随读写存储区两部分，ROM存储区选用4片长度8位、容易8KB的58C65芯片实现，RAM存储区选用2片长度8位、容量2KB的6116芯片实现，每2个8位的芯片合成一组用于组成16位长度的内存字，6个芯片被分成3组，其地址空间分配关系是：0-1777h用于第一组ROM，固化监控程序，2000-2777h用于RAM，保存用户程序和用户数据，其高端的一些单元作监控程序的数据区，第二组ROM的地址范围可以由用户选择，主要用于完成扩展内存容量的教学实验。

地址总线的低13位送到ROM芯片的地址线引脚，用于选择芯片内的一个存储字。

用于实现存储字的高位字节的3个芯片的数据线引脚、实现低位字节的3个芯片的数据线引脚分别连接在一起接到数据总线的高、低位字节，是实现存储器数据读写的信息通路。

数据总线要通过一个双向三态门电路与CPU一侧的内部总线IB 相连接，已完成存储器、接口电路和CPU之间的数据通讯。

2、扩展教学机的存储空间四、实验内容：1) 要完成存储器容量扩展的教学实验，需为扩展存储器选择一个地址，并注意读写和OE等控制信号的正确状态。

A t m e l改变命名规则的芯片型号对照表乐享集团公司，写于2021年6月16日ATMLU对应ATMEL芯片：换代选型2011-04-25 23:57AT24C01BN-SH-B/T ATMEL ATMLU701 DIP AT24C01B-PU ATMELATMLU702 DIPATMEL ATMLU703 DIPAT24C02BN-SH-B/T ATMEL ATMLU704 DIP AT24C02B-PU ATMEL ATMLU705 DIPATMEL ATMLU706DIPAT24C04BN-SH-B ATMEL ATMLU707 DIP ATMELATMLU708 DIP ATMEL ATMLU709 DIP ATMEL ATMLU710 DIPATMEL ATMLU711 DIPATMEL ATMLU712 DIPATMEL ATMLU713 DIPATMEL ATMLU714 DIPATMELATMLU715 DIPATMEL ATMLU716 DIPAT24C16BN-SH-B ATMEL ATMLU717 DIPATMEL ATMLU718 DIPATMEL ATMLU719 DIPAT24C256BN-SH-T ATMEL ATMLU720 DIP AT24C256B-PU ATMEL ATMLU721 DIPAT24C256N-10SI18 ATMEL ATMLU722 DIP ATMEL ATMLU723 DIPATMEL ATMLU724 DIPAT24C32CN-SH-T ATMEL ATMLU725DIPATMEL ATMLU726 DIPAT24C512BN-SH25-B ATMEL ATMLU727 DIP AT24C512BN-SH-B ATMELATMLU728 DIPAT24C512B-PU25 ATMELATMLU729 DIPATMEL ATMLU730 DIPATMEL ATMLU731 DIPATMELATMLU732 DIPAT24C64CN-SH-B ATMELATMLU733 DIPAT24C64CN-SH-T ATMEL ATMLU734 DIPATMEL ATMLU735 DIPATMEL ATMLU736 DIPAT25DF041A-SH-B ATMEL ATMLU737DIPATMEL ATMLU738 DIPATMEL ATMLU739DIPAT26DF081A-SSU-SL965 ATMEL ATMLU740 DIP AT26DF081A-SU-SL965 ATMEL ATMLU741 DIP AT26DF161-SUATMEL ATMLU742DIPAT26DF321-SU ATMEL ATMLU743DIPAT27BV256-70JU ATMELATMLU744 DIPAT27C010-70PUATMEL ATMLU745 DIPAT27C040-70PU ATMEL ATMLU746DIPAT27C256R-70PU ATMEL ATMLU748DIP AT27C512R-70JU ATMELATMLU749 DIP AT28BV256-20TU ATMEL ATMLU750 DIP AT28C256-15PU ATMEL ATMLU751 DIP AT28C64B-15JU ATMEL ATMLU752 DIP AT28C64B-15PU ATMEL ATMLU801 DIP AT28C64B-15SUATMELATMLU802 DIPAT29C010A-70JU ATMEL ATMLU803 DIP AT29C020-90JU ATMELATMLU804 DIP AT29C020-90TU ATMEL ATMLU805 DIP AT29C040A-90JU ATMEL ATMLU806 DIP AT29C040A-90TU ATMEL ATMLU807DIP AT29LV020-10TUATMEL ATMLU808 DIP AT29LV040A-15JU ATMEL ATMLU809 DIP AT29LV512-12JUATMELATMLU810 DIP AT45DB021B-SU ATMEL ATMLU811DIP AT45DB041D-SU ATMEL ATMLU812 DIP AT45DB081D-SU ATMELATMLU813 DIP AT45DB161D-SU ATMEL ATMLU814 DIP AT45DB161D-TU ATMEL ATMLU815DIP AT45DB321D-SU ATMEL ATMLU816 DIP AT45DB321D-TU ATMEL ATMLU817 DIPAT47BV163A-70TU ATMEL ATMLU819 DIPAT49BV040B-JU ATMEL ATMLU820 DIPAT49BV322DT-70TU ATMEL ATMLU821 DIP AT49BV512-90TU ATMEL ATMLU822 DIPAT73C213 ATMEL ATMLU823 DIPAT76C112 ATMEL ATMLU824 DIPAT76C120H-MU1-JZ208 ATMEL ATMLU825 DIP AT80251G2D-SLSUM ATMEL ATMLU826 DIP AT80C32X2-3CSUM ATMEL ATMLU827 DIPAT80C32X2-RLTUM ATMEL ATMLU828 DIPAT80C32X2-SLSUM ATMEL ATMLU829 DIPAT83C24-TISIL ATMEL ATMLU830 DIPAT88SC0104C-SU ATMEL ATMLU831 DIPAT88SC153-10SU ATMEL ATMLU832 DIPAT89C2051-12PU ATMEL ATMLU833 DIPAT89C2051-12SU ATMEL ATMLU834 DIPAT89C2051-24PU ATMEL ATMLU835 DIPAT89C2051-24SU ATMEL ATMLU836 DIPAT89C4051-24PU ATMEL ATMLU837 DIPAT89C4051-24SU ATMEL ATMLU838 DIPAT89C5131A-S3SUM ATMEL ATMLU839 DIP AT89C51AC2-RLTUM ATMEL ATMLU840 DIPAT89C51CC01CA-RLTUM ATMEL ATMLU841 DIP AT89C51CC01CA-SLSUM ATMEL ATMLU842 DIP AT89C51CC01UA-RLTUM ATMEL ATMLU843 DIP AT89C51CC01UA-SLSUM ATMEL ATMLU844 DIP AT89C51ED2-RDTUM ATMEL ATMLU845 DIP AT89C51ED2-RLTUM ATMEL ATMLU846 DIP AT89C51ED2-SLSUM ATMEL ATMLU847 DIP AT89C51ED2-SMSUM ATMEL ATMLU848 DIP AT89C51RB2-3CSUM ATMEL ATMLU849 DIP AT89C51RB2-RLTUM ATMEL ATMLU850 DIP AT89C51RB2-SLSUM ATMEL ATMLU851 DIP AT89C51RC2-3CSUM ATMEL ATMLU852 DIP AT89C51RC-24JU ATMEL ATMLU901 DIPAT89C51RC-24PU ATMEL ATMLU902 DIPAT89C51RC2-RLTUM ATMEL ATMLU903 DIP AT89C51RC2-SLSUM ATMEL ATMLU904 DIP AT89C51RD2-RLTUM ATMEL ATMLU905 DIP AT89C51RD2-SLRUM ATMEL ATMLU906 DIP AT89C51RD2-SLSUM ATMEL ATMLU907 DIP AT89C51-24PC ATMEL ATMLU908 DIPAT89C51-24PI ATMEL ATMLU909 DIPAT89C52-24JI ATMEL ATMLU910 DIPAT89C52-24PI ATMEL ATMLH701 SOPAT89C55WD-24AU ATMEL ATMLH702 SOP AT89C55WD-24JU ATMEL ATMLH703 SOP AT89C55WD-24PU ATMEL ATMLH704 SOP AT89LS52-16JU ATMEL ATMLH705 SOPAT89LS52-16PU ATMEL ATMLH706 SOPAT89LV51-12AI ATMEL ATMLH707 SOPAT89S51-24AU ATMEL ATMLH708 SOPAT89S51-24PU ATMEL ATMLH709 SOPAT89S52-24AU ATMEL ATMLH710 SOPAT89S52-24JU ATMEL ATMLH711 SOPAT89S52-24PU ATMEL ATMLH712 SOPAT89S54-3CSIM ATMEL ATMLH713 SOPAT89S54-SLSIM ATMEL ATMLH714 SOPAT89S58-SLSIM ATMEL ATMLH715 SOPAT89S8253-24AU ATMEL ATMLH716 SOP AT89S8253-24JU ATMEL ATMLH717 SOP AT89S8253-24PU ATMEL ATMLH718 SOP AT90CAN128-16AU ATMEL ATMLH719 SOP AT90CAN32-16AU ATMEL ATMLH720 SOP AT91M40800-33AU ATMEL ATMLH721 SOP AT91M55800A-33AU ATMEL ATMLH722 SOP AT91RM9200-CJ-002 ATMEL ATMLH723 SOP AT91RM9200-QU-002 ATMEL ATMLH724 SOPAT91SAM7S256-AU-001 ATMEL ATMLH725 SOP AT91SAM7S321-AU ATMEL ATMLH726 SOPAT91SAM7S32-AU-001 ATMEL ATMLH727 SOP AT91SAM7S64-AU-001 ATMEL ATMLH728 SOP AT91SAM7SE32-AU ATMEL ATMLH729 SOPAT91SAM7X256-AU ATMEL ATMLH730 SOPAT91SAM9260-CJ ATMEL ATMLH731 SOPAT91SAM9260-EK ATMEL ATMLH732 SOPAT91SAM9261-EK ATMEL ATMLH733 SOPAT91SAM9261S-CU ATMEL ATMLH734 SOPAT91SAM9263-CU ATMEL ATMLH735 SOPAT91SAM7X-EK ATMEL ATMLH736 SOPAT91SAM-ICE ATMEL ATMLH737 SOPATMEL ATMLH738 SOPATMEL ATMLH739 SOPAT93C46DN-SH-B ATMEL ATMLH740 SOPAT93C46D-TH-T ATMEL ATMLH741 SOPATMEL ATMLH742 SOPATMEL ATMLH743 SOPAT93C66A-10PU27 ATMEL ATMLH744 SOPATMEL ATMLH745 SOPATMEL ATMLH746 SOPATAVRDRAGON ATMEL ATMLH747 SOPATAVRISP2 ATMEL ATMLH748 SOPATF1502AS-15JC44 ATMEL ATMLH749 SOP ATF1508AS-15AC100 ATMEL ATMLH750 SOP ATF1508AS-15JC84 ATMEL ATMLH751 SOP ATF16V8B-15JU ATMEL ATMLH752 SOP ATF16V8B-15PC ATMEL ATMLH801 SOP ATF16V8B-15PU ATMEL ATMLH802 SOP ATF16V8BQL-15JC ATMEL ATMLH803 SOP ATF20V8B-15JC ATMEL ATMLH804 SOP ATJTAGICE2 ATMEL ATMLH805 SOP ATMEGA1280V-8AU ATMEL ATMLH806 SOP ATMEGA128-16AU ATMEL ATMLH807 SOP ATMEGA128L-8AU ATMEL ATMLH808 SOP ATMEGA16-16AU ATMEL ATMLH809 SOP ATMEGA16-16PU ATMEL ATMLH810 SOP ATMEGA162-16PU ATMEL ATMLH811 SOP ATMEGA162V-8AU ATMEL ATMLH812 SOP ATMEGA168-20AU ATMEL ATMLH813 SOP ATMEGA168-20MU ATMEL ATMLH814 SOP ATMEGA168-20PU ATMEL ATMLH815 SOP ATMEGA168V-10AU ATMEL ATMLH816 SOP ATMEGA169P-16AU ATMEL ATMLH817 SOP ATMEGA169PV-8AU ATMEL ATMLH818 SOPATMEGA169V-8AU ATMEL ATMLH819 SOP ATMEGA16L-8AU ATMEL ATMLH820 SOP ATMEGA16L-8PU ATMEL ATMLH821 SOP ATMEGA32-16AU ATMEL ATMLH822 SOP ATMEGA32-16PU ATMEL ATMLH823 SOP ATMEGA325V-8MU ATMEL ATMLH824 SOP ATMEGA32L-8AU ATMEL ATMLH825 SOP ATMEGA32L-8PU ATMEL ATMLH826 SOP ATMEGA48-20AU ATMEL ATMLH827 SOP ATMEGA48V-10AU ATMEL ATMLH828 SOP ATMEGA48V-10PU ATMEL ATMLH829 SOP ATMEGA48V-10MU ATMEL ATMLH830 SOP ATMEGA640V-8AU ATMEL ATMLH831 SOP ATMEGA64-16AU ATMEL ATMLH832 SOP ATMEGA64L-8AU ATMEL ATMLH833 SOP ATMEGA8-16AU ATMEL ATMLH834 SOP ATMEGA8-16PU ATMEL ATMLH835 SOP ATMEGA8515-16AU ATMEL ATMLH836 SOP ATMEGA8515-16JU ATMEL ATMLH837 SOP ATMEGA8515-16PU ATMEL ATMLH838 SOP ATMEGA8515L-8JU ATMEL ATMLH839 SOP ATMEGA8535-16JI ATMEL ATMLH840 SOP ATMEGA8535-16JU ATMEL ATMLH841 SOPATMEGA8535-16PU ATMEL ATMLH842 SOP ATMEGA8535L-8AU ATMEL ATMLH843 SOP ATMEGA8535L-8JU ATMEL ATMLH844 SOP ATMEGA8535L-8PU ATMEL ATMLH845 SOP ATMEGA88-20AU ATMEL ATMLH846 SOP ATMEGA88-20MU ATMEL ATMLH847 SOP ATMEGA88-20PU ATMEL ATMLH848 SOP ATMEGA88V-10AU ATMEL ATMLH849 SOP ATMEGA88V-10MU ATMEL ATMLH850 SOP ATMEGA88V-10PU ATMEL ATMLH851 SOP ATMEGA8L-8AU ATMEL ATMLH852 SOP ATMEGA8L-8PU ATMEL ATMLH901 SOP ATTINY11L-2SU ATMEL ATMLH902 SOP ATTINY13-20SU ATMEL ATMLH903 SOP ATTINY13V-10PU ATMEL ATMLH904 SOP ATTINY13V-10SSU ATMEL ATMLH905 SOP ATTINY13V-10SU ATMEL ATMLH906 SOP ATTINY15L-1PU ATMEL ATMLH907 SOP ATTINY2313-20PU ATMEL ATMLH908 SOP ATTINY2313-20SU ATMEL ATMLH909 SOP ATTINY2313V-10PU ATMEL ATMLH910 SOP AT24C01BN-SH-B/T ATMEL ATMLU701 DIP AT24C01B-PI ATMEL ATMLU702 DIPAT24C02BN-SH-B/T ATMEL ATMLU704 DIP AT24C02B-PI ATMEL ATMLU705 DIPATMEL ATMLU706 DIPAT24C04BN-SH-B ATMEL ATMLU707 DIP ATMEL ATMLU708 DIPATMEL ATMLU709 DIPATMEL ATMLU710 DIPATMEL ATMLU711 DIPATMEL ATMLU712 DIPATMEL ATMLU713 DIPATMEL ATMLU714 DIPATMEL ATMLU715 DIPATMEL ATMLU716 DIPAT24C16BN-SH-B ATMEL ATMLU717 DIP ATMEL ATMLU718 DIPATMEL ATMLU719 DIPAT24C256BN-SH-T ATMEL ATMLU720 DIP AT24C256B-PI ATMEL ATMLU721 DIPAT24C256N-10SI18 ATMEL ATMLU722 DIP ATMEL ATMLU723 DIPATMEL ATMLU724 DIPAT24C32CN-SH-T ATMEL ATMLU725 DIPAT24C512BN-SH25-B ATMEL ATMLU727 DIP AT24C512BN-SH-B ATMEL ATMLU728 DIPAT24C512B-PI25 ATMEL ATMLU729 DIPATMEL ATMLU730 DIPATMEL ATMLU731 DIPATMEL ATMLU732 DIPAT24C64CN-SH-B ATMEL ATMLU733 DIPAT24C64CN-SH-T ATMEL ATMLU734 DIPATMEL ATMLU735 DIPATMEL ATMLU736 DIPAT25DF041A-SH-B ATMEL ATMLU737 DIPATMEL ATMLU738 DIPATMEL ATMLU739 DIPAT26DF081A-SSI-SL965 ATMEL ATMLU740 DIP AT26DF081A-SI-SL965 ATMEL ATMLU741 DIP AT26DF161-SI ATMEL ATMLU742 DIPAT26DF321-SI ATMEL ATMLU743 DIPAT27BV256-70JI ATMEL ATMLU744 DIPAT27C010-70PI ATMEL ATMLU745 DIPAT27C040-70PI ATMEL ATMLU746 DIPAT27C256R-70JI ATMEL ATMLU747 DIPAT27C256R-70PI ATMEL ATMLU748 DIPAT28BV256-20TI ATMEL ATMLU750 DIP AT28C256-15PI ATMEL ATMLU751 DIP AT28C64B-15JI ATMEL ATMLU752 DIP AT28C64B-15PI ATMEL ATMLU801 DIP AT28C64B-15SI ATMEL ATMLU802 DIP AT29C010A-70JI ATMEL ATMLU803 DIP AT29C020-90JI ATMEL ATMLU804 DIP AT29C020-90TI ATMEL ATMLU805 DIP AT29C040A-90JI ATMEL ATMLU806 DIP AT29C040A-90TI ATMEL ATMLU807 DIP AT29LV020-10TI ATMEL ATMLU808 DIP AT29LV040A-15JI ATMEL ATMLU809 DIP AT29LV512-12JI ATMEL ATMLU810 DIP AT45DB021B-SI ATMEL ATMLU811 DIP AT45DB041D-SI ATMEL ATMLU812 DIP AT45DB081D-SI ATMEL ATMLU813 DIP AT45DB161D-SI ATMEL ATMLU814 DIP AT45DB161D-TI ATMEL ATMLU815 DIP AT45DB321D-SI ATMEL ATMLU816 DIP AT45DB321D-TI ATMEL ATMLU817 DIP AT45DB642D-TI ATMEL ATMLU818 DIP AT47BV163A-70TI ATMEL ATMLU819 DIPAT49BV322DT-70TI ATMEL ATMLU821 DIP AT49BV512-90TI ATMEL ATMLU822 DIPAT73C213 ATMEL ATMLU823 DIPAT76C112 ATMEL ATMLU824 DIPAT76C120H-MI1-JZ208 ATMEL ATMLU825 DIP AT80251G2D-SLSIM ATMEL ATMLU826 DIP AT80C32X2-3CSIM ATMEL ATMLU827 DIPAT80C32X2-RLTIM ATMEL ATMLU828 DIPAT80C32X2-SLSIM ATMEL ATMLU829 DIPAT83C24-TISIL ATMEL ATMLU830 DIPAT88SC0104C-SI ATMEL ATMLU831 DIPAT88SC153-10SI ATMEL ATMLU832 DIPAT89C2051-12PI ATMEL ATMLU833 DIPAT89C2051-12SI ATMEL ATMLU834 DIPAT89C2051-24PI ATMEL ATMLU835 DIPAT89C2051-24SI ATMEL ATMLU836 DIPAT89C4051-24PI ATMEL ATMLU837 DIPAT89C4051-24SI ATMEL ATMLU838 DIPAT89C5131A-S3SIM ATMEL ATMLU839 DIP AT89C51AC2-RLTIM ATMEL ATMLU840 DIP AT89C51CC01CA-RLTIM ATMEL ATMLU841 DIP AT89C51CC01CA-SLSIM ATMEL ATMLU842 DIPAT89C51CC01IA-RLTIM ATMEL ATMLU843 DIP AT89C51CC01IA-SLSIM ATMEL ATMLU844 DIP AT89C51ED2-RDTIM ATMEL ATMLU845 DIP AT89C51ED2-RLTIM ATMEL ATMLU846 DIP AT89C51ED2-SLSIM ATMEL ATMLU847 DIP AT89C51ED2-SMSIM ATMEL ATMLU848 DIP AT89C51RB2-3CSIM ATMEL ATMLU849 DIP AT89C51RB2-RLTIM ATMEL ATMLU850 DIP AT89C51RB2-SLSIM ATMEL ATMLU851 DIP AT89C51RC2-3CSIM ATMEL ATMLU852 DIP AT89C51RC-24JI ATMEL ATMLU901 DIPAT89C51RC-24PI ATMEL ATMLU902 DIPAT89C51RC2-RLTIM ATMEL ATMLU903 DIP AT89C51RC2-SLSIM ATMEL ATMLU904 DIP AT89C51RD2-RLTIM ATMEL ATMLU905 DIP AT89C51RD2-SLRIM ATMEL ATMLU906 DIP AT89C51RD2-SLSIM ATMEL ATMLU907 DIP AT89C51-24PC ATMEL ATMLU908 DIPAT89C51-24PI ATMEL ATMLU909 DIPAT89C52-24JI ATMEL ATMLU910 DIPAT89C52-24PI ATMEL ATMLH701 SOPAT89C55WD-24AI ATMEL ATMLH702 SOPAT89C55WD-24JI ATMEL ATMLH703 SOPAT89C55WD-24PI ATMEL ATMLH704 SOPAT89LS52-16JI ATMEL ATMLH705 SOPAT89LS52-16PI ATMEL ATMLH706 SOPAT89LV51-12AI ATMEL ATMLH707 SOPAT89S51-24AI ATMEL ATMLH708 SOPAT89S51-24PI ATMEL ATMLH709 SOPAT89S52-24AI ATMEL ATMLH710 SOPAT89S52-24JI ATMEL ATMLH711 SOPAT89S52-24PI ATMEL ATMLH712 SOPAT89S54-3CSIM ATMEL ATMLH713 SOPAT89S54-SLSIM ATMEL ATMLH714 SOPAT89S58-SLSIM ATMEL ATMLH715 SOPAT89S8253-24AI ATMEL ATMLH716 SOPAT89S8253-24JI ATMEL ATMLH717 SOPAT89S8253-24PI ATMEL ATMLH718 SOPAT90CAN128-16AI ATMEL ATMLH719 SOPAT90CAN32-16AI ATMEL ATMLH720 SOPAT91M40800-33AI ATMEL ATMLH721 SOPAT91M55800A-33AI ATMEL ATMLH722 SOP AT91RM9200-CJ-002 ATMEL ATMLH723 SOP AT91RM9200-QI-002 ATMEL ATMLH724 SOP AT91SAM7S256-AI-001 ATMEL ATMLH725 SOP AT91SAM7S321-AI ATMEL ATMLH726 SOPAT91SAM7S64-AI-001 ATMEL ATMLH728 SOP AT91SAM7SE32-AI ATMEL ATMLH729 SOP AT91SAM7X256-AI ATMEL ATMLH730 SOP AT91SAM9260-CJ ATMEL ATMLH731 SOPAT91SAM9260-EK ATMEL ATMLH732 SOPAT91SAM9261-EK ATMEL ATMLH733 SOPAT91SAM9261S-CI ATMEL ATMLH734 SOP AT91SAM9263-CI ATMEL ATMLH735 SOPAT91SAM7X-EK ATMEL ATMLH736 SOPAT91SAM-ICE ATMEL ATMLH737 SOPATMEL ATMLH738 SOPATMEL ATMLH739 SOPAT93C46DN-SH-B ATMEL ATMLH740 SOPAT93C46D-TH-T ATMEL ATMLH741 SOPATMEL ATMLH742 SOPATMEL ATMLH743 SOPAT93C66A-10PI27 ATMEL ATMLH744 SOPATMEL ATMLH745 SOPATMEL ATMLH746 SOPATAVRDRAGON ATMEL ATMLH747 SOP ATAVRISP2 ATMEL ATMLH748 SOPATF1502AS-15JC44 ATMEL ATMLH749 SOPATF1508AS-15JC84 ATMEL ATMLH751 SOP ATF16V8B-15JI ATMEL ATMLH752 SOP ATF16V8B-15PC ATMEL ATMLH801 SOP ATF16V8B-15PI ATMEL ATMLH802 SOP ATF16V8BQL-15JC ATMEL ATMLH803 SOP ATF20V8B-15JC ATMEL ATMLH804 SOP AT JTAGICE MKII ATMEL ATMLH805 SOP ATMEGA1280V-8AI ATMEL ATMLH806 SOP ATMEGA128-16AI ATMEL ATMLH807 SOP ATMEGA128L-8AI ATMEL ATMLH808 SOP ATMEGA16-16AI ATMEL ATMLH809 SOP ATMEGA16-16PI ATMEL ATMLH810 SOP ATMEGA162-16PI ATMEL ATMLH811 SOP ATMEGA162V-8AI ATMEL ATMLH812 SOP ATMEGA168-20AI ATMEL ATMLH813 SOP ATMEGA168-20MI ATMEL ATMLH814 SOP ATMEGA168-20PI ATMEL ATMLH815 SOP ATMEGA168V-10AI ATMEL ATMLH816 SOP ATMEGA169P-16AI ATMEL ATMLH817 SOP ATMEGA169PV-8AI ATMEL ATMLH818 SOP ATMEGA169V-8AI ATMEL ATMLH819 SOP ATMEGA16L-8AI ATMEL ATMLH820 SOPATMEGA16L-8PI ATMEL ATMLH821 SOP ATMEGA32-16AI ATMEL ATMLH822 SOP ATMEGA32-16PI ATMEL ATMLH823 SOP ATMEGA325V-8MI ATMEL ATMLH824 SOP ATMEGA32L-8AI ATMEL ATMLH825 SOP ATMEGA32L-8PI ATMEL ATMLH826 SOP ATMEGA48-20AI ATMEL ATMLH827 SOP ATMEGA48V-10AI ATMEL ATMLH828 SOP ATMEGA48V-10PI ATMEL ATMLH829 SOP ATMEGA48V-10MI ATMEL ATMLH830 SOP ATMEGA640V-8AI ATMEL ATMLH831 SOP ATMEGA64-16AI ATMEL ATMLH832 SOP ATMEGA64L-8AI ATMEL ATMLH833 SOP ATMEGA8-16AI ATMEL ATMLH834 SOP ATMEGA8-16PI ATMEL ATMLH835 SOP ATMEGA8515-16AI ATMEL ATMLH836 SOP ATMEGA8515-16JI ATMEL ATMLH837 SOP ATMEGA8515-16PI ATMEL ATMLH838 SOP ATMEGA8515L-8JI ATMEL ATMLH839 SOP ATMEGA8535-16JI ATMEL ATMLH840 SOP ATMEGA8535-16JI ATMEL ATMLH841 SOP ATMEGA8535-16PI ATMEL ATMLH842 SOP ATMEGA8535L-8AI ATMEL ATMLH843 SOPATMEGA8535L-8JI ATMEL ATMLH844 SOP ATMEGA8535L-8PI ATMEL ATMLH845 SOP ATMEGA88-20AI ATMEL ATMLH846 SOP ATMEGA88-20MI ATMEL ATMLH847 SOP ATMEGA88-20PI ATMEL ATMLH848 SOP ATMEGA88V-10AI ATMEL ATMLH849 SOP ATMEGA88V-10MI ATMEL ATMLH850 SOP ATMEGA88V-10PI ATMEL ATMLH851 SOP ATMEGA8L-8AI ATMEL ATMLH852 SOP ATMEGA8L-8PI ATMEL ATMLH901 SOP ATTINY11L-2SI ATMEL ATMLH902 SOP ATTINY13-20SI ATMEL ATMLH903 SOP ATTINY13V-10PI ATMEL ATMLH904 SOP ATTINY13V-10SSI ATMEL ATMLH905 SOP ATTINY13V-10SI ATMEL ATMLH906 SOP ATTINY15L-1PI ATMEL ATMLH907 SOP ATTINY2313-20PI ATMEL ATMLH908 SOP ATTINY2313-20SI ATMEL ATMLH909 SOP ATTINY2313V-10PI ATMEL ATMLH910 SOP AT17LV010-10PI 1000 ATMEL0007AT17LV256-10JI 1000 ATMEL0008AT17LV256-10PC 1000 ATMEL0009AT17LV256-10PI 1000 ATMEL0010AT17LV512-10PC 1000 ATMEL0011 AT17LV512-10PC 1000 ATMEL0012 AT17LV512A-10PI 1000 ATMEL0013 AT17LV65-10PI 1000 ATMEL0014 AT22V10-15DC 1000 ATMEL0015 AT22V10-15JC 1000 ATMEL0016 AT22V10-15KC 1000 ATMEL0017 AT22V10-20DC 1000 ATMEL0018 AT22V10-20JC 1000 ATMEL0019 AT22V10-25DC 1000 ATMEL0020 AT22V10-25JC 1000 ATMEL0021 AT22V10-25JI 1000 ATMEL0022 AT22V10-25KC 1000 ATMEL0023 AT22V10-35DC 1000 ATMEL0024 AT22V10-35JC 1000 ATMEL0025 AT22V10-35KC 1000 ATMEL0026 AT22V10-35PC 1000 ATMEL0027 AT22V10L-20PC 1000 ATMEL0028 AT22V10L-25DC 1000 ATMEL0029 AT22V10L-25JC 1000 ATMEL0030 AT22V10L-25JI 1000 ATMEL0031 AT22V10L-35DC 1000 ATMEL0032 AT24C01-10PC 1000 ATMEL0033AT24C01-10PI 1000 ATMEL00351000 ATMEL0036AT24C01-10SC 1000 ATMEL0037 AT24C01A-10PC 8000 ATMEL0038 AT24C01A-10SC 8000 ATMEL0039 8000 ATMEL00408000 ATMEL06018000 ATMEL0041AT24C01BN-SH-B 8000 ATMEL0042 AT24C01BN-SH-T 8000 ATMEL0043 AT24C01B-PU 8000 ATMEL0602AT24C01B-TH-B 8000 ATMEL0044 AT24C01B-TH-T 8000 ATMEL0045 AT24C01BTSU-T 8000 ATMEL0603 AT24C01BU3-UU-T 8000 ATMEL0604 AT24C01B-W-11 8000 ATMEL0046 AT24C01BY6-YH-T 8000 ATMEL0047 8000 ATMEL0048AT24C02-10PC 8000 ATMEL00498000 ATMEL00508000 ATMEL00518000 ATMEL00528000 ATMEL01018000 ATMEL01028000 ATMEL01038000 ATMEL06068000 ATMEL01048000 ATMEL06078000 ATMEL01058000 ATMEL01068000 ATMEL01078000 ATMEL01088000 ATMEL01098000 ATMEL06088000 ATMEL01108000 ATMEL01118000 ATMEL0112 8000 ATMEL0113 8000 ATMEL01148000 ATMEL06098000 ATMEL06108000 ATMEL01158000 ATMEL01168000 ATMEL01178000 ATMEL06118000 ATMEL06138000 ATMEL01188000 ATMEL01198000 ATMEL01208000 ATMEL06148000 ATMEL06158000 ATMEL01218000 ATMEL01228000 ATMEL01238000 ATMEL06168000 ATMEL06178000 ATMEL01248000 ATMEL0125AT24C16-10PI 8000 ATMEL0126 8000 ATMEL0127AT24C164-10PC 8000 ATMEL0128 8000 ATMEL0129AT24C164-10PI 8000 ATMEL0130 AT24C164-10SC 8000 ATMEL0131 8000 ATMEL01328000 ATMEL01338000 ATMEL01348000 ATMEL01368000 ATMEL01378000 ATMEL0138AT24C16N-SC 8000 ATMEL0139 8000 ATMEL01408000 ATMEL01418000 ATMEL01428000 ATMEL01438000 ATMEL01448000 ATMEL01458000 ATMEL0146AT24C256-10PC 8000 ATMEL0147 8000 ATMEL01488000 ATMEL01498000 ATMEL01508000 ATMEL01518000 ATMEL01528000 ATMEL0201AT24C32-10PC 8000 ATMEL0202 AT24C32－ 8000 ATMEL02038000 ATMEL02048000 ATMEL02058000 ATMEL0207AT24C32N-SC 8000 ATMEL0208AT24C32W-10SI 8000 ATMEL02098000 ATMEL02108000 ATMEL06188000 ATMEL02118000 ATMEL02128000 ATMEL02138000 ATMEL02148000 ATMEL06198000 ATMEL02158000 ATMEL02168000 ATMEL02178000 ATMEL02188000 ATMEL02198000 ATMEL06208000 ATMEL02208000 ATMEL0221AT24C64-SC 8000 ATMEL0222AT24RF08CN 1000 ATMEL0223。

L90多功能编程器使用说明L90多功能编程器，功能强大，支持最新的主板BIOS spi 25Xxxx 在线编程和高速烧写EPROM、EEPROM、FLASH和串行EEPROM 系列芯片，并且还直接支持PIC、MCS51、AVR单片机芯片；价格低，性价比高；既适合于电子和电脑爱好者使用，也适合于电子电脑维修人员和单片机开发人员使用。

一、特点：1、使用优质3M 32脚镀银锁紧座，夹具专用孔型18脚、8脚DIP插座，优质进口PLCC32座性能稳定可靠。

2、全新设计，使用USB和外接电源双接口供电，并使用25针PC并行打印口通讯，具有较高的写片速度。

3、采用WINDOWS下的图形界面，使用鼠标进行操作，支持Windows 95/98/ME/2000/XP系统。

4、支持最新810、815、845、848、865、875、915等等主板上使用的大容量FWH/LPC BIOS芯片，性能价格比高。

对于电脑爱好者维修者，可用来对电脑的各种板卡的BIOS芯片进行编程，修复被病毒破坏的主板BIOS芯片，对主板、显卡等的BIOS芯片进行升级以提升计算机性能等等。

5、主板上集成了93CXX、24CXX、25CXX PIC 16FXX、DIP32Z转PLCC32、FWH/LPC PLCC32适配器，支持51系列单片机的全系列型号，可用来进行单片机开发；支持最新的大容量程序芯片；支持12.5V、15V、21V、25V多种编程电压，直接支持3.3V及2.9V电压的芯片（即显卡的BIOS芯片如SST39VF512等）。

6、全新设计的硬件，让使用者更容易使用，控制程序工作界面友好，具有编程指示！对芯片的各种操作变得十分简单，无论是电子专业人员还是电脑爱好者、维修者都可轻松掌握。

7、软件随时更新，最新软件可免费获取。

注意：1、计算机的并口要在BIOS中设置为ECP或者ECP+EPP；2、多功能编程器使用的联机电缆是25针对25孔标准。

1/24June 2000M28C6464Kbit (8K x 8)Parallel EEPROMWith Software Data ProtectionsFast Access Time:–90ns at V CC =5V for M28C64and M28C64-A –120ns at V CC =3V for M28C64-xxWsSingle Supply Voltage:–4.5V to 5.5V for M28C64and M28C64-A –2.7V to 3.6V for M28C64-xxWs Low Power ConsumptionsFast BYTE and PAGE WRITE (up to 64Bytes)–1ms at V CC =4.5V for M28C64-A –3ms at V CC =4.5V for M28C64–5ms at V CC =2.7V for M28C64-xxWsEnhanced Write Detection and Monitoring:–Ready/Busy Open Drain Output –Data Polling –Toggle Bit–Page Load Timer Statuss JEDEC Approved Bytewide Pin-Out s Software Data Protections 100000Erase/Write Cycles (minimum)sData Retention (minimum):–40Years for M28C64and M28C64-xxW –10Years for M28C64-AFigure 1.Logic DiagramAI01350C13A0-A12W DQ0-DQ7V CCM28C64GEV SS8RBTable 1.Signal NamesA0-A12Address Input DQ0-DQ7Data Input /Output W Write Enable E Chip Enable G Output Enable RB Ready /Busy V CC Supply Voltage V SSGroundPDIP28(BS)SO28(MS)300mil width PLCC32(KA)281TSOP28(NS)8x 13.4mm281M28C642/24Figure 2A.DIP ConnectionsNote:1.NC =Not Connected Figure 2B.PLLC ConnectionsNote:1.NC =Not Connected2.DU =Do Not UseA1A0DQ0A7A4A3A2A6A5NC A10A8A9DQ7W A11G E DQ5DQ1DQ2DQ3V SSDQ4DQ6A12RB V CCAI01351CM28C6481234567910111213141615282726252423222120191817AI01352DN CA8A10D Q 417A0NC DQ0D Q 1D Q 2D U D Q 3A6A3A2A1A5A49W A91R B A11DQ6A 7DQ732D U V C C M28C64A 12NC D Q 5G E 25V S S Figure 2C.SO ConnectionsNote:1.NC =Not ConnectedFigure 2D.TSOP ConnectionsNote:1.NC =Not ConnectedDQ0DQ1A3A0A2A1A10E NC DQ7G DQ5V CC DQ4A9W A4RB A7AI01353CM28C648234567910111213142221201918171615DQ2V SSA6A5DQ6282726252423A11DQ31A12A8A1A0DQ0A5A2A4A3A9A11DQ7A8G E DQ5DQ1DQ2DQ3DQ4DQ6NC W A12A6RB V CC A7AI01354CM28C642812278141521V SS A10DESCRIPTIONThe M28C64devices consist of 8192x8bits of low power,parallel EEPROM,fabricated with STMicroelectronics’proprietary single polysilicon CMOS technology.The devices offer fast access time,with low power dissipation,and require a single voltage supply (5V or 3V,depending on the option chosen).The device has been designed to offer a flexible microcontroller interface,featuring both hardwareand software handshaking,with Ready/Busy,Data Polling and Toggle Bit.The device supports a 64byte Page Write operation.Software Data Protection (SDP)is also supported,using the standard JEDEC algorithm.3/24M28C64Figure 3.Block DiagramAI01355ADDRESS LATCHA6-A12(Page Address)X D E C O D ECONTROL LOGIC64K ARRAYADDRESS LATCHA0-A5Y DECODE V PP GENRESET SENSE AND DATA LATCHI/O BUFFERSRBEGWPAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLINGDQ0-DQ7Table 2.Absolute Maximum Ratings 1Note:1.Except for the rating “Operating Temperature Range”,stresses above those listed in the Table “Absolute Maximum Ratings”maycause permanent damage to the device.These are stress ratings only,and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability.Refer also to the ST SURE Program and other relevant quality -STD-883C,3015.7(100pF,1500Ω)Symbol ParameterValue Unit T A Ambient Operating Temperature -40to 125°C T STG Storage Temperature -65to 150°C V CC Supply Voltage -0.3to V CC +1V V IO Input or Output Voltage -0.6to V CC +0.6V V I Input Voltage-0.3to 6.5V V ESDElectrostatic Discharge Voltage (Human Body model)24000VM28C644/24Table 3.Operating Modes 1Note:1.0=V IL ;1=V IH ;X =V IH or V IL ;V=12V ±5%.ModeE G W DQ0-DQ7Stand-by 1X X Hi-Z Output Disable X 1X Hi-Z Write Disable X X 1Hi-Z Read 001Data Out Write 010Data In Chip EraseVHi-ZSIGNAL DESCRIPTIONThe external connections to the device are summarized in Table 1,and their use in Table 3.Addresses (A0-A12).The address inputs are used to select one byte from the memory array during a read or write operation.Data In/Out (DQ0-DQ7).The contents of the data byte are written to,or read from,the memory array through the Data I/O pins.Chip Enable (E).The chip enable input must be held low to enable read and write operations.When Chip Enable is high,power consumption is reduced.Output Enable (G).The Output Enable input controls the data output buffers,and is used to initiate read operations.Write Enable (W).The Write Enable input controls whether the addressed location is to be read,from or written to.Ready/Busy (RB).Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle.DEVICE OPERATIONIn order to prevent data corruption and inadvertent write operations,an internal V CC comparator inhibits the Write operations if the V CC voltage is lower than V WI (see Table 4A and Table 4B).Once the voltage applied on the V CC pin goes over the V WI threshold (V CC >V WI ),write access to the memory is allowed after a time-out t PUW ,as specified in Table 4A and Table 4B.Further protection against data corruption is offered by the E and W low pass filters:any glitch,on the E and W inputs,with a pulse width less than 10ns (typical)is internally filtered out to prevent inadvertent write operations to the memory.Table 4A.Power-Up Timing 1for M28C64(5V range)(T A =0to 70°C or –40to 85°C or –40to 125°C;V CC =4.5to 5.5V)Note:1.Sampled only,not 100%tested.Table 4B.Power-Up Timing 1for M28C64-xxW (3V range)(T A =0to 70°C or –40to 85°C;V CC =2.7to 3.6V)Note:1.Sampled only,not 100%tested.Symbol ParameterMin.Max.Unit t PUR Time Delay to Read Operation1µs t PUW Time Delay to Write Operation (once V CC ≥V WI )10ms V WIWrite Inhibit Threshold3.04.2VSymbol ParameterMin.Max.Unit t PUR Time Delay to Read Operation1µs t PUW Time Delay to Write Operation (once V CC ≥V WI )15ms V WIWrite Inhibit Threshold1.52.5V5/24M28C64ReadThe device is accessed like a static RAM.When E and G are low,and W is high,the contents of the addressed location are presented on the I/O pins.Otherwise,when either G or E is high,the I/O pins revert to their high impedance state.WriteWrite operations are initiated when both W and E are low and G is high.The device supports both W-controlled and E-controlled write cycles (as shown in Figure 11and Figure 12).The address is latched during the falling edge of W or E (which ever occurs later)and the data is latched on the rising edge of W or E (which ever occurs first).After a delay,t WLQ5H ,that cannot be shorter than the value specified in Table 10A to Table 10C,the internal write cycle starts.It continues,under internal timing control,until the write operation is complete.The commencement of this period can be detected by reading the Page Load Timer Status on DQ5.The end of the cycle can be detected by reading the status of the Data Polling and the Toggle Bit functions on DQ7and DQ6.Page WriteThe Page Write mode allows up to 64bytes to be written on a single page in a single go.This is achieved through a series of successive Write operations,no two of which are separated by more than the t WLQ5H value (as specified in Table 10A to Table 10C).All bytes must be located on the same page address (A12-A6must be the same for all bytes).The internal write cycle can start at any instant after t WLQ5H .Once initiated,the write operation is internally timed,and continues,uninterrupted,until completion.As with the single byte Write operation,described above,the DQ5,DQ6and DQ7lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle.Software Data Protection (SDP)The device offers a software-controlled write-protection mechanism that allows the user to inhibit all write operations to the device.This can be useful for protecting the memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected,or when power supply levels are outside their specified values).By default,the device is shipped in the “unprotected”state:the memory contents can be freely changed by the user.Once the Software Data Protection Mode is enabled,all write commands are ignored,and have no effect on the memory contents.The device remains in this mode until a valid Software Data Protection disable sequence is received.The device reverts to its “unprotected”state.The status of the Software Data Protection (enabled or disabled)is represented by a non-Figure 4.Software Data Protection Enable Algorithm and Memory WriteNote:1.The most significant address bits (A12to A6)differ during these specific Page Write operations.AI01356CWrite AAh in Address 1555hWrite 55h in Address 0AAAh Write A0h in Address 1555h SDP is setWrite AAh in Address 1555h Write 55h in Address 0AAAh Write A0h in Address 1555hPage Write (1up to 64bytes)Write to Memory When SDP is SETSDP Enable AlgorithmPage WriteTiming (see note 1)Page WriteTiming (see note 1)Write is enabledPhysical Page Write InstructionM28C646/24volatile latch,and is remembered across periods of the power being off.The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page),as shown in Figure 4.Similarly to disable the Software Data Protection,the user has to write specific data bytes into six different locations,as shown in Figure 5.This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism.When SDP is enabled,the memory array can still have data written to it,but the sequence is more complex (and hence better protected from inadvertent use).The sequence is as shown in Figure 4.This consists of an unlock key,to enable the write action,at the end of which the SDP continues to be enabled.This allows the SDP to be enabled,and data to be written,within a single Write cycle (t WC ).Software Chip EraseUsing this function,available on the M28C64but not on the M28C64-A or M28C64-xxW,the contents of the entire memory are erased (set to FFh)by holding Chip Enable (E)low,and holding Output Enable (G)at V CC +7.0V.The chip is cleared when a 10ms low pulse is applied to the Write Enable (W)signal (see Figure 7and Table 5for details).Status BitsThe devices provide three status bits (DQ7,DQ6and DQ5),and one output pin (RB),for use during write operations.These allow the application to use the write time latency of the device for getting on with other work.These signals are available on the I/O port bits DQ7,DQ6and DQ5(but only during programming cycle,once a byte or more has been latched into the memory)or continuously on the RB output pin.Data Polling bit (DQ7).The internally timed write cycle starts after t WLQ5H (defined in Table 10A to Table 10C)has elapsed since the previous byte was latched in to the memory.The value of the DQ7bit of this last byte,is used as a signalFigure 5.Software Data Protection Disable AlgorithmAI01357BWrite AAh in Address 1555h Write 55h in Address 0AAAh Write 80h in Address 1555h Unprotected StateWrite AAh in Address 1555h Write 55h in Address 0AAAh Write 20h in Address 1555h Page WriteTimingFigure 6.Status Bit AssignmentAI02815DPTBPLTSHi-ZHi-ZHi-ZHi-ZHi-ZDP TB PLTS Hi-Z DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0=Data Polling =Toggle Bit=Page Load Timer Status =High impedance7/24M28C64Table 5.Chip Erase AC Characteristics 1for M28C64and M28C64-xxW (T A =0to 70°C or –40to 85°C or –40to 125°C;V CC =4.5to 5.5V)(T A =0to 70°C or –40to 85°C;V CC =2.7to 3.6V)Note:1.Sampled only,not 100%tested.Symbol ParameterTest Condition Min.Max.Unit t ELWL Chip Enable Low to Write Enable Low G =V CC +7V 1µs t WHEH Write Enable High to Chip Enable High G =V CC +7V 0ns t WLWH2Write Enable Low to Write Enable High G =V CC +7V 10ms t GLWH Output Enable Low to Write Enable High G =V CC +7V 1µs t WHRHWrite Enable High to Write Enable LowG =V CC +7V3msthroughout this write operation:it is inverted while the internal write operation is underway,and is inverted back to its original value once the operation is complete.Toggle bit (DQ6).The device offers another way for determining when the internal write cycle is completed.During the internal Erase/Write cycle,DQ6toggles from ’0’to ’1’and ’1’to ’0’(the first read value being ’0’)on subsequent attempts to read any byte of the memory.When the internal write cycle is complete,the toggling is stopped,and the values read on DQ7-DQ0are those of the addressed memory byte.This indicates that the device is again available for new Read and Write operations.Page Load Timer Status bit (DQ5).An internal timer is used to measure the period between successive Write operations,up to t WLQ5H (defined in Table 10A to Table 10C).The DQ5line is held low to show when this timer is running (hence showing that the device has received one write operation,and is waiting for the next).The DQ5line is held high when the counter hasoverflowed (hence showing that the device is now starting the internal write to the memory array).Ready/Busy pin.The RB pin is an open drain output that is held low during the erase/write cycle,and that is released (allowed to float)at the completion of the programming cycle.Figure 7.Chip Erase AC Waveforms (M28C64and M28C64-xxW)AI01484BEGWtWLWH2tELWLtGLWHtWHRHtWHEHM28C648/24Table 6A.Read Mode DC Characteristics for M28C64and M28C64-A (5V range)(T A =0to 70°C or –40to 85°C or –40to 125°C;V CC =4.5to 5.5V)Note:1.All inputs and outputs open circuit.Table 6B.Read Mode DC Characteristics for M28C64-xxW (3V range)(T A =0to 70°C or –40to 85°C;V CC =2.7to 3.6V)Note:1.All inputs and outputs open circuit.Symbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current 0V ≤ V IN ≤V CC 10µA I LO Output Leakage Current 0V ≤V OUT ≤V CC10µA I CC1Supply Current (TTL inputs)E =V IL ,G =V IL ,f =5MHz 30mA Supply Current (CMOS inputs)E =V IL ,G =V IL ,f =5MHz25mA I CC11Supply Current (Stand-by)TTL E =V IH 1mA I CC21Supply Current (Stand-by)CMOS E >V CC -0.3V100µA V IL Input Low Voltage -0.30.8V V IH Input High Voltage 2V CC +0.5V V OL Output Low Voltage I OL =2.1mA 0.4V V OHOutput High VoltageI OH =-400µA2.4VSymbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current 0V ≤ V IN ≤V CC 10µA I LO Output Leakage Current 0V ≤V OUT ≤V CC10µA I CC1Supply Current (CMOS inputs)E =V IL ,G =V IL ,f =5MHz,V CC =3.3V 8mA E =V IL ,G =V IL ,f =5MHz,V CC =3.6V10mA I CC21Supply Current (Stand-by)CMOS E >V CC -0.3V20µA V IL Input Low Voltage -0.30.6V V IH Input High Voltage 2V CC +0.5V V OL Output Low Voltage I OL =1.6mA 0.2V CCV V OHOutput High VoltageI OH =-400µA0.8V CCV9/24M28C64Table 7.Input and Output Parameters 1(T A =25°C,f =1MHz)Note:1.Sampled only,not 100%tested.Table 8.AC Measurement ConditionsSymbol ParameterTest Condition Min.Max.Unit C IN Input Capacitance V IN =0V 6pF C OUTOutput CapacitanceV OUT =0V12pFInput Rise and Fall Times≤20ns Input Pulse Voltages (M28C64,M28C64-A)0.4V to 2.4V Input Pulse Voltages (M28C64-xxW)0V to V CC -0.3V Input and Output Timing Reference Voltages (M28C64,M28C64-A)0.8V to 2.0V Input and Output Timing Reference Voltages (M28C64-xxW)0.5V CCFigure 8.AC Testing Input Output WaveformsAI02101B4.5V to5.5V Operating Voltage 2.7V to 3.6V Operating Voltage V CC –0.3V0V0.5V CC2.4V0.4V2.0V 0.8VFigure 9.AC Testing Equivalent Load CircuitAI02102BOUTC L =100pFC L includes JIG capacitanceI OLDEVICE UNDER TESTI OHM28C6410/24Table 9A.Read Mode AC Characteristics for M28C64and M28C64-A (5V range)(T A =0to 70°C or –40to 85°C;V CC =4.5to 5.5V)Note:1.Output Hi-Z is defined as the point at which data is no longer driven.Table 9B.Read Mode AC Characteristics for M28C64(5V range)(T A =–40to 125°C;V CC =4.5to 5.5V)Note:1.Output Hi-Z is defined as the point at which data is no longer driven.SymbolAlt.ParameterTest Condit ion M28C64Unit-90-12-15MinMax MinMax MinMax t AVQV t ACC Address Valid to Output Valid E =V IL ,G =V IL 90120150ns t ELQV t CE Chip Enable Low to Output Valid G =V IL 90120150ns t GLQV t OE Output Enable Low to Output Valid E =V IL 404550ns t EHQZ 1t DF Chip Enable High to Output Hi-Z G =V IL 040045050ns t GHQZ 1t DF Output Enable High to Output Hi-Z E =V IL 040045050ns t AXQXt OHAddress Transition to Output TransitionE =V IL ,G =V IL00ns SymbolAlt.ParameterTest Condit ion M28C64Unit-12MinMax t AVQV t ACC Address Valid to Output Valid E =V IL ,G =V IL 120ns t ELQV t CE Chip Enable Low to Output Valid G =V IL 120ns t GLQV t OE Output Enable Low to Output Valid E =V IL 45ns t EHQZ 1t DF Chip Enable High to Output Hi-Z G =V IL 065ns t GHQZ 1t DF Output Enable High to Output Hi-Z E =V IL 065ns t AXQXt OHAddress Transition to Output TransitionE =V IL ,G =V ILns11/24Table 9C.Read Mode AC Characteristics for M28C64-xxW (3V range)(T A =0to 70°C or –40to 85°C;V CC =2.7to 3.6V)Note:1.Output Hi-Z is defined as the point at which data is no longer driven.SymbolAlt.ParameterTest Condit ion M28C64-xxWUnit-12-15-20-25-30MinMax Min Max Min Max Min MaxMinMax t AVQV t ACC Address Valid to Output Valid E =V IL ,G =V IL 120150200250300ns t ELQV t CE Chip Enable Low to Output Valid G =V IL 120150200250300ns t GLQV t OE Output Enable Low to Output Valid E =V IL 8080100150150ns t EHQZ 1t DF Chip Enable High to Output Hi-Z G =V IL 045050055060060ns t GHQZ 1t DF Output Enable High to Output Hi-Z E =V IL 045050055060060ns t AXQXt OHAddress Transition to Output TransitionE =V IL ,G =V IL00ns Figure 10.Read Mode AC Waveforms (with Write Enable,W,high)Note:1.Write Enable (W)=V IHAI00749BVALIDtAVQVtAXQXtGLQVtEHQZtGHQZDATA OUTA0-A12EGDQ0-DQ7tELQVHi-Z12/24Table 10A.Write Mode AC Characteristics for M28C64and M28C64-A (5V range)(T A =0to 70°C or –40to 85°C;V CC =4.5to 5.5V)Note:1.With a 3.3k Ωpull-up resistor.Symbol Alt.ParameterTest Condition M28C64Unit Min Maxt AVWL t AS Address Valid to Write Enable Low E =V IL ,G =V IH 0ns t AVEL t AS Address Valid to Chip Enable Low G =V IH ,W =V IL0ns t ELWL t CES Chip Enable Low to Write Enable Low G =V IH 0ns t GHWL t OES Output Enable High to Write Enable Low E =V IL 0ns t GHEL t OES Output Enable High to Chip Enable Low W =V IL 0ns t WLEL t WES Write Enable Low to Chip Enable Low G =V IH0ns t WLAX t AH Write Enable Low to Address Transition 50ns t ELAX t AH Chip Enable Low to Address Transition 50ns t WLDV t DV Write Enable Low to Input Valid E =V IL ,G =V IH 1µs t ELDV t DV Chip Enable Low to Input Valid G =V IH ,W =V IL1µs t ELEH t WP Chip Enable Low to Chip Enable High 50ns t WHEH t CEH Write Enable High to Chip Enable High 0ns t WHGL t OEH Write Enable High to Output Enable Low 0ns t EHGL t OEH Chip Enable High to Output Enable Low 0ns t EHWH t WEH Chip Enable High to Write Enable High 0ns t WHDX t DH Write Enable High to Input Transition 0ns t EHDX t DH Chip Enable High to Input Transition 0ns t WHWL t WPH Write Enable High to Write Enable Low 501000ns t WLWH t WP Write Enable Low to Write Enable High 50ns t WLQ5Ht BLCTime-out after last byte write (M28C64)100µs Time-out after last byte write (M28C64-A)20µs t Q5HQ5X t WC Write Cycle Time (M28C64)3ms Write Cycle Time (M28C64-A)1ms t WHRL t DB Write Enable High to Ready/Busy Low Note 1150ns t EHRL t DB Chip Enable High to Ready/Busy Low Note 1150ns t DVWH t DS Data Valid before Write Enable High 50ns t DVEHt DSData Valid before Chip Enable High50nsTable10B.Write Mode AC Characteristics for M28C64(5V range) (T A=–40to125°C;V CC=4.5to5.5V)Symbol Alt.Parameter Test ConditionM28C64Unit Min Maxt AVWL t AS Address Valid to Write Enable Low E=V IL,G=V IH0ns t AVEL t AS Address Valid to Chip Enable Low G=V IH,W=V IL0ns t ELWL t CES Chip Enable Low to Write Enable Low G=V IH0ns t GHWL t OES Output Enable High to Write Enable Low E=V IL0ns t GHEL t OES Output Enable High to Chip Enable Low W=V IL0ns t WLEL t WES Write Enable Low to Chip Enable Low G=V IH0ns t WLAX t AH Write Enable Low to Address Transition75ns t ELAX t AH Chip Enable Low to Address Transition75ns t WLDV t DV Write Enable Low to Input Valid E=V IL,G=V IH1µs t ELDV t DV Chip Enable Low to Input Valid G=V IH,W=V IL1µs t ELEH t WP Chip Enable Low to Chip Enable High50ns t WHEH t CEH Write Enable High to Chip Enable High0ns t WHGL t OEH Write Enable High to Output Enable Low0ns t EHGL t OEH Chip Enable High to Output Enable Low0ns t EHWH t WEH Chip Enable High to Write Enable High0ns t WHDX t DH Write Enable High to Input Transition0ns t EHDX t DH Chip Enable High to Input Transition0ns t WHWL t WPH Write Enable High to Write Enable Low501000ns t WLWH t WP Write Enable Low to Write Enable High50nst WLQ5H t BLC Time-out after last byte write(M28C64)100µs Time-out after last byte write(M28C64-A)20µst Q5HQ5X t WC Write Cycle Time(M28C64)3ms Write Cycle Time(M28C64-A)1mst WHRL t DB Write Enable High to Ready/Busy Low Note1150ns t EHRL t DB Chip Enable High to Ready/Busy Low Note1150ns t DVWH t DS Data Valid before Write Enable High50ns t DVEH t DS Data Valid before Chip Enable High50ns13/2414/24Table 10C.Write Mode AC Characteristics for M28C64-xxW (3V range)(T A =0to 70°C or –40to 85°C;V CC =2.7to 3.6V)Note:1.With a 3.3k Ωpull-up resistor.Symbol Alt.ParameterTest Condition M28C64-xxW Unit Min Maxt AVWL t AS Address Valid to Write Enable Low E =V IL ,G =V IH 0ns t AVEL t AS Address Valid to Chip Enable Low G =V IH ,W =V IL0ns t ELWL t CES Chip Enable Low to Write Enable Low G =V IH 0ns t GHWL t OES Output Enable High to Write Enable Low E =V IL 0ns t GHEL t OES Output Enable High to Chip Enable Low W =V IL 0ns t WLEL t WES Write Enable Low to Chip Enable Low G =V IH0ns t WLAX t AH Write Enable Low to Address Transition 100ns t ELAX t AH Chip Enable Low to Address Transition 100ns t WLDV t DV Write Enable Low to Input Valid E =V IL ,G =V IH 1µs t ELDV t DV Chip Enable Low to Input Valid G =V IH ,W =V IL1µs t ELEH t WP Chip Enable Low to Chip Enable High 1001000ns t WHEH t CEH Write Enable High to Chip Enable High 0ns t WHGL t OEH Write Enable High to Output Enable Low 0ns t EHGL t OEH Chip Enable High to Output Enable Low 0ns t EHWH t WEH Chip Enable High to Write Enable High 0ns t WHDX t DH Write Enable High to Input Transition 0ns t EHDX t DH Chip Enable High to Input Transition 0ns t WHWL t WPH Write Enable High to Write Enable Low 501000ns t WLWH t WP Write Enable Low to Write Enable High 100ns t WLQ5H t BLC Time-out after the last byte write 100µs t Q5HQ5X t WC Write Cycle Time5ms t WHRL t DB Write Enable High to Ready/Busy Low Note 1150ns t EHRL t DB Chip Enable High to Ready/Busy Low Note 1150ns t DVWH t DS Data Valid before Write Enable High 50ns t DVEHt DSData Valid before Chip Enable High50ns15/24Figure 11.Write Mode AC Waveforms (Write Enable,W,controlled)Figure 12.Write Mode AC Waveforms (Chip Enable,E,controlled)AI01126VALIDtAVWLA0-A12EGDQ0-DQ7DATA INWtWLAXtELWLtGHWLtWLDVtWHEHtWHGLtWLWH tWHWLtWHDXtDVWHRBtWHRLAI00751VALIDtAVELA0-A12EGDQ0-DQ7DATA IN WtELAXtGHELtWLELtELDVtEHGLtEHDXtDVEHRBtEHRLtELEHtEHWH16/24Figure 13.Page Write Mode AC Waveforms (Write Enable,W,controlled)Figure 14.Software Protected Write Cycle WaveformsNote:1.A12to A6must specify the same page address during each high-to-low transition of W (or E).G must be high only when W and Eare both low.tQ5HQ5XAI00752DA0-A12EGDQ0-DQ7(in)WAddr 0DQ5(out)RBAddr 1Addr 2Addr ntWLQ5HtWLWHtWHWLtWHRLByte 0Byte 1Byte 2Byte nAI01358BA0-A5EGDQ0-DQ7WtWLWHtDVWHByte 0tWHWLA6-A12tWLAXtWHDXtAVEL1555h0AAAh1555hByte 62Byte 63AAh55hA0hByte AddressPage Address17/24Figure 15.Data Polling Sequence WaveformsFigure 16.Toggle Bit Sequence WaveformsNote:1.The Toggle Bit is first set to ‘0’.AI00753CA0-A12EGDQ7WDQ7DQ7DQ7DQ7DQ7READYLAST WRITE INTERNAL WRITE SEQUENCE Address of the last byte of the Page Write instructionAI00754DA0-A12EGDQ6WREADYLAST WRITEINTERNAL WRITE SEQUENCE(1)TOGGLE18/24Table 11.Ordering Information SchemeNote:1.Available only with 120ns speed (-12),5V operating range (-blank),and -40to 85°C temperature range (-6).2.Available for the M28C64only.3.Available for the 3V range (-xxW)only.4.Not available for the 1ms write time option (-A).5.Available only for the “M28C64-12MS 3”(5V range,SO28package)Example:M28C64–A12BS6TWrite TimeOptionblank t WC =3ms at 4.5V to 5.5V;t WC =5ms at 2.7V to 3.6V TTape and Reel PackingA 1t WC =1ms at 4.5V to 5.5VSpeedTemperature Range 90290ns 10°C to 70°C 12120ns 6–40°C to 85°C 15150ns 3–40°C to 125°C 5203200ns 253250ns 303300nsPackage BSPDIP28Operating Voltage KA PLCC32blank 4.5V to 5.5V MS SO28(300mil width)W 42.7V to3.6VNSTSOP28(8x 13.4mm)ORDERING INFORMATIONDevices are shipped from the factory with the memory content set at all ‘1’s (FFh).The notation used for the device number is as shown in Table 11.For a list of available options (speed,package,etc.)or for further information on any aspect of this device,please contact your nearest ST Sales Office.Figure17.PDIP28(BS)Note: 1.Drawing is not to scale.PDIPA2A1ALB1B e1DSE1EN1CαeAeBD2Table12.PDIP28-28pin Plastic DIP,600mils widthSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 3.94 5.080.1550.200A10.38 1.780.0150.070A2 3.56 4.060.1400.160B0.380.560.0150.021B1 1.14 1.780.0450.070C0.200.300.0080.012D34.7037.34 1.366 1.470E14.8016.260.5830.640E112.5013.970.4920.550e1 2.54––0.100––eA15.2017.780.5980.700L 3.05 3.820.1200.150S 1.02 2.290.0400.090α0°15°0°15°N282819/2420/24Table 13.PLCC32-32lead Plastic Leaded Chip Carrier,rectangularSymbolmminches Typ.Min.Max.Typ.Min.Max.A 2.54 3.560.1000.140A1 1.52 2.410.0600.095A2–0.38–0.015B 0.330.530.0130.021B10.660.810.0260.032D 12.3212.570.4850.495D111.3511.560.4470.455D29.9110.920.3900.430E 14.8615.110.5850.595E113.8914.100.5470.555E212.4513.460.4900.530e 1.27––0.050––F 0.000.250.0000.010R 0.89––0.035––N 3232Nd 77Ne 99CP0.100.004Figure 18.PLCC (KA)Note: 1.Drawing is not to scale.PLCCD NeE1E1ND1NdCPBD2/E2eB1A1AR0.51(.020)1.14(.045)F A2。

多功能编程器极品版CZ多功能编程器极品版，基于LZ-A编程器的升级版本，不需要51适配器的多功能编程器,写51系列芯片的操作变得更简单、更直接、更稳定。

操作省时省力。

适合烧写各类常用的存储器、51、PIC等系列单片机的编程，同时还适合BIOS玩家烧写各种常见的BIOS芯片。

接插件特色：3个非常养眼的万能ZIF40IC座、漂亮的彩色跳线帽，非常醒目。

东西好不好，只需要看看就知道了。

零件的特色：DC-DC升压部分采用了高成本的线绕电感，VPP编程电压更稳定。

没有采用色环或豆状电感，不会出现豆状电感在写27系列容易烧的问题。

所有的电阻均为高精度金属膜电阻。

集成的IC：全部为德州、摩托罗拉、菲利浦等大厂的集成电路，所有的IC都配有集成电路插座。

布局的特色：VPP高压源电路、三极管功率控制电路都集中在电源VCC附近，抗干扰能力更好。

以往的经验告诉我们，VCC、VPP和开关三极管的距离越近，抗干扰的能力就越强。

电源的设计：USB取电、设有外接电源专用接口，双电源接口之见可以自动切换，支持外部其他标准5V电源的接入，省时省力。

产品的工艺：焊接采用一如既往的波峰焊接工工艺。

PCB电路板：PCB电路板由专业大厂制作，PCB全部采用精致的覆铜设计，绝非裸线板。

产品的定位：高成本精心打造多功能编程器中的高级精品,不求市场占有率，一心给同志们打造多功能编程器中的“劳斯莱斯”。

CZ多功能编程器主机的外观多功能BIOS编程器支持的芯片程器可以支持最新Intel810、815、845主板上使用的N82802AB、SST49LF002、SST49LF004等3.3V电压的芯片，也就是说，目前几乎所有主板上的BIOS芯片，多功能BIOS编程器都可以支持，真正是一款性价比较高的编程器。

多功能编程器程序的跳线设置在多功能编程器上，共有三组跳线，用来设置不同类型的芯片，共具体说明如下：第一组跳线：PCB上的标号为J1和J2用来设置2732、2716、2816、I28F001、AT29C256几个特殊芯片。

AT28C64B 64Kbit,并行EEPROMs 存储器AT28C64B 器件操作(1)ATMEL 爱特梅尔AT28C64B 程序存储器芯片读操作ATMEL 爱特梅尔AT28C64B 程序存储器芯片读操作访问就像使用静态RAM 一样,当CE 和OE 为低电平,WE 为高电平,由地址引脚上电平决定的存储单元中的存储的数据就被读出。

无论何时CE 或OE 为高电平时,AT28C64B 输出引脚上都呈高阻状态。

AT28C64B 这种双信号控制机制给设计者防止总线冲突带来灵活性。

(2)ATMEL 爱特梅尔AT28C64B 程序存储器芯片后备状态CE 信号是芯片选择控制信号,实际上同时也作为电源控制信号。

当其为高电平时,ATMEL 爱特梅尔AT28C64B 程序存储器芯片就进入低功耗后备状态。

这时ATMEL 爱特梅尔AT28C64B 程序存储器芯片输出呈高阻状态,并与OE 信号无关。

(3)ATMEL 爱特梅尔AT28C64B 程序存储器芯片数据保护为了确保数据的完整性和安全性,持别是在上电和掉电过渡过程中,可以用以下方法实现数据保护：①利用内部检测电路对电源电压Vcc 进行检测,当ATMEL 爱特梅尔AT28C64B 程序存储器芯片检测到的电压低于规定的阂值时,AT28C64B 就禁止内部非易失性编程操作的初姑化。

当达到阂值电压时,AT28C64B 芯片在允许字节写入之前将自动输出5阳的定时脉冲。

②ATMEL 爱特梅尔AT28C64B 程序存储器芯片片内有一个丽信号滤波电路,可以防止而信号负脉冲从初姑化到写入周期所持续的时间小于10ns。

③ATMEL爱特梅尔AT28C64B程序存储器芯片在上电和掉电期间,通过保持WE或CE 为高电平,或者OE为低电乎都可以封锁字节写入周期。

(4)ATMEL爱特梅尔AT28C64B程序存储器芯片写操作把数据写入AT28C64B芯片类似于静态RAM的操作,当OE为高电平、WE或CE为低电平时,相对应的CE或WE信号为低电平,就对字节写入操作进行韧始化。

一.实验设备和运行环境在教学计算机中，选用静态存储器芯片实现内存储器，包括唯读存储区（ROM，存放监控程序等）和随读写存储区（RAM）两部分，每个存储器芯片提供8位数据，用2个芯片组成16位长度的内存字。

6个芯片被分成3组，其地址空间分配关系是：0-1777h用于第一组ROM，固化监控程序；2000-2777h 用于RAM，保存用户程序和用户数据，其高端的一些单元作为监控程序的数据区；第二组ROM的地址范围可以由用户选择，主要用于完成扩展内存容量（存储器的字、位扩展）的教学实验。

内存储器和串行接口线路的组成如下图所示。

地址总线的低13位送到ROM芯片的地址线引脚（RAM芯片只用低11位），用于选择芯片内的一个存储字，地址总线的高3位通过译码器产生8个片选信号。

存储器16位的数据线连接到数据总线，并通过双向三态门电路74LS245与CPU 一侧的内部总线IB相连接。

这里用到3个译码器电路，其中一片74LS138译码器芯片接收地址总线最高3位地址信息，以产生内存芯片的8个片选信号，用于确定哪一个空间范围的内存区可以读写。

另外一片74LS138译码器芯片接收地址总线低位字节的最高4位地址信息（最高一位恒定为1），以产生接口芯片的8个片选信号用于选择哪一个接口电路可以读写。

一片74LS139双二-四译码器芯片接收控制器送来的3位控制信号MIO、REQ、WE，当这3位信号组合为000、001、010、011、1××时，译码器将产生写内存操作、读内存操作、写接口操作、读接口操作、内存和接口芯片都无读写操作的控制命令。

可以选用2片58C65 ROM（电可擦出的EPROM器件）芯片扩展8K字的存储空间，既可以通过专用的编程设备向芯片写入相应的数据，也可以通过写内存的指令向芯片的指定单元写入16位的数据，只是每一次的写操作需要占用几百个微秒的时间才能完成。

串行接口芯片的8位数据线引脚连接到数据总线DB的低位字节，它与CPU 之间每次交换8位信息，属于并行操作关系。

西北农林科技大学信息工程学院计算机组成原理实习报告班级信息管理与信息系统年级 11级2班姓名刘佳学号 2011013316实验一基础汇编语言程序设计实验目的1．学习和了解TEC-XP教学实验系统监控命令的用法；2．学习和了解TEC-XP教学实验系统的指令系统；3．学习简单的TEC-XP教学实验系统汇编程序设计。

实验内容1．学习联机使用TEC-XP教学实验系统和仿真终端软件PCEC。

2．使用监控程序R命令显示／修改寄存器内容、D命令显示存储器内容、E命令修改存储器内容；3．使用A命令写一小段汇编程序，U命令反汇编刚输入的程序，用G命令连续运行该程序，用T、P命令单步运行并观察程序单步执行情况。

实验步骤1．用R命令查看寄存器内容或修改寄存器的内容1）在命令行提示符状态下输入：R↙；显示寄存器的内容注：寄存器的内容在运行程序或执行命令后会发生变化。

2）在命令行提示符状态下输入：R R0↙；修改寄存器R0的内容，被修改的寄存器与所赋值之间可以无空格，也可有—个或数个空格主机显示：寄存器原值：_在后面输入新的值0036再用R命令显示寄存器内容，则R0的内容变为0036。

2．用D命令显示存储器内容在命令行提示符状态下输入：D 2000↙会显示从2000H地址开始的连续128个字的内容；连续使用不带参数的D命令，起始地址会自动加128（即80H）。

3．用E命令修改存储器内容在命令行提示符状态下输入：E 2000↙屏幕显示：2000 地址单元的原有内容：光标在此闪烁等待输入输入0000依次改变地址单元2001~2005的内容为：1111 2222 3333 4444 5555注意：用E命令连续修改内存单元的值时，每修改完—个，按一下空格键，系统会自动给出下一个内存单元的值，等待修改；按回车键则退出E命令。

4．用D命令显示这几个单元的内容D 2000↙可以看到这六个地址单元的内容变为0000 1111 2222 3333 4444 5555。

EEPROM实验说明一、实验内容一，按照实验教程的要求，完成在文件缓冲区第1行输入16个字形码，实验箱数码管上分别显示0、1、2、……e、F等十六个字符。

实验步骤如下：1.数据下载：⑴．将实验箱左下角(绿色小盒子下边)的拨动开关置于左侧编程方式。

⑵．双击桌面TopWin6 图标—〉弹出TopWin Ver6.33T窗口。

⑶．选择器件：在主菜单“操作”栏中点击“选择器件”，弹出TOP0窗口，选择芯片类型“电擦除存储器”—〉选择芯片公司“ATMEL”—〉选择芯片型号“AT28C64B”—〉确认。

或者点击“选择芯片的型号”图标，弹出sellecte chip窗口，点击“ALL”—〉点击“ATMEL”—〉点击“AT28C64B”—〉确定。

⑷．在主菜单“操作”栏中点击“擦除器件”或者点击“擦除器件”图标。

⑸．在文件缓冲区第1行，用鼠标点亮第一个FF，将实验教程中的编程数据（八段共阴字形码）共计16个，去掉前面的0和后面的H，如FD、61、DB、F3 …从左至右依次正确输入。

⑹. 在主菜单“操作”栏中点击“写器件”—〉点击“校对”—〉点击“读器件”。

或者点击“写器件”图标—〉点击“比较器件与缓冲区数据”图标—〉点击“读器件中内容到缓冲区”图标。

2.硬件电路接线。

⑴.将实验箱左下角(绿色小盒子下边)的拨动开关置于右侧电路方式，此时开关右边的发光二极管亮。

⑵.实验连线：将芯片的地址输入端A3、A2、A1、A0分别接4个开关；数据输出端O7、O6…O1、O0分别接共阴八段数码管的a、b…g、h(Dp)端，其他管脚悬空（实际上电路板下面已将其他管脚连线）。

⑶.打开实验箱电源（在实验箱后面）。

3.实验结果：在开关上改变EEPROM的地址输入0000~1111，八段共阴数码管上分别显示0、1、2、……e、F等十六个字符。

二、实验内容二，完成在文件缓冲区第n行（n=座位号+50）输入16个字形码，实验箱数码管上分别显示0、1、2、……e、F等十六个字符。

Features•Fast Read Access Time – 150 ns •Automatic Page Write Operation –Internal Address and Data Latches for 64 Bytes •Fast Write Cycle Times–Page Write Cycle Time: 10 ms Maximum –1 to 64-byte Page Write Operation •Low Power Dissipation –40 mA Active Current–100 µA CMOS Standby Current•Hardware and Software Data Protection•DATA Polling and Toggle Bit for End of Write Detection •High Reliability CMOS Technology –Endurance: 100,000 Cycles –Data Retention: 10 Years •Single 5V ± 10% Supply•CMOS and TTL Compatible Inputs and Outputs •JEDEC Approved Byte-wide Pinout•Commercial and Industrial Temperature RangesDescriptionThe AT28C64B is a high-performance electrically-erasable and programmable read only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.Manufactured with Atmel ’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 µA.Pin ConfigurationsPin Name Function A0 - A12Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7Data Inputs/Outputs NC No Connect DCDon ’t Connect PDIP , SOIC T op ViewTop ViewPLCC Top ViewNote:PLCC package pins 1 and 17 are DON ’T CONNECT.(continued)The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components.The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched,freeing the address and data bus for other operations. Fol-lowing the initiation of a write cycle, the device will automat-ically write the latched data using an internal control timer.ING of I/O 7. Once the end of a write cycle has been detected, a new access for a read or write can begin.Atmel ’s AT28C64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protec-tion mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.Block DiagramAbsolute Maximum Ratings*Temperature Under Bias................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityStorage Temperature.....................................-65°C to +150°C All Input Voltages (including NC Pins)with Respect to Ground...................................-0.6V to +6.25V All Output Voltageswith Respect to Ground.............................-0.6V to V CC + 0.6V Voltage on OE and A9with Respect to Ground...................................-0.6V to +13.5VAT28C64B Device OperationREAD: The AT28C64B is accessed like a Static RAM. at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-line control gives designers flexibility in preventing bus con-tention in their systems.BYTE WRITE: A low pulse on the WE or CE input with CE The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising will automatically time itself to completion. Once a pro-gramming operation has been initiated and for the duration of t WC, a read operation will effectively be a polling operation.PAGE WRITE: The page write operation of the AT28C64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150µs (t BLC) of the previous byte. If the t BLC limit is exceeded, the AT28C64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For tion, A6 to A12 must be the same.The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle.TOGGLE BIT:provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.DATA PROTECTION: If precautions are not taken, inad-vertent writes may occur during transitions of the host sys-tem power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.HARDWARE DATA PROTECTION: Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a) V CC sense – if V CC is below 3.8V (typi-cal), the write function is inhibited; (b) V CC power-on delay – once V CC has reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a write; (c)write inhibit –inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C64B. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP disabled.SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the “Software Data Protection Algorithm” diagram in this datasheet). After writ-ing the 3-byte command sequence and waiting t WC, the entire AT28C64B will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28C64B by preceding the data to be written by the same 3-byte command sequence used to enable SDP.Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device. However, for the duration of t WC, read operations will effectively be poll-ing operations.DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array.元器件交易网Notes:1.X can be V IL or V IH .2.Refer to the “AC Write Waveforms ” diagrams in this datasheet.3.V H = 12.0V ± 0.5V .DC and AC Operating RangeAT28C64B-15AT28C64B-20AT28C64B-25OperatingTemperature (Case)Com.0°C - 70°C 0°C - 70°C 0°C - 70°C Ind.-40°C - 85°C -40°C - 85°C -40°C - 85°C V CC Power Supply5V ± 10%5V ± 10%5V ± 10%Operating ModesMode CE OE WE I/O Read V IL V IL V IH D OUT Write (2)V IL V IH V IL D IN Standby/Write Inhibit V IH X (1)X High ZWrite Inhibit X X V IH Write Inhibit X V IL X Output Disable X V IH XHigh Z Chip Erase V ILV H (3)V IL High ZDC CharacteristicsSymbol Parameter ConditionMinMax Units I LI Input Load Current V IN = 0V to V CC + 1V 10µA I LO Output Leakage Current V I/O = 0V to V CC10µA I SB1V CC Standby Current CMOS CE = V CC - 0.3V to V CC + 1V Com., Ind.100µA I SB2V CC Standby Current TTL CE = 2.0V to V CC + 1V 2mA I CC V CC Active Current f = 5 MHz; I OUT = 0 mA40mA V IL Input Low Voltage 0.8V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 2.1 mA 0.40V V OHOutput High VoltageI OH = -400 µA2.4V元器件交易网AT28C64BAC Read Waveforms (1)(2)(3)(4)Notes:1.ACC - t CE after the address transition without impact on t ACC .2.CE - t OE CE or by t ACC - t OE after an address changewithout impact on t ACC .3.t DF is specified from OE or CE whichever occurs first (C L = 5 pF).4.This parameter is characterized and is not 100% tested.Input Test Waveforms and Measurement LevelOutput Test LoadNote:1.This parameter is characterized and is not 100% tested.AC Read CharacteristicsSymbol ParameterAT28C64B-15AT28C64B-20AT28C64B-25Units MinMax MinMax MinMax t ACC Address to Output Delay 150200250ns t CE (1)CE to Output Delay 150200250ns t OE (2)OE to Output Delay 0700800100ns t DF (3)(4)CE or OE to Output Float 050055060ns t OHOutput Hold from OE, CE or Address, whichever occurred first00nsR F Pin Capacitancef = 1 MHz, T = 25°C (1)Symbol Typ Max Units Conditions C IN 46pF V IN = 0V C OUT 812pFV OUT = 0V元器件交易网AC Write WaveformsWE ControlledAC Write CharacteristicsSymbol ParameterMin MaxUnits t AS , t OES Address, OE Setup Time 0ns t AH Address Hold Time 50ns t CS Chip Select Setup Time 0ns t CH Chip Select Hold Time 0ns t WP Write Pulse Width (WE or CE)100ns t DS Data Setup Time 50ns t DH , t OEHData, OE Hold Timens元器件交易网AT28C64BPage Mode Write Waveforms (1)(2)Notes: 1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE).2.OE must be high only when WE and CE are both low.Chip Erase Waveformst S = t H = 1 µsec (min.)t W = 10 msec (min.)V H = 12.0 ± 0.5VPage Mode CharacteristicsSymbol Parameter MinMax Units t WC Write Cycle Time10ms t WC Write Cycle Time (option available; contact Atmel sales office for ordering part number)02ms t AS Address Setup Time 0ns t AH Address Hold Time 50ns t DS Data Setup Time 50ns t DH Data Hold Time 0ns t WP Write Pulse Width 100ns t BLC Byte Load Cycle Time 150µs t WPHWrite Pulse Width High50ns元器件交易网Software Data Protection Enable Algorithm (1)Notes for software program code:1.Data Format: I/O7 - I/O0 (Hex);Address Format: A12 - A0 (Hex).2.Write Protect state will be activated at end ofwrite even if no other data is loaded.3.Write Protect state will be deactivated at end ofwrite period even if no other data is loaded.4. 1 to 64 bytes of data are loaded.Software Data Protection Disable Algorithm (1)Software Protected Write Cycle Waveforms (1)(2)Notes: 1.A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered.2.元器件交易网AT28C64BNotes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics ”.Notes:1.These parameters are characterized and not 100% tested.2.See “AC Read Characteristics ”.Toggle Bit Waveforms (1)(2)(3)Notes: 1.2.Beginning and ending state of I/O6 will vary.3.Any address location may be used but the address should not vary.Data Polling Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 0ns t OEH OE Hold Time 0ns t OE OE to Output Delay (2)ns t WR Write Recovery TimensToggle Bit Characteristics (1)Symbol Parameter Min TypMaxUnits t DH Data Hold Time 10ns t OEH OE Hold Time 10ns t OE OE to Output Delay (2)ns t OEHP OE High Pulse 150ns t WR Write Recovery Time0ns元器件交易网元器件交易网AT28C64BNote:1.See “Valid Part Numbers ” table below.Ordering Information (1)t ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby 150400.1A T28C64B-15JC A T28C64B-15PC A T28C64B-15SC A T28C64B-15TC 32J 28P628S 28T Commercial (0°C to 70°C)A T28C64B-15JI A T28C64B-15PI A T28C64B-15SI A T28C64B-15TI32J 28P628S 28T Industrial (-40°C to 85°C)200400.1A T28C64B-20JC A T28C64B-20PC A T28C64B-20SC A T28C64B-20TC 32J 28P628S 28T Commercial (0°C to 70°C)A T28C64B-20JI A T28C64B-20PI A T28C64B-20SI A T28C64B-20TI32J 28P628S 28T Industrial (-40°C to 85°C)250400.1A T28C64B-25JC A T28C64B-25PC A T28C64B-25SC A T28C64B-25TC 32J 28P628S 28T Commercial (0°C to 70°C)A T28C64B-25JI A T28C64B-25PI A T28C64B-25SI A T28C64B-25TI32J 28P628S 28TIndustrial (-40°C to 85°C)Valid Part NumbersThe following table lists standard Atmel products that can be ordered.Device Numbers Speed Package and Temperature Combinations AT28C64B 15JC, JI, PC, PI, SC, SI, TC, TI AT28C64B 20JC, JI, PC, PI, SC, SI, TC, TI AT28C64B 25JC, JI, PC, PI, SC, SI, TC, TI AT28C64B–WDie ProductsReference Section: Parallel EEPROM Die Products元器件交易网AT28C64B12Packaging Information© Atmel Corporation 1999.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard war-ranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems.Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.Terms and product names in this document may be trademarks of others.Atmel HeadquartersAtmel OperationsCorporate Headquarters2325 Orchard Parkway San Jose, CA 95131TEL (408) 441-0311FAX (408) 487-2600EuropeAtmel U.K., Ltd.Coliseum Business Centre Riverside WayCamberley, Surrey GU15 3YL EnglandTEL (44) 1276-686-677FAX (44) 1276-686-697AsiaAtmel Asia, Ltd.Room 1219Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong KongTEL (852) 2721-9778FAX (852) 2722-1369JapanAtmel Japan K.K.9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTEL (81) 3-3523-3551FAX (81) 3-3523-7581Atmel Colorado Springs1150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TEL (719) 576-3300FAX (719) 540-1759Atmel RoussetZone Industrielle13106 Rousset Cedex FranceTEL (33) 4-4253-6000FAX (33) 4-4253-6001Fax-on-DemandNorth America:1-(800) 292-8635International:1-(408) 441-0732e-mailliterature@Web Site BBS1-(408) 436-43090270H –12/99/xM。

三菱服务器使用说明书一、软件主界面介绍启动密码：1234上方菜单栏为功能的快捷菜单，在功能操作中是功能的快捷按钮和命令按钮。

使用说明:进入软件后默认为数据读取模式1 数据页读取模式在段地址输入框，偏地址输入框输入您要读取的RAM内存数据及程序ROM数据的偏址及段址。

点击读操作开始读取偏地址开始的256个数据。

2段读取模式和数据段读取模式分为保存模式和普通模式选中段读取模式，此时读范围输入框由灰色变为黑色，这时在偏地址中输入要读取数据段的起始偏地址，在读范围中输入结束地址，点击读取开始读取数据。

如果没有选中保存模式，此时在数据显示框中会显示读取的数据。

如果选中保存模式，将不显示数据但此时数据保存按钮将为可用状态。

在数据读取完成后，点击数据保存会出现数据保存框输入您要保存数据的文件名如GPS-3-DATA.BIN点击确定。

数据将会保存在软件所在的文件夹中。

可以方便的保存电梯的功能程序规格表数据，方便对程序进行比较查找。

二、电梯输入端子状态界面功能说明：可以实时的查看电梯主板各输入端子的状态。

使用方法：启动软件后点击菜单栏的电梯IO状态即进入查看界面。

您需要做的只是输入当前所连接的电梯型号代码。

电梯型号代码说明：1代表HOPE全系列，GPS-I ,GPS-II, NOV A 全系列，凌云全系列。

2 代表GPS -3三、TSD辅助调整目前该功能支持HOPE全系列，GPS-I ,GPS-II, NOV A 全系列，凌云全系列。

使用方法：1 进入功能界面2 将电梯开到次底层及次高层，打到检修状态。

3 将MON调到4，然后开慢车直到撞限位，在撞限位后软件会自动计算同方向的减速开关误差。

分别测试上下方向的减速开关。

四、电梯显示更改操作界面该功能提供了快捷方便的显示更改操作。

电梯型号代码说明：HOPE1及2，GPS-I ,GPS-II, NOV A 全系列请选择1 ；最新的凌云，及HOPE3 包括凌杰选择3 ；GPS-3 及无机房选择2 ；进入软件后第一步先选择正确的电梯型号，输入电梯型号代码。