第30卷 第2期2007年4月电子器件Ch inese Jou r nal Of Elect ro n DevicesVol.30 No.2Ap r.2007CMOS L N A f or Homodyne UHF RF ID Receiver 3Z H A N G Ru n 2x i 1,S H I Chu n 2qi 1,CU I J i a n 2mi n g 1,L A I Zon g 2shen g 1,CAO Fen g 2w en21.I nst i tut e of Microel ect ronics Ci rcuit &S ys tem ,East Chi na Normal Universit y ,S hangh ai 200062;2.Dept of Microelect ronics ,S uzhou Vocati onal Uni versi t y ,S uzhou J i angs u 215000Abstract :A 1.2V 900M Hz L NA for U HF R F I D (Ult ra High Frequency Radio Frequency Identifica tion )system s implement ed i n TSMC 0.18μm st andard CMOS process ha s been proposed.The ci rcui t ry i s ad 2vise d based on t he feat ures of t he RF ID application.This induct ivel y degenera ted com mon 2source low noi se amplifier p rovides a forward gai n of 20.8dB wit h a noi se figure of onl y 1.1dB whil e eac h stage drawi ng a 2bout 10mA current f rom 1.2V supply volt age.The spurious t hree stage s st r uct ure which reuses t he bias current guara nt ees a reverse i solat ion about -87dB.This LN A achieves IP3of -8.4dB m ,1dB compres 2sion of -18dB m.K ey w or ds :receiver ;U H F R FID system ;homodyne ;CMOS low noi se amplifierEEACC :1220;2570F零中频UHF RFID 接收机中的低噪声放大器设计3张润曦1,石春琦1,崔建明1,赖宗声1,曹丰文21.华东师范大学微电子电路与系统研究所,上海200062;2.苏州职业大学电子系,江苏苏州215000收稿日期:2006204211基金项目:上海市科委项目资助(AM0513);苏州学院资助(06019)作者简介:张润曦(19782)男,博士生,华东师范大学微电子与电路系统研究所,苏州学院助教,主要研究方向为模拟集成电路设计,51041202035@st ;石春琦(2),博士生,华东师范大学微电子与电路系统研究所,研究方向为模拟集成电路设计;崔建明(2),博士生,华东师范大学微电子与电路系统研究所,研究方向为模拟集成电路设计;赖宗声(2),博导,教授,华东师范大学微电子与电路系统研究所,研究方向为集成电路设计;曹丰文(2),教授,苏州学院电子工程系,研究方向为集成电路设计摘 要:介绍了一个基于0.18μm 标准CMOS 工艺,可用于零中频U HF RF ID (射频识别)接收机系统的900M Hz 低噪声放大器.根据射频识别系统的特点与要求对低噪放的结构、匹配、功耗和噪声等问题进行了权衡与分析,仿真结果表明:在1.2V 供电时放大器可以提供20.8dB 的前向增益,采用源端电感实现匹配并保证噪声性能,噪声系数约为1.1dB ,放大器采用电流复用以降低功耗,每级电路从电源电压上抽取10mA 左右的工作电流,并使反向隔离度达到-87dB.放大器的IP3为-8.4dB m ,1dB 压缩点为-18dBm.关键词:接收机;超高频段射频识别系统;零中频;互补金属氧化物半导体低噪声放大器中图分类号:TN 722 文献标识码:A 文章编号:100529490(2007)022******* The application pot enti alit y of low cost and low powe r di ssipation U HF R FID syst em [1](e.g.,t ransport ation ,retail )has mot ivate d t he investi ga 2t ion of low 2noi se f ront end t echni que s i n st anda rd CMOS p rocesses.Rece nt work ha s demonst rat edt he viabilit y of CMOS RF f ront end i n 900MHz and hi gher f reque ncies [227]Typical U HF R FID receiver s ’f ront 2end are show n i n Fi gure 1.Bot h can opera te properl y wit hDS B 2AS K signal regul ated by U HF EPC global8.protocol.In Fig.1(a ),het erodyne arc hi tect ure exhi bi t s a serious i mage rej ection problem ,com 2monly ,i ma ge rejection filt ers realized as a pa ssive and exter nal component and not accept able for monol it hic i nt egration.The homodyne arc hi tect ure i n Fig.1(b )offers a n important advantage over a heterodyne count erpart.The probl em of image re 2jection is circumvent ed for zero IF.But ,sim ult a 2neousl y ,LNA in t hi s archit ect ure requi res addit ive performance ,such as hi gher reverse i solation.(a )Heterodyne receiver f ront 2e nd(b )Homodyne receiver f ro nt 2endFig.1 TWO receive r architecture s1 L NA Design and AnalysisThe primary goal i n t he desi gn of an L NA i s t o achieve lowest noi se wi t h reaso nable power di s 2sipation ,of course ,low suppl y vol tage and hi gh rever se isol ation peculiar to R FID application.Inorder to match wit h a n off 2chip 50Ωreal source i mpedance ,t here a re t hree usual mea ns ,i. e.,fee dback ,paral lel 50Ωresi stor and i nduct ive source degeneration.The drawback of feedback to 2pology i s t he rel atively low volt age gain at hi gh frequencies for t he bandwidt h limit ation at out put node.Parallel 50Ωresist or i nt roduce s a bound of 3dB on t he achievable noi se fi gure for t he t hermal noise of t he re si stor.In t his paper ,we employ t he i nduct ive source degeneration to provi de a mat cha 2bl e real part .Neglecti ng t he gat e 2drai n and source 2bul k capaci ta nce ,accordi ng to Fi g.2,we can writ eZ =(L +L )++L I ,f y 2nat e at t he f requency of int erest.Therefore ,an on 2chip L C mat ching net work may be needed.Fig.2 Inp ut stageThe noise figure ca n be appro ximat ed i n t he Fig.3,noise cont ri buted by second and followi ng st ages can be ignored when t he fi rst st age ’s gai n is enough.Several noi se sources will i nfl uence t henoi se figure of t he L NA.The source re si st ance ,i nducti ve resi st ance ,gate resi stance and cha nnel t hermal noi se cur re nt are i mportant.Amo ng t he se sources ,t he t hermal noi se is t he most significant.Accordi ng to ref.[8],4k Tγg m i s a ble to accepta bly p redict t he t hermal noi se of MOSFE T in sat ura 2tion.Experi ment al st udies have shown t hat γmay be as high a s 2to 3for short cha nnel devices oper 2at ing i n sat uration.The n we writ eI 2n =4kT γg m1Wi t h t he circuit ill ust rat ed in Fig.3,t he e 2quivalent t ransconductance of t he fir st st age ca n be wri tt en as [9]G eq =g m1Q in =g m1ωC gs (R s +ωT L s )=ωT2ωR s Fig.3 Equivalent circ uit for n oise figure calc ula tingwhere we have used t he app roxi ma tion t hat ωTi s t he rat io of g m1t o C gs .Q in i s t he effective i nput Q value of t he i nput sta ge.We can note t he ove rall t ransconductance is i ndepe ndent of t he device i nner I 2ff y T f y y154第2期张润曦,石春琦等:零中频U HF R FID 接收机中的低噪声放大器设计8i n s g s 1C gs sg m s C gsn practi ce t he i rst t wo t erm s ma not re so t ransconductance.t happens w hen t he two com peti ng e ect s cancel p reci sel .he noi se i gure is achi eved b t he tot al output noise power divided bt he noi se power at t he output onl y due to t he i nput noise power.We have[N F ]=1+R l R s +R gR s+R s g m1ωωT 2w here neglect ing t he cont ri bution of subse 2quent st ages.Obviously ,t he noi se figure will i m 2prove wi t h decreasing t he widt h of t he device.Of course ,it i s helpful to use new t echnology whilet he noi se fi gure is p roportional to 1/ω2T .F ig.4 C omplete LNA schematic with on 2chip in put matching2 Discussion &Simulat ion ResultsA complet e circuit is shown i n t he Fi g.4.In t hi s circuit ,bot h M 1and M 2operat e a s common 2source stage s ,but t hey share sa me bias current.It i s significant t o save power di ssipat ion by t he reuse of t he bias current.A not her com mon source st age i s followed to dri ve a 50Ωload.There are spuri 2ous t hree stage s in t his circuit.The signal ampli 2fied by M 1i s coupl ed to t he gate of M 2by M 1while t he source of M 2i s bypassed by C 2.In practice ,parasitic bot tom 2plat e capacit ance of C 1may limit t he gain of LNA.M 2plays a very i mportant role i n t hi s circuit by improving t he reverse i solation.It i s meani ngf ul t o lower t he L O unexpecta ble lea kage produced by t he fol lowing mi xer ,which will int ro 2duce unnecessary interf ere nce for Int errogators.To opt imize t he noi se performance of L NA ,we at t ai n noi se figure i n a way [9]t hat t ake s power di ssipation i nto account.According to t hi s powe r 2const rai ned noi se opti mi zation ,we achieve t he op 2f M T M t he i np ut device.The choice i s com mon and some 2what arbi t rary.In fact ,i t i s t he consequence of suppressi ng t he Miller effect and reduci ng t he de 2vice ’s own i nt ernal noi se.At a bias current of 10mA ,t he value of ωT i s achieved.In order to gener 2at e a real part of 50Ω,L s m ust be 3.5n H.Reso 2nati ng agai nst t he capacit ance of C gs at 900MHz requi re s a t ot al induct ance of about 20n H ,so t hatL g i s app roximat ely 16.5n H.The input and out 2p ut resonances are commonly set equal to each ot h 2er ,but an offset ca n be advantageous to yield a broader and flat t er response.An LNA based on t his topology ha s been sim 2ulat ed i n ADS wit h TSMC _CM018RF proce ss.The M 1st age is biased by an i np ut bia s net work.The re si stor R B I A S i s chosen e nough t hat it s equiva 2le nt noise cur re nt i s small eno ugh to be ignore d.In t hi s 50Ωsystem ,several kilohm is adequat e.The gat e i nduct ance L g is somewhat la rge.A planarspi ral of t his value would consume t re me ndous di e area and it s lossi ness woul d al so de grade t he noi sefigure significant ly.We realize only part of t he t o 2tal wi t h a bondwire and t he rest wit h an ext ernal i nductor.Excell ent repeata bili t y is possi ble for t he rel ative dimensional st abilit y.The i nductor L s is realized as ei t her a bondwi re of 3.5mm le ngt h or as an on 2chip planar spiral.A spiral inductor L d act s as t he load i nducta nce to resonat e a gai nst t he drain capacit ance of M 2a nd gate capaci tance of M 3.An open 2drain st age drives a 50Ωload.Aft er con 2st ructi ng ,we found t hat t he i nput re sona nce hap 2pened in a hi gher f requency ot her t han t he maxi 2mum gai n ,an on 2c hip L C net work was used to ad 2j ust t he i nput re sona nce.Usi ng t hi s ci rcuit ,t he si mulated forward gain of LNA was about 20.8dB and noi se figure was 1.1dB wit h 24mW power dissipation at 1.2V supply volt 2age.About half of the total power (10.8mW )is used i n t he output stage and able to be reduced by decrea 2sing t he size of M 3wit hout degrading t he noise per 2formance.T o the aut hors ’knowledge ,t he rever se i 2solation about -87dB i s t he hi ghe st one reported f MOS f U F 254电 子 器 件第30卷8t imum wi dt h o input t ransi stor 1.he t ransi stor 2i s chosen here to have t he same widt h a sto da te or a C a mpli ier operati ng a t H ba nd. (a)S 21 (b)S 12 (c)1dB Comp ression (d)Noise FigureFig.5 Fi g.5(a ),(b )ill ust rat e t he si mulat ed S 21,S 12of t he amplifier.A 1-dB compre ssion point sim ulation yielded -18dB m ,as shown i n Fig.5(c).The noise figure i s show n i n Fi g.5(d).T a ble.1 Compar iso n of 0.9～5.8GH z CMOS L NA per for ma nce reported in the litera tur e Y ea r G ain Re ver se isolation N F/dB V/V P/mW f req/GHz IP3/dBm Tec hnology/μmRef 200411.57-19.56dB 2.51 4.5 5.8-5.470.18[2]200320-35dB 2.4 3.37.2 2.4-3.40.25[3]200119.9-47.8dB 2.5214.7 2.420.35[4]199922NA 2.5 1.512 2.520.35[5]199815NA 2.8 3.654 1.9-100.8[6]199622NA 3.5 1.530 1.5-9.30.6[7]This work 20.8-87dB1.11.2240.9-8.70.183 ConclusionThe paper p rese nt s a 900MHz LNA i mple 2mented in a 0.18μm CMOS process.Analysis of 2t he a mplifier provides some insight s of t he pro 2posed LN A desi gn.The performance repre sent s ac 2cepta ble compari ng wi t h rece nt wor k li ste d in Ta 2bl e.1and havi ng hi ghest rever se isol at io n especial 2ly.Thi s LNA a rchi tect ure i s suit abl e for low volt 2age U HF RF ID homodyne recei vers a nd ot her higher freque ncy wi reless applications.Fut ure work may be focused on t he furt her opti mization of power di ssipation.4 A cknow ledgmentThe aut hor would like to acknowledge Chun 2Qi S H I ,Jia n 2Ming CUI ,Zong 2Sheng LA I a nd Feng 2Wen CAO for t heir a ssist ance during t he de 2si gn of t he L NA.R eferences :[1] EPC R adio 2Frequency Identi ty Prot ocol s C l ass 21Generatio n 22U H F R FID Pro tocol fo r C o mmunicat ions at 8602960MH Z[S][B OL ][2] Wan g X Z ,Weber R.Des i gn of a CMOS Low Noise A m plifi er(LNA )at 5.8GHz and It s Sen s i ti vit y Anal ysi s[C][EB /OL ].Avail abl e at :ht t p ://www.cam /sym po sium s.[3] Yang X M ,Wu T X ,Mcmacken J .Des i gn of L NA at 2.4GHzu s i ng 0.25m CMOS t echnology [J ].Microwave and Opt ical Technology L et t er s ,2003,36(4):2702275.[4] Huang J C ,Weng R M ,C hang C C.A 2V 2.4GHz f ully i n 2t egrat ed CMOS L NA[C ]//Proc 2001IEE E Intl Symp C i rcuit s Syst 4(2001):4662469.[5] Rafla R A ,El 2G amal M N.Des i gn of a 1.5V CMOS int egrat 2ed 3GHz LNA [C ]//Proc t he 1999IEEE Int l Symp Ci rcuit s Syst 2(1999):4402443.[6] K i m C S ,M Par k ,K i m C H.A Full y Int egrat ed 1.92GHzCMOS Lo w 2Noi s e Amplifi er [J ].IEE E Mi crowave and Gui de W ave Let ters ,1998,8(8):2932295.[7] Shaeffer D K ,L ee T H.A 1.5V ,1.5GHz CMOS lo w noi seamplifier[C]//Symposiu m on VLSI C i rcuit s Di gest (1996):32233.[8] Wang B ,Hel lum s J R ,Sodi ni C G.MOSFET Thermal Noi seModel ing for Analog Integrat ed Ci rcuit s [J ].I EEE J ournal of Soli d 2St at e circui t s ,1994,29(7):8332835.[9] Lee T H.The Des i gn of CMOS Radio 2Frequency Int egrat edCircui t s [M ].Cambri dge U ni versit y Pres s ,C am bri dge ,Eng 2land ,2004.[10] Behzard R.R F Mi croel ect ronics [M ].Pear s on Educat ionInc.,1998.354第2期张润曦,石春琦等:零中频U HF R FID 接收机中的低噪声放大器设计8E /.A vaila ble at :ht tp ://ww w.epc gl obali nc.or g.。
