ADC08D1500
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ADC08D1500
HighPerformance,LowPower,Dual8-Bit,1.5GSPSA/D
Converter
GeneralDescription
TheADC08D1500isadual,lowpower,highperformance
CMOSanalog-to-digitalconverterthatdigitizessignalsto8
bitsresolutionatsampleratesupto1.7GSPS.Consuming
atypical1.8Wattsat1.5GSPSfromasingle1.9Voltsupply,
thisdeviceisguaranteedtohavenomissingcodesoverthe
fulloperatingtemperaturerange.Theuniquefoldingand
interpolatingarchitecture,thefullydifferentialcomparator
design,theinnovativedesignoftheinternalsample-and-
holdamplifierandtheself-calibrationschemeenableavery
flatresponseofalldynamicparametersbeyondNyquist,
producingahigh7.25ENOBwitha748MHzinputsignal
anda1.5GHzsampleratewhileprovidinga10-18B.E.R.
OutputformattingisoffsetbinaryandtheLVDSdigitalout-
putsarecompliantwithIEEE1596.3-1996,withtheexcep-
tionofanadjustablecommonmodevoltagebetween0.8V
and1.2V.
Eachconverterhasa1:2demultiplexerthatfeedstwoLVDS
busesandreducestheoutputdatarateoneachbustohalf
thesamplerate.Thetwoconverterscanbeinterleavedand
usedasasingle3GSPSADC.
Theconvertertypicallyconsumeslessthan3.5mWinthe
PowerDownModeandisavailableina128-lead,thermally
enhancedexposedpadLQFPandoperatesovertheIndus-
trial(-40˚C≤TA≤+85˚C)temperaturerange.Features
nInternalSample-and-Hold
nSingle+1.9V±0.1VOperation
nChoiceofSDRorDDRoutputclocking
nInterleaveModefor2xSampleRate
nMultipleADCSynchronizationCapability
nGuaranteedNoMissingCodes
nSerialInterfaceforExtendedControl
nFineAdjustmentofInputFull-ScaleRangeandOffset
nDutyCycleCorrectedSampleClock
KeySpecifications
nResolution8Bits
nMaxConversionRate1.5GSPS(min)
nBitErrorRate10-18(typ)
nENOB@748MHzInput7.25Bits(typ)
nDNL±0.15LSB(typ)
nPowerConsumption
—Operating1.8W(typ)
—PowerDownMode3.5mW(typ)
Applications
nDirectRFDownConversion
nDigitalOscilloscopes
nSatelliteSet-topboxes
nCommunicationsSystems
nTestInstrumentation
BlockDiagram
20152153September2005ADC08D1500
High
Performance,
Low
Power,
Dual
8-Bit,
1.5
GSPS
A/D
Converter
©2005NationalSemiconductorCorporationDS201521www.national.comOrderingInformation
IndustrialTemperatureRange
(-40˚C
ADC08D1500CIYB128-PinExposedPadLQFP
ADC08D1500EVALEvaluationBoard
PinConfiguration
20152101
*Exposedpadonbackofpackagemustbesolderedtogroundplanetoensureratedperformance.ADC08D1500
www.national.com2PinDescriptionsandEquivalentCircuits
PinFunctions
PinNo.SymbolEquivalentCircuitDescription
3OutV/SCLKOutputVoltageAmplitudeandSerialInterfaceClock.Tiethis
pinhighfornormaldifferentialDCLKanddataamplitude.
Groundthispinforareduceddifferentialoutputamplitudeand
reducedpowerconsumption.SeeSection1.1.6.Whenthe
extendedcontrolmodeisenabled,thispinfunctionsasthe
SCLKinputwhichclocksintheserialdata.SeeSection1.2for
detailsontheextendedcontrolmode.SeeSection1.3for
descriptionoftheserialinterface.
4OutEdge/DDR
/SDATADCLKEdgeSelect,DoubleDataRateEnableandSerialData
Input.ThisinputsetstheoutputedgeofDCLK+atwhichthe
outputdatatransitions.(SeeSection1.1.5.2).Whenthispinis
floatingorconnectedto1/2thesupplyvoltage,DDRclocking
isenabled.Whentheextendedcontrolmodeisenabled,this
pinfunctionsastheSDATAinput.SeeSection1.2fordetails
ontheextendedcontrolmode.SeeSection1.3fordescription
oftheserialinterface.
15DCLK_RSTDCLKReset.Apositivepulseonthispinisusedtoresetand
synchronizetheDCLKoutsofmultipleconverters.See
Section1.5fordetaileddescription.
26
29PD
PDQPowerDownPins.AlogichighonthePDpinputstheentire
deviceintothePowerDownMode.AlogichighonthePDQ
pinputsonlythe"Q"ADCintothePowerDownmode.
30CALCalibrationCycleInitiate.Aminimum80inputclockcycles
logiclowfollowedbyaminimumof80inputclockcycleshigh
onthispininitiatestheselfcalibrationsequence.SeeSection
2.4.2foranoverviewofself-calibrationandSection2.4.2.2for
adescriptionofon-commandcalibration.
14FSR/ECEFullScaleRangeSelectandExtendedControlEnable.In
non-extendedcontrolmode,alogiclowonthispinsetsthe
full-scaledifferentialinputrangeto650mVP-P.Alogichighon
thispinsetsthefull-scaledifferentialinputrangeto870
mVP-P.SeeSection1.1.4.Toenabletheextendedcontrol
mode,wherebytheserialinterfaceandcontrolregistersare
employed,allowthispintofloatorconnectittoavoltage
equaltoVA/2.SeeSection1.2forinformationonthe
extendedcontrolmode.
127CalDly/DES/
SCSCalibrationDelay,DualEdgeSamplingandSerialInterface
ChipSelect.Withalogichighorlowonpin14,thispin
functionsasCalibrationDelayandsetsthenumberofinput
clockcyclesafterpowerupbeforecalibrationbegins(See
Section1.1.1).Withpin14floating,thispinactsastheenable
pinfortheserialinterfaceinputandtheCalDlyvalue
becomes"0"(shortdelaywithnoprovisionforalong
power-upcalibrationdelay).Whenthispinisfloatingor
connectedtoavoltageequaltoVA/2,DES(DualEdge
Sampling)modeisselectedwherethe"I"inputissampledat
twicetheinputclockrateandthe"Q"inputisignored.See
Section1.1.5.1.ADC08D1500
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