FPGA可编程逻辑器件芯片XQ5VFX100T-1F1136I中文规格书

Symbol DescriptionSpeed GradeUnits -2I-1I-1MSequential DelaysT REG Clock to A–D outputs 1.43 1.73 1.73ns, Max T REG_MUX Clock to AMUX–DMUX output 1.55 1.87 1.87ns, Max T REG_M31Clock to DMUX output via M31 output 1.15 1.38 1.38ns, Max Setup and Hold Times Before/After Clock CLKT WS/T WH WE input0.24–0.040.29–0.020.29–0.02ns, MinT CECK/T CKCE CE input to CLK0.27–0.070.33–0.060.33–0.06ns, MinT DS/T DH A–D inputs to CLK 0.660.090.780.110.780.11ns, MinClock CLKT MPW Minimum pulse width0.700.850.85ns, MinNotes:1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” islisted, there is no positive hold time.DSP48E Switching CharacteristicsMaximum Frequency F MAXBlock RAM in all modes500450450MHz F MAX_CASCADE Block RAM in cascade configuration 450400400MHz F MAX_FIFO FIFO in all modes500450450MHz F MAX_ECC Block RAM and FIFO in ECC configuration375325325MHzNotes:1.TRACE will report all of these parameters as T RCKO_DO .2.T RCKO_DOR includes T RCKO_DOW , T RCKO_DOPR , and T RCKO_DOPW as well as the B port equivalent timing parameters.3.These parameters also apply to synchronous FIFO with DO_REG =0.4.T RCKO_DO includes T RCKO_DOP as well as the B port equivalent timing parameters.5.These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG =1.6.T RCKO_FLAGS includes the following parameters: T RCKO_AEMPTY , T RCKO_AFULL , T RCKO_EMPTY , T RCKO_FULL , T RCKO_RDERR , T RCKO_WRERR .7.T RCKO_POINTERS includes both T RCKO_RDCOUNT and T RCKO_WRCOUNT .8.The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.9.T RCKO_DI includes both A and B inputs as well as the parity inputs of A and B.10.These parameters also apply to RDEN.11.T RCO_FLAGS includes the following flags: AEMPTY , AFULL, EMPTY , FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT .Table 69:DSP48E Switching CharacteristicsSymbolDescriptionSpeed Grade Units-2I -1I -1M Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{AA, BB, ACINA, BCINB}/TDSPCKD_{AA, BB, ACINA, BCINB}{A, B, ACIN, BCIN} input to {A, B} register CLK 0.210.230.260.300.260.30ns TDSPDCK_CC/TDSPCKD_CCC input to C register CLK0.160.310.200.370.200.50nsSetup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{AM, BM, ACINM, BCINM}/TDSPCKD_{AM, BM, ACINM, BCINM}{A, B, ACIN, BCIN} input to M register CLK1.440.191.710.191.710.19nsSetup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{AP , BP , ACINP , BCINP}_M/TDSPCKD_{AP , BP , ACINP , BCINP}_M {A, B, ACIN, BCIN} input to P register CLK using multiplier2.74–0.303.25–0.30 3.25–0.30ns TDSPDCK_{AP , BP , ACINP , BCINP}_NM/TDSPCKD_{AP , BP , ACINP , BCINP}_NM {A, B, ACIN, BCIN} input to P register CLK not using multiplier1.54–0.10 1.83–0.10 1.83–0.10ns TDSPDCK_CP/TDSPCKD_CP C input to P register CLK1.42–0.13 1.70–0.13 1.70–0.13ns TDSPDCK_{PCINP , CRYCINP , MULTSIGNINP}/TDSPCKD_{PCINP , CRYCINP , MULTSIGNINP}{PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK1.170.111.310.111.310.11nsSetup and Hold Times of the CE PinsTDSPCCK_{CEA1A, CEA2A, CEB1B,CEB2B}/TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}{CEA1, CEA2A, CEB1B, CEB2B} input to {A,B} register CLK 0.280.250.330.310.330.31nsTDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.210.210.260.280.260.28ns TDSPCCK_CEMM/TDSPCKC_CEMMCEM input to M register CLK0.290.210.360.260.360.26nsTable 68:Block RAM and FIFO Switching Characteristics (Cont’d)SymbolDescriptionSpeed Grade Units-2I -1I -1MPLL Switching Characteristics Table 74:PLL SpecificationSymbol DescriptionSpeed GradeUnits -2I-1I-1MF INMAX Maximum Input Clock Frequency710645645MHz F INMIN Minimum Input Clock Frequency191919MHz F INJITTER Maximum Input Clock Period Jitter<20% of clock input period or 1ns Max F INDUTY Allowable Input Duty Cycle: 19—49MHz25/75%Allowable Input Duty Cycle: 50—199MHz30/70%Allowable Input Duty Cycle: 200—399MHz35/65%Allowable Input Duty Cycle: 400—499MHz40/60%Allowable Input Duty Cycle: >500MHz45/55% F VCOMIN Minimum PLL VCO Frequency400400400MHz F VCOMAX Maximum PLL VCO Frequency120010001000MHzF BANDWIDTH Low PLL Bandwidth at T ypical(1)111MHz High PLL Bandwidth at Typical(1)444MHzT ST APHAOFFSET Static Phase Offset of the PLL Outputs120120120ps T OUTJITTER PLL Output Jitter(2)Note 1T OUTDUTY PLL Output Clock Duty Cycle Precision(3)±200±200±200ps T LOCKMAX PLL Maximum Lock Time(4)100100100µs F OUTMAX PLL Maximum Output Frequency for LX30T, LX85, LX110,LX110T, SX50T, and FX70T(I) devices667600N/A MHzPLL Maximum Output Frequency for LX155T, FX70T(M), andFX100T devices600550550MHz PLL Maximum Output Frequency for FX130T devices500450N/A MHzPLL Maximum Output Frequency for LX220T, LX330T, SX95T,SX240T, and FX200T devices500450N/A MHz F OUTMIN PLL Minimum Output Frequency(5) 3.125 3.125 3.125MHz T EXTFDVAR External Clock Feedback Variation<20% of clock input period or 1ns Max RST MINPULSE Minimum Reset Pulse Width555ns F PFDMAX Maximum Frequency at the Phase Frequency Detector500450450MHz F PFDMIN Minimum Frequency at the Phase Frequency Detector191919MHz T FBDELAY Maximum Delay in the Feedback Path3ns Max or one CLKIN cycle Notes:1.The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.2.Values for this parameter are available in the Architecture Wizard.3.Includes global clock buffer.4.The LOCK signal must be sampled after T LOCKMAX. The LOCK signal is invalid after configuration or reset until the T LOCKMAX time hasexpired.5.Calculated as F VCO/128 assuming output duty cycle is 50%.。

FPGA RX InterfaceOverviewThe FPGA receives RX data from the GTX receiver through the FPGA RX interface. Data is read from the RXDATA port on the positive edge of RXUSRCLK2.The width of RXDATA can be configured to be one or two bytes wide. The actual width of the port depends on the internal data width of the GTX_DUAL tile, and whether or not the 8B/10B decoder is enabled. Ports widths of 8 bits, 10 bits, 16 bits, 20 bits, 32 bits, and 40 bits are possible.The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. RXUSRCLK must be provided for the internal PCS logic in the receiver. This section shows how to drive the parallel clocks and explains the constraints on those clocks for correct operation.Ports and AttributesPortDirClock DomainDescriptionINT D ATAWI D TH InAsyncS pecifies the bit width for the TX and RX paths. The bit width of TX and RXmust be identical for both channels.0: 16-bit width 1: 20-bit widthREFCLKOUT Out N/AThe REFCLKOUT port from each GTX_DUAL tile provides access to thereference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.RXDATA0[31:0]RXDATA1[31:0]Out RXUSRCLK2Receive data bus of the receive interface to the FPGA. The width of RXDATA(0/1) depends on the setting of RXDATAWIDTH(0/1).RXDATAWIDTH0RXDATAWIDTH1InRXUSRCLK2Selects the width of the RXDATA(0/1) receive data connection to the FPGA.0: One-byte interface => RXDATA(0/1)[7:0]1: Two-byte interface => RXDATA(0/1)[15:0]2: Four-byte interface => RXDATA(0/1)[31:0]The clock domain depends on the selected clock (RXRECCLK(0/1), RXUSRCLK(0/1), and RXUSRCLK2(0/1)) for this interface.RXRECCLK0RXRECCLK1Out N/ARecovered clock from the CDR. Clocks the RX logic between the PMA and the RX elastic buffer. Can be used to drive RXUSRCLK synchronously with incoming data.When RXPOWERDOWN[1:0] is set to 11, which is P2 the lowest power state, then RXRECCLK of this transceiver is indeterminate. RXRECCLK of this GTX transceiver is either a static 1 or a static 0.RXRESET0RXRESET1In AsyncPCS RX system reset. Resets the RX elastic buffer, 8B/10B decoder, comma detect, and other RX registers. This is a per channel subset of GTXRESET.FPGA RX InterfaceThere are no attributes in this section.DescriptionThe FPGA RX interface allows parallel received data to be read from the GTX transceiver. For this interface to be used, the following must be done: •The width of the RXDATA port must be configured•RXUSRCLK2 and RXUSRCLK must be connected to clocks running at the correct rate.Configuring the Width of the InterfaceTable 7-44 shows how to select the interface width for the RX datapath. 8B/10B decoding is discussed in more detail in “Configurable 8B/10B Decoder,” page 200.RXUSRCLK0RXUSRCLK1In N/AThis port provides a clock for the internal RX PCS datapath. This clock must always be provided. The rate depends on INTDATAWIDTH where:INTDATAWIDTH is Low; F RXUSRCLK = Line Rate/16INTDATAWIDTH is High; F RXUSRCLK = Line Rate/20RXUSRCLK20RXUSRCLK21In N/AThis port synchronizes the FPGA logic with the RX interface. This clock must be positive-edge aligned to RXUSRCLK. The clock rate depends on F RXUSRCLK and RXDATAWIDTH:RXDATAWIDTH =0; F RXUSRCLK2=2x F RXUSRCLK RXDATAWIDTH =1; F RXUSRCLK2=F RXUSRCLK RXDATAWIDTH =2; F RXUSRCLK2=F RXUSRCLK /2Table 7-43:FPGA RX Interface Ports (Cont’d)PortDirClock DomainDescriptionTable 7-44:RX Datapath Width ConfigurationINTDATAWIDTH (1)RXDATAWIDTH (2)RXDEC8B10BUSEFPGA RX Interface Width(bits)00N/A 801N/A 1602N/A 3210010110201204010181111612132Notes:1.The internal datapath is 16 bits when INTDATAWIDTH is Low and 20 bits when INTDATAWIDTH is High.2.The RXDATA interface is one byte wide when RXDATAWIDTH = 0, two bytes wide when RXDATAWIDTH = 1, and four bytes when RXDATAWIDTH = 2.Chapter 7:GTX Receiver (RX)Figure7-42 shows how RXDATA is received serially when the internal datapath is 16bits(INTDATAWIDTH is Low) and 8B/10B decoding is disabled.Figure 7-42:RX Interface with 8B/10B Bypassed (16-Bit Internal Datapath)Figure7-43 shows how RXDATA is received serially when the internal datapath is 20 bits(INTDATAWIDTH is High) and 8B/10B decoding is disabled. When RXDATA is 10 bits or20bits wide, the RXDISPERR and RXCHARISK ports are taken from the 8B/10B decoderinterface and are used to present the extra bits.Figure 7-43:RX Interface with 8B/10B Bypassed (20-Bit Internal Datapath)DescriptionUsing the CRC BlocksFigure8-3 shows a CRC block calculating the CRC for input data. Also shown in this figureis the CRC32 primitive. This operation is performed when the CRC is being generated orchecked. CRC_POLY is the fixed CRC32 polynomial used for all calculations.Figure 8-3:CRC Block TimingAt the start of each frame, CRCRESET must be applied to set the initial CRC value toCRC_INIT. CRC calculations are cumulative, so this step is required to start the CRCcalculation at a known value. CRC_INIT is a 32-bit value for the initial state of the CRCinternal register. Its default value is 0xFFFFFFFF. When CRCRESET is driven Low, on thefirst cycle the CRC block outputs 0x00000000 on the CRCOUT port. The following cycleswill have the calculated CRC value for the data on the CRCIN port. The CRC_INIT valuerequired for a given protocol is specified as part of that protocol’s CRC algorithm. Table8-6shows the CRC_INIT values for some common protocols that use the CRC32 polynomial.Table 8-6:CRC_INIT Values for Some Common ProtocolsProtocol CRC_INITEthernet32’hFFFF_FFFFPCI Express32’hFFFF_FFFFInfiniband32’hFFFF_FFFFFibre Channel32’hFFFF_FFFFSATA32’h5232_5032Chapter 8:Cyclic Redundancy Check。

DS310 (v1.7) June 28, 2005Product SpecificationFeatures•Optimized for 1.8V systems-As fast as 3.8ns pin-to-pin logic delays-As low as 12 μA quiescent current•Industry’s best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis-Multi-voltage I/O operation: 1.5V through 3.3V•Available in multiple package options-32-land QFN with 21 user I/O-44-pin PLCC with 33 user I/O-44-pin VQFP with 33 user I/O-56-ball CP BGA with 33 user I/O-Pb-free available for all packages•Advanced system features-Fastest in system programming· 1.8V ISP using IEEE 1532 (JTAG) interface-IEEE1149.1 JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-Two separate I/O banks-RealDigital 100% CMOS product term generation-Flexible clocking modes-Optional DualEDGE triggered registers-Global signal options with macrocell control·Multiple global clocks with phase selection permacrocell·Multiple global output enables·Global set/reset-Efficient control term clocks, output enables andset/resets for each macrocell and shared acrossfunction blocks-Advanced design security-Open-drain output option for Wired-OR and LEDdrive-Optional configurable grounds on unused I/Os-Optional bus-hold, 3-state or weak pullup onselected I/O pins-Mixed I/O voltages compatible with 1.5V, 1.8V,2.5V, and3.3V logic levels-PLA architecture·Superior pinout retention·100% product term routability across functionblock-Hot pluggable Refer to the CoolRunner™-II family data sheet for architec-ture description.Description The CoolRunner ™-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli-ability is improved This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configura-tion bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up,open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to stor-ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis.Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.A global set/reset control line is also available to asynchro-nously set or reset selected registers during operation.Additional local clock, synchronous clock-enable, asynchro-nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. The CoolRunner-II 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O com-patible with the use of Schmitt-trigger inputs.Another feature that eases voltage translation is I/O bank-ing. Two I/O banks are available on the CoolRunner-II 32A macrocell device that permit easy interfacing to 3.3V, 2.5V,1.8V, and 1.5V devices.XC2C32A CoolRunner-II CPLDDS310 (v1.7) June 28, 2005Product SpecificationCoolRunner-II CPLD I2C Bus Controller ImplementationTable 1: CoolRunner-II I2C Controller Signal DescriptionIRQ Output Interrupt Request. Active Low.MCF Output Data Transferring Bit. While one byte of data isbeing transferred, this bit is cleared. It is set by thefalling edge of the ninth clock of a byte transfer. Thisbit is used to signal the completion of a byte transferto the μC.CLK Input Clock. This clock is input from the system. Theconstants used in generating a 100 KHz SCL signalassumes the frequency to be 1.832 MHz. Differentclock frequencies can be used, but the constants inthe VHDL source code must be recalculated. Block Diagram The block diagram of the CoolRunner-II I2C Controller, shown in Figure3 was broken into two major blocks, the μC interface and the I2C interface.Figure 3: CoolRunner-II I2C ControllerXAPP385 (v1.1) December 30, 2003。

© 2006–2010, 2014, 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.Virtex-5 FPGA Electrical CharacteristicsVirtex®-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and ACelectrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range.All supply voltage and junction temperature specifications are representative of worst-case conditions. Theparameters included are common to popular designs and typical applications.This Virtex-5 FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:•Virtex-5 Family Overview •Virtex-5 FPGA User Guide•Virtex-5 FPGA Configuration Guide•Virtex-5 FPGA XtremeDSP™ Design Considerations •Virtex-5 FPGA Packaging and Pinout Specification•Embedded Processor Block in Virtex-5 FPGAs Reference Guide•Virtex-5 FPGA RocketIO™ GTP Transceiver User Guide •Virtex-5 FPGA RocketIO GTX Transceiver User Guide •Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide•Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express® Designs•Virtex-5 FPGA System Monitor User Guide •Virtex-5 FPGA PCB Designer’s GuideAll specifications are subject to change without notice.Virtex-5 FPGA DC CharacteristicsProduct SpecificationTable 1:Absolute Maximum RatingsSymbol DescriptionUnits V CCINT Internal supply voltage relative to GND –0.5 to 1.1V V CCAUX Auxiliary supply voltage relative to GND–0.5 to 3.0V V CCO Output drivers supply voltage relative to GND –0.5 to 3.75V V BATT Key memory battery backup supply –0.5 to 4.05V V REFInput reference voltage–0.5 to 3.75V V IN (3)3.3V I/O input voltage relative to GND (4) (user and dedicated I/Os)–0.75 to 4.05V 3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(5)–0.95 to 4.4(Commercial Temperature)V –0.85 to 4.3(Industrial Temperature)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO +0.5V I IN Current applied to an I/O pin, powered or unpowered±100mA Total current applied to all I/O pins, powered or unpowered±100mA V TS Voltage applied to 3-state 3.3V output (4) (user and dedicated I/Os)–0.75 to 4.05V Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)–0.75 to V CCO +0.5V T STG Storage temperature (ambient)–65to 150°C T SOL Maximum soldering temperature (2)+220°C T JMaximum junction temperature (2)+125°CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.2.For soldering guidelines, refer to UG112: Device Package User Guide . For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging andPinout Specification on the Xilinx website.3. 3.3V I/O absolute maximum limit applied to DC and AC signals.4.For 3.3V I/O operation, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines .5.For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period .找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司DS202 (v5.5) June 17, 2016Table 2:Recommended Operating ConditionsSymbol DescriptionTemperature RangeMin Max Units V CCINT Internal supply voltage relative to GND, T J =0°C to +85°C Commercial 0.95 1.05V Internal supply voltage relative to GND, T J =–40°C to +100°C Industrial 0.95 1.05V V CCAUX (1)Auxiliary supply voltage relative to GND, T J =0°C to +85°C Commercial 2.375 2.625V Auxiliary supply voltage relative to GND, T J =–40°C to +100°C Industrial 2.375 2.625V V CCO (2,4,5)Supply voltage relative to GND, T J =0°C to +85°C Commercial 1.14 3.45V Supply voltage relative to GND, T J =–40°C to +100°C Industrial 1.14 3.45V V IN3.3V supply voltage relative to GND, T J =0°C to +85°C Commercial GND –0.20 3.45V 3.3V supply voltage relative to GND, T J =–40°C to +100°C Industrial GND –0.20 3.45V 2.5V and below supply voltage relative to GND, T J =0°C to +85°CCommercial GND –0.20V CCO +0.2V 2.5V and below supply voltage relative to GND, T J =–40°C to +100°CIndustrial GND –0.20V CCO +0.2V I IN (6)Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode Commercial 10mA Industrial 10mA V BATT (3)Battery voltage relative to GND, T J =0°C to +85°C Commercial 1.0 3.6V Battery voltage relative to GND, T J =–40°C to +100°CIndustrial1.03.6VGTX_DUAL Tile SpecificationsGTX_DUAL Tile DC CharacteristicsTable 36:Absolute Maximum Ratings for GTX_DUAL TilesSymbol Description Units MGTAVCCPLL Analog supply voltage for the GTX_DUAL shared PLL relative to GND–0.5 to 1.1V MGTAVTTTX Analog supply voltage for the GTX_DUAL transmitters relative to GND–0.5 to 1.32V MGTAVTTRX Analog supply voltage for the GTX_DUAL receivers relative to GND–0.5 to 1.32V MGTAVCC Analog supply voltage for the GTX_DUAL common circuits relative to GND–0.5 to 1.1V–0.5 to 1.32V MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTX_DUALcolumnSystem Monitor Analog-to-Digital Converter SpecificationTable 51:Analog-to-Digital SpecificationsParameter Symbol Comments/Conditions Min Typ Max UnitsAV DD=2.5V±2%, V REFP=2.5V,V REFN=0V, ADCCLK=5.2MHz, T A=T MIN to T MAX, Typical values at T A=+25°CDC Accuracy: All external input channels such as V P/V N and V AUXP[15:0]/V AUXN[15:0], Unipolar Mode,and Common Mode = 0VResolution10Bits Integral Nonlinearity INL±2LSBsDifferential Nonlinearity DNL No missing codes (T MIN to T MAX)Guaranteed Monotonic±0.9LSBs Unipolar Offset Error(1)Uncalibrated±2±30LSBs Bipolar Offset Error(1)Uncalibrated measured in bipolar mode ±2±30LSBs Gain Error(1)Uncalibrated±0.2±2% Bipolar Gain Error(1)Uncalibrated measured in bipolar mode±0.2±2%Total Unadjusted Error (Uncalibrated)TUE Deviation from ideal transfer function.V REFP–V REFN=2.5V±10LSBsTotal Unadjusted Error (Calibrated)TUE Deviation from ideal transfer function.V REFP–V REFN=2.5V±1±2LSBsCalibrated Gain TemperatureCoefficientVariation of FS code with temperature±0.01LSB/°CDC Common-Mode Reject CMRR DC V N = V CM=0.5V± 0.5V,V P–V N=100mV70dB Conversion Rate(2)Conversion Time - Continuous t CONV Number of CLK cycles2632Conversion Time - Event t CONV Number of CLK cycles21T/H Acquisition Time t ACQ Number of CLK cycles4DRP Clock Frequency DCLK DRP clock frequency8250MHz ADC Clock Frequency ADCCLK Derived from DCLK1 5.2MHz CLK Duty cycle4060% Analog Inputs(3)Dedicated Analog Inputs Input Voltage RangeV P - V N Unipolar Operation01Volts Differential Inputs–0.25+0.25Unipolar Common Mode Range (FS input)0+0.5 Differential Common Mode Range (FS input) +0.3+0.7 Bandwidth20MHzAuxiliary Analog InputsInput Voltage RangeV AUXP[0] /V AUXN[0] to V AUXP[15] /V AUXN[15]Unipolar Operation01Volts Differential Operation–0.25+0.25Unipolar Common Mode Range (FS input)0+0.5 Differential Common Mode Range (FS input)+0.3+0.7 Bandwidth10kHzInput Leakage Current A/D not converting, ADCCLK stopped±1.0µA Input Capacitance10pFOn-chip Supply Monitor Error V CCINT and V CCAUX with calibration enabled±1.0% Reading On-chip Temperature MonitorError–40°C to +125°C with calibration enabled±4°C。

General DescriptionThe Defense-grade XQ UltraScale™ architecture-based devices extend the equivalent commercial offerings, adding unique ruggedized packages, extended operating temperature range support, and added environmental qualification testing. This XQ portfolio spans the following families, with each offering a unique mix of features. XQ Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic andnext-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.XQ Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.XQ Virtex® UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.XQ Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the Arm Cortex-R5 real-time processor and the UltraScale architecture to create the industry's first Defense-grade MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration. XQ Zynq UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.XQ Device ComparisonsDS895 (v2.0) November 15, 2018Product Specification Table 1:Device Resources(1)XQ Kintex UltraScale FPGAXQ KintexUltraScale+FPGAXQ VirtexUltraScale+FPGAXQ ZynqUltraScale+MPSoCXQ ZynqUltraScale+RFSoCMPSoC Processing System✓✓RF-ADC/DAC and SD-FEC✓System Logic Cells (K)530–1,451475–1,143862–2,835154–1,143930 Block Memory (Mb)21.1–75.916.9–34.625.3–70.9 5.1–34.638.0 UltraRAM (Mb)18–3690–2700–3622.5 HBM DRAM (GB)0(2)DSP (Slices)1,920–5,5201,824–1,9682,280–9,216360–3,5284,272 DSP Performance (GMAC/s)(3)7,2973,05014,2845,4686,621 Transceivers16–6416–5640–960–488–16 Max. Transceiver Speed (Gb/s)16.328.228.228.228.2 Max. Serial Bandwidth (full duplex) (Gb/s)2,0862,4025,4161,950902I/O Pins312–728280–512416–83282–644152–408 Notes:1.Metrics given in this table pertain to the XQ ruggedized package devices. For non-ruggedized device variants consult Xilinx sales.2.HBM not currently offered in an XQ ruggedized Package; consult Xilinx sales for further details and options.3.Calculated based on XQ maximum DSP clock rate for a Symmetric FIR Filter, e.g. for KU040 with 1920 DSP48s, -2 speed-grade DSP48F MAX=661MHz, GMACs=2x0.661x1,920=2,538.XQ Kintex UltraScaleXQ Kintex UltraScale+XQ Virtex UltraScale+XQ Zynq UltraScale+ PLXQ Zynq UltraScale+ PSADC10-bit 200kSPS10-bit 200kSPS10-bit 1MSPS Interfaces JTAG, I2C, DRP JTAG, I2C, DRP, PMBus APB•64-bit quad-core Arm Cortex-A53 MPCores. Features associated with each core include: o Arm v8-A Architectureo Operating target frequency: up to 1.5GHzo Single and double precision floating point:4SP/2DP FLOPso NEON Advanced SIMD support with single and double precision floating point instructions o A64 instruction set in 64-bit operating mode, A32/T32 instruction set in 32-bit operating mode o Level 1 cache (separate instruction and data, 32KB each for each Cortex-A53 CPU)–2-way set-associative Instruction Cache with parity support–4-way set-associative Data Cache with ECC supporto Integrated memory management unit (MMU) per processor coreMIO OverviewThe IOP peripherals communicate to external devices through a shared pool of up to 78 dedicated multiplexed I/O (MIO) pins. Each peripheral can be assigned one of several pre-defined groups of pins, enabling a flexible assignment of multiple devices simultaneously. Although 78 pins are not enough for simultaneous use of all the I/O peripherals, most IOP interface signals are available to the PL, allowing use of standard PL I/O pins when powered up and properly configured. Extended multiplexed I/O (EMIO) allows unmapped PS peripherals to access PL I/O.Port mappings can appear in multiple locations. For example, there are up to 12 possible port mappings for CAN pins. The PS Configuration Wizard (PCW) tool aids in peripheral and static memory pin mapping. See Table 17.Transceiver (PS-GTR)The four PS-GTR transceivers, which reside in the full power domain (FPD), support data rates of up to 6.0Gb/s. All the protocols cannot be pinned out at the same time. At any given time, four differential pairs can be pinned out using the transceivers. This is user programmable via the high-speed I/O multiplexer (HS-MIO). •A Quad transceiver PS-GTR (TX/RX pair) able to support following standards simultaneouslyo x1, x2, or x4 lane of PCIe at Gen1 (2.5Gb/s) or Gen2 (5.0Gb/s) rates o 1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s o 1 or 2 SATA channels at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s o 1 or 2 USB3.0 channels at 5.0Gb/s o1-4 Ethernet SGMII channels at 1.25Gb/sTable 17:MIO Peripheral Interface MappingPeripheral InterfaceMIOEMIOQuad-SPI NAND YesNo USB2.0: 0,1Yes: External PHY No SDIO 0,1Yes Yes SPI: 0,1I2C: 0,1CAN: 0,1GPIOYesCAN: External PHY GPIO: Up to 78 bits YesCAN: External PHY GPIO: Up to 96 bitsGigE: 0,1,2,3RGMII v2.0: External PHYSupports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and 1000BASE-X in Programmable LogicUART: 0,1Simple UART:Only two pins (TX and RX)Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:•Two Processing System (PS) pins (RX and TX) through MIO and sixadditional Programmable Logic (PL) pins, or •Eight Programmable Logic (PL) pinsDebug Trace Ports Yes: Up to 16 trace bits Yes: Up to 32 trace bits Processor JTAGYesYes。

OverviewThe purpose of this notification is to inform Xilinx customers of the discontinuation of certain Virtex®-4 andVirtex®-5 FPGA devices special part numbers only; devices will continue to ship without change to form, fit, or function, but with updated part numbers.DescriptionSince the introduction of Virtex-4 and Virtex-5 FPGA products, Xilinx has qualified both product families in both Toshiba, in Oita, Japan, and UMC in Taiwan, and has been shipping the majority of devices in each product family from UMC. As part of the consolidation effort described in XCN11030, wafer fabrication for all Virtex-4 and Virtex-5 Devices described in this document will be transferred to UMC.As a result of this transfer, certain part numbers, including SCD and Stepping, will be converted into standard part numbers.For these devices, there is no change to the form, fit, or function of the devices themselves. Qualification data is available in the Xilinx reliability report UG116.Products AffectedThe products affected include all Virtex-4 and Virtex-5 part numbers associated with the following associated SCDand stepping: 0641, 0988, 4009, 4013, 4023, 4058, 4094, 4098, 4108, CS1, CS2 part numbers listed in Table 1,Table 2 and Table 3 below.XCN11031 (v1.1) June 9, 2015Product Discontinuation Notice For Virtex-4 and Virtex-5 FPGA SCDs from Toshiba Wafer FabricationXCN11031 (v1.1) June 9, 2015Product Discontinuation Notice For Virtex-4 and Virtex-5 FPGA SCDs from Toshiba Wafer FabricationXCN11031 (v1.1) June 9, 2015Product Discontinuation Notice For Virtex-4 and Virtex-5 FPGA SCDs from Toshiba Wafer FabricationXCN11031 (v1.1) June 9, 2015Product Discontinuation Notice For Virtex-4 and Virtex-5 FPGA SCDs from Toshiba Wafer Fabrication XCN11031 (v1.1) June 9, 2015。

DS100 (v5.1) August 21, 2015Product Specification General DescriptionUsing the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25x18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC®440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability.Summary of Virtex-5 FPGA FeaturesVirtex-5 Family OverviewSystem Blocks Specific to the LXT, SXT, TXT, and FXT DevicesIntegrated Endpoint Block for PCI Express Compliance•Works in conjunction with RocketIO GTP transceivers (LXT and SXT) and GTX transceivers (TXT and FXT) to deliver full PCI Express Endpoint functionality withminimal FPGA logic utilization.•Compliant with the PCI Express Base Specification 1.1•PCI Express Endpoint block or Legacy PCI Express Endpoint block•x8, x4, or x1 lane width•Power management support•Block RAMs used for buffering•Fully buffered transmit and receive •Management interface to access PCI Express configuration space and internal configuration •Supports the full range of maximum payload sizes •Up to 6x32 bit or 3x64 bit BARs (or a combination of32 bit and 64 bit)Tri-Mode Ethernet Media Access Controller •Designed to the IEEE 802.3-2002 specification •Operates at 10, 100, and 1,000 Mb/s•Supports tri-mode auto-negotiation•Receive address filter (5 address entries)•Fully monolithic 1000Base-X solution with RocketIO GTP transceivers•Supports multiple external PHY connections (RGMII, GMII, etc.) interfaces through soft logic and SelectIOresources•Supports connection to external PHY device through SGMII using soft logic and RocketIO GTP transceivers •Receive and transmit statistics available through separate interface•Separate host and client interfaces•Support for jumbo frames•Support for VLAN•Flexible, user-configurable host interface•Supports IEEE 802.3ah-2004 unidirectional modeVirtex-5 Family OverviewRocketIO GTP Transceivers (LXT/SXT only)•Full-duplex serial transceiver capable of 100Mb/s to3.75Gb/s baud rates•8B/10B, user-defined FPGA logic, or no encoding options•Channel bonding support•CRC generation and checking •Programmable pre-emphasis or pre-equalization for the transmitter•Programmable termination and voltage swing •Programmable equalization for the receiver •Receiver signal detect and loss of signal indicator •User dynamic reconfiguration using secondary configuration bus•Out of Band (OOB) support for Serial AT A (SAT A)•Electrical idle, beaconing, receiver detection, and PCI Express and SATA spread-spectrum clocking support •Less than 100mW typical power consumption •Built-in PRBS Generators and Checkers RocketIO GTX Transceivers (TXT/FXT only)•Full-duplex serial transceiver capable of 150Mb/s to6.5Gb/s baud rates•8B/10B encoding and programmable gearbox to support 64B/66B and 64B/67B encoding, user-defined FPGA logic, or no encoding options•Channel bonding support•CRC generation and checking •Programmable pre-emphasis or pre-equalization for the transmitter•Programmable termination and voltage swing •Programmable continuous time equalization for the receiver•Programmable decision feedback equalization for the receiver•Receiver signal detect and loss of signal indicator •User dynamic reconfiguration using secondary configuration bus•OOB support (SAT A)•Electrical idle, beaconing, receiver detection, and PCI Express spread-spectrum clocking support •Low-power operation at all line rates PowerPC 440 RISC Cores (FXT only)•Embedded PowerPC 440 (PPC440) cores−Up to 550MHz operation−Greater than 1000 DMIPS per core−Seven-stage pipeline−Multiple instructions per cycle−Out-of-order execution−32Kbyte, 64-way set associative level 1 instruction cache−32Kbyte, 64-way set associative level 1 data cache−Book E compliant•Integrated crossbar for enhanced system performance −128-bit Processor Local Buses (PLBs)−Integrated scatter/gather DMA controllers−Dedicated interface for connection to DDR2 memory controller−Auto-synchronization for non-integer PLB-to-CPU clock ratios•Auxiliary Processor Unit (APU) Interface and Controller −Direct connection from PPC440 embedded block to FPGA fabric-based coprocessors−128-bit wide pipelined APU Load/Store−Support of autonomous instructions: no pipeline stalls−Programmable decode for custom instructionsArchitectural DescriptionVirtex-5 FPGA Array OverviewVirtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-5 devices implement the following functionality:Global ClockingThe CMTs and global-clock multiplexer buffers provide a complete solution for designing high-speed clock networks. Each CMT contains two DCMs and one PLL. The DCMs and PLLs can be used independently or extensively cascaded. Up to six CMT blocks are available, providing up to eighteen total clock generator elements.Each DCM provides familiar clock generation capability. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90°, 180°, and 270° phase-shifted versions of the output clocks. Fine-grained phase shifting offers higher-resolution phase adjustment with fraction of the clock period increments. Flexible frequency synthesis provides a clock output frequency equal to a fractional or integer multiple of the input clock frequency.To augment the DCM capability, Virtex-5 FPGA CMTs also contain a PLL. This block provides reference clock jitter filtering and further frequency synthesis options.Virtex-5 devices have 32 global-clock MUX buffers. The clock tree is designed to be differential. Differential clocking helps reduce jitter and duty cycle distortion.DSP48E SlicesDSP48E slice resources contain a 25x18 two’s complement multiplier and a 48-bitadder/subtacter/accumulator. Each DSP48E slice also contains extensive cascade capability to efficiently implement high-speed DSP algorithms.The Virtex-5 FPGA DSP48E slice features are further discussed in Virtex-5 FPGA XtremeDSP Design Considerations.Routing ResourcesAll components in Virtex-5 devices use the same interconnect scheme and the same access to the global routing matrix. In addition, the CLB-to-CLB routing is designed to offer a complete set of connectivity in as few hops as possible. Timing models are shared, greatly improving the predictability of the performance for high-speed designs.Boundary ScanBoundary-Scan instructions and associated data registers support a standard methodology for accessing and configuring Virtex-5 devices, complying with IEEE standards1149.1 and 1532.ConfigurationVirtex-5 devices are configured by loading the bitstream into internal configuration memory using one of the following modes:•Slave-serial mode•Master-serial mode•Slave SelectMAP mode•Master SelectMAP mode•Boundary-Scan mode (IEEE-1532 and -1149)•SPI mode (Serial Peripheral Interface standard Flash)•BPI-up/BPI-down modes (Byte-wide Peripheral interface standard x8 or x16 NOR Flash)In addition, Virtex-5 devices also support the following configuration options:•256-bit AES bitstream decryption for IP protection •Multi-bitstream management (MBM) for cold/warm boot support•Parallel configuration bus width auto-detection •Parallel daisy chain•Configuration CRC and ECC support for the most robust, flexible device integrity checkingVirtex-5 device configuration is further discussed in the Virtex-5 FPGA Configuration Guide.System MonitorFPGAs are an important building block in highavailability/reliability infrastructure. Therefore, there is need to better monitor the on-chip physical environment of the FPGA and its immediate surroundings within the system. For the first time, the Virtex-5 family System Monitor facilitates easier monitoring of the FPGA and its external environment. Every member of the Virtex-5 family contains a System Monitor block. The System Monitor is built around a 10-bit 200kSPS ADC (Analog-to-Digital Converter). This ADC is used to digitize a number of on-chip sensors to provide information about the physical environment within the FPGA. On-chip sensors include a temperature sensor and power supply sensors. Access to the external environment is provided via a number of external analog input channels. These analog inputs are general purpose and can be used to digitize a wide variety of voltage signal types. Support for unipolar, bipolar, and true differential input schemes is provided. There is full access to the on-chip sensors and external channels via the JTAG T AP, allowing the existing JT AG infrastructure on the PC board to be used for analog test and advanced diagnostics during development or after deployment in the field. The System Monitor is fully operational after power up and before configuration of the FPGA. System Monitor does not require an explicit instantiation in a design to gain access to its basic functionality. This allows the System Monitor to be used even at a late stage in the design cycle.The Virtex-5 FPGA System Monitor is further discussed in the Virtex-5 FPGA System Monitor User Guide.。

SelectIO™ DC Input and Output LevelsValues for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recommended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested.Table 7:SelectIO DC Input and Output LevelsI/O StandardV IL V IH V OL V OH I OL I OH V, Min V, Max V, Min V, Max V, Max V, Min mA mALVTTL–0.30.8 2.0 3.450.4 2.4Note(3)Note(3) LVCMOS33,LVDCI33–0.30.8 2.0 3.450.4V CCO–0.4Note(3)Note(3)LVCMOS25,LVDCI25–0.30.7 1.7V CCO+0.30.4V CCO–0.4Note(3)Note(3)LVCMOS18,LVDCI18–0.335% V CCO65% V CCO V CCO+0.30.45V CCO–0.45Note(4)Note(4)LVCMOS15,LVDCI15–0.335% V CCO65% V CCO V CCO+0.325%V CCO75%V CCO Note(4)Note(4) LVCMOS12–0.335% V CCO65% V CCO V CCO+0.325%V CCO75%V CCO Note(6)Note(6) PCI33_3(5)–0.230% V CCO50% V CCO V CCO10%V CCO90%V CCO Note(5)Note(5) PCI66_3(5)–0.230% V CCO50% V CCO V CCO10%V CCO90%V CCO Note(5)Note(5) PCI-X(5)–0.235% V CCO50% V CCO V CCO10%V CCO90%V CCO Note(5)Note(5) GTLP–0.3V REF–0.1V REF+0.1–0.6N/A36N/A GTL–0.3V REF–0.05V REF+0.05–0.4N/A32N/A HSTL I_12–0.3V REF–0.1V REF+0.1V CCO+0.325%V CCO75%V CCO 6.3 6.3 HSTL I(2)–0.3V REF–0.1V REF+0.1V CCO+0.30.4V CCO–0.48–8 HSTL II(2)–0.3V REF–0.1V REF+0.1V CCO+0.30.4V CCO–0.416–16 HSTL III(2)–0.3V REF–0.1V REF+0.1V CCO+0.30.4V CCO–0.424–8 HSTL IV(2)–0.3V REF–0.1V REF+0.1V CCO+0.30.4V CCO–0.448–8 DIFF HSTL I(2)–0.350% V CCO–0.150% V CCO+0.1V CCO+0.3––––DIFF HSTL II(2)–0.350% V CCO–0.150% V CCO+0.1V CCO+0.3––––SSTL2I–0.3V REF–0.15V REF+0.15V CCO+0.3V TT–0.61V TT+0.618.1–8.1 SSTL2II–0.3V REF–0.15V REF+0.15V CCO+0.3V TT–0.81V TT+0.8116.2–16.2DIFF SSTL2I–0.350% V CCO–0.1550%V CCO+0.15V CCO+0.3––––DIFF SSTL2II–0.350% V CCO–0.1550%V CCO+0.15V CCO+0.3––––SSTL18I–0.3V REF–0.125V REF+0.125V CCO+0.3V TT–0.47V TT+0.47 6.7–6.7 SSTL18II–0.3V REF–0.125V REF+0.125V CCO+0.3V TT–0.60V TT+0.6013.4–13.4DIFF SSTL18I–0.350% V CCO–0.12550%V CCO+0.125V CCO+0.3––––DIFF SSTL18II–0.350% V CCO–0.12550%V CCO+0.125V CCO+0.3––––Notes:1.Tested according to relevant specifications.2.Applies to both 1.5V and 1.8V HSTL.ing drive strengths of 2, 4, 6, 8, 12, 16, or 24mA.ing drive strengths of 2, 4, 6, 8, 12, or 16mA.5.For more information on PCI33_3, PCI66_3, and PCI-X, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.6.Supported drive strengths of 2, 4, 6, or 8mA.Symbol DC Parameter Conditions Min Typ Max Units V CCO Supply Voltage 2.38 2.5 2.63V V OD Differential Output Voltage R T = 100Ω across Q and Q signals495600715mV ΔV OD Change in V OD Magnitude–1515mV V OCM Output Common Mode Voltage R T = 100Ω across Q and Q signals495600715mV ΔV OCM Change in V OCM Magnitude–1515mV V ID Input Differential Voltage2006001000mV ΔV ID Change in V ID Magnitude–1515mV V ICM Input Common Mode Voltage440600780mV ΔV ICM Change in V ICM Magnitude–1515mVTable 27:GTP_DUAL Tile Quiescent Supply CurrentSymbol Description Typ(1)Max UnitsI AVTTTXQ Quiescent MGTAVTTTX (transmitter termination) supply current8.518mAI AVCCPLLQ Quiescent MGTAVCCPLL (PLL) supply current818mAI AVTTRXQ Quiescent MGTAVTTRX (receiver termination) supply current. Includes0.10.8mAMGTAVTTRXCQ.I AVCCQ Quiescent MGTAVCC (analog) supply current 2.511mA Notes:1.Typical values are specified at nominal voltage, 25°C.2.Device powered and unconfigured.3.Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWERAnalyzer (XPA) tools.4.GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number ofavailable GTP_DUAL tiles in the target LXT or SXT device.GTX_DUAL Tile Switching CharacteristicsConsult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.Table 42:GTX_DUAL Tile PerformanceSymbol DescriptionSpeed Grade Units -3-2-1F GTXMAX Maximum GTX transceiver data rate 6.5 6.5 4.25Gb/s F GPLLMAX Maximum PLL frequency 3.25 3.25 3.25GHz F GPLLMINMinimum PLL frequency1.481.481.48GHzTable 43:Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching CharacteristicsSymbol DescriptionSpeed Grade Units -3-2-1F GTXDRPCLKGTX DCLK (DRP clock) maximum frequency200175150MHzTable 44:GTX_DUAL Tile Reference Clock Switching CharacteristicsSymbol DescriptionConditionsAll Speed Grades Units Min Typ Max F GCLK Reference clock frequency range (1)CLK60650MHz T RCLK Reference clock rise time 20%–80%200ps T FCLK Reference clock fall time 80%–20%200ps T DCREF Reference clock duty cycle CLK 405060%T GJTT Reference clock total jitter (2, 3)At 100KHz –145dBc/Hz At 1MHz –150dBc/Hz T LOCK Clock recovery frequency acquisition timeInitial PLL lock0.251ms T PHASE Clock recovery phase acquisition timeLock to data after PLL has locked to the reference clock200µsNotes:1.GREFCLK can be used for serial bit rates up to 1Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.2.GTX_DUAL jitter characteristics measured using a clock with specification T GJTT . A reference clock with higher phase noise can be used with link margin trade off.3.The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during transceiver jitter characterization - see Table 46 and Table 47.Figure 10:Reference Clock Timing Parameters。

CoolRunner-II Serial Peripheral Interface Master not specify that the first byte contain an address or a read/write line. When communicating to devices over the SPI bus, it is important to review the specifications of these devices to determine the required communication protocol so that commands, addresses and the data direction (read/write) can be set correctly. The CoolRunner-II CPLD SPI Master implementation will not enforce a particular data protocol. It is expected that the μC will specify the data bytes to be transferred on the SPI bus in the correct order. All data received on the SPI bus will be stored in a receive register for the user logic to interpret. All data written to the transmit register will be transmitted on the SPI bus.CoolRunner-II SPI Master Implementation The CoolRunner-II CPLD implementation of an SPI Master supports the following features:•Microcontroller interface•Multi-master bus contention detection and interrupt•Eight external slave selects•Four transfer protocols available with selectable clock polarity and clock phase•SPI transfer complete microcontroller interrupt•Four different bit rates available for SCKSignal Descriptions The 36 I/O signals of the CoolRunner-II CPLD SPI Master are described in Table1. Pin numbers have not been assigned to this design, this can be done to meet the system requirements of the designer.Table 1: CoolRunner-II SPI Master Signal DescriptionName Direction DescriptionMOSI Output SPI Serial Data Output. Serial data output from theSPI Master to a SPI slave.MISO Input SPI Serial Data Input. Serial data input from a SPIslave to the SPI Master.SS_IN_N Input SPI Slave Select Input. Active Low slave selectinput to the SPI Master. If this line is asserted, itindicates that another master on the bus was tryingto select this SPI Master as a SPI slave and thus buscontention can occur. Assertion of this line causesthe CoolRunner-II CPLD SPI Master to reset allcommunication and interrupt the μC.SS_N[7:0]Output SPI Slave Selects. Active Low slave select signalsto eight SPI slaves in the system.SCK Output SPI Serial Clock. Clock output selectable as 1/2,1/4, 1/8, or 1/16 of the system clock.ADDR[15:8]InputμC Address Bus. High byte address bus.ADDR_DATA[7:0]BidirectionalμC Multiplexed Address/Data Bus.ALE_N Input Address Latch Enable. Active Low μC controlsignal indicating that the data present on themultiplexed address/data bus is a valid address. PSEN_N Input Program Store Enable. Active Low μC controlsignal indicating that the current bus cycle is anaccess to the external program memory.RD_N Input Read Strobe. Active Low μC control signalindicating that the current bus cycle is a read cycle.XAPP386 (v1.0) December 12, 2002Using Xilinx CPLDs to Interface to a NAND Flash Memory DeviceAMD UltraNAND Memory DeviceThe AM30LV0064D is organized as 8 kB (+ 256 byte spare area) blocks (1,024 blocks total).Each block has 16 pages of 512 bytes (+ 16 bytes spare area) or 16,384 pages total. Figure2is a block diagram of the AMD UltraNAND device.Figure 2: AMD UltraNAND Block DiagramTable2 describes the AMD UltraNAND command set and functionality. The command registerdoes not occupy any addressable memory location. This register holds the command, alongwith any address and data information needed to execute the command. Programming datainto the Flash array is a two step process. The data to be programmed is loaded into the data XAPP354 (v1.1) September 30, 2002。

IntroductionThank you for designing with the Xilinx Virtex®-6 family of devices. Although Xilinx has made every effort to ensure the highest possible quality, the devices listed in Table 1 are subject to the limitations described in the following errata.DevicesThese errata apply to the devices shown in Table 1.Hardware Errata DetailsThis section provides a detailed description of each hardware issue known at the release time of this document.MMCMRestriction of Frequency Range for Bandwidth = HIGH or OPTIMIZEDWhen the Phase Frequency Detector (PFD) frequency (FIN/D) is lower than 135MHz and the BANDWIDTH attribute of the MMCM is set to HIGH or OPTIMIZED, a phase error between MMCM output clocks can occur, making the output clock signals invalid. This condition can also cause the fractional output counter to fail.The ISE® software v12.4 and later provides appropriate warnings for possible violations of this restriction.The ISE software v12.4 and later correctly handles designs set to OPTIMIZED bandwidth for all valid PFD frequencies.This issue will not be fixed in the devices listed in Table 1.Work-aroundPFD frequencies lower than 135MHz must use LOW bandwidth mode to ensure correct operation. See Answer Record 38132 for more information.Virtex-6 FPGA -1L Speed GradeLX75T, LX130T, LX195T, LX240T, LX365T,LX550T, LX760, SX315T, and SX475TProduction ErrataEN154 (v1.5) April 11, 2011Errata NotificationTable 1:Devices Affected by These ErrataDevicesXC6VLX75T JTAG ID (Revision Code): 4, 6XC6VLX130T JTAG ID (Revision Code): 4, 6XC6VLX195T JTAG ID (Revision Code): 4, 6XC6VLX240T JTAG ID (Revision Code): 4, 6XC6VLX365T JTAG ID (Revision Code): 0, 2XC6VLX550T JTAG ID (Revision Code): 0, 2XC6VLX760JTAG ID (Revision Code): 4, 6XC6VSX315T JTAG ID (Revision Code): 4, 6XC6VSX475TJTAG ID (Revision Code): 4, 6Packages All Speed Grades-1LRestriction of Clock Divider ValuesThe input clock divider (DIVCLK_DIVIDE) cannot have a value of 3 or 4 when the input clock frequency (F IN) of the MMCM is above 315MHz.The ISE software v12.4 and later provides appropriate warnings for possible violations of this restriction.This issue will not be fixed in the devices listed in Table1.Work-aroundIn all designs in which F IN is above 315MHz and DIVCLK_DIVIDE is set to 3 or 4, double the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values. See Answer Record 38133 for more information.Block RAMDual Port Block RAM Address Overlap in READ_FIRST and Simple Dual Port ModeWhen using the block RAM in True Dual Port (TDP) Read_First mode, Simple Dual Port (SDP) mode, or ECC mode with different clocks on ports A and B, the user must ensure certain addresses do not occur simultaneously on both ports when both ports are enabled and one port is being written to. Failure to observe this restriction can result in read and/or memory array corruption.The description is found in the Conflict Avoidance section in v1.3.1 (or later) of UG363, Virtex-6 FPGA Memory Resources User Guide.This description was originally added in UG363 (v1.1), published 9/16/09. This errata is being provided to highlight this change and ensure that all users are aware of this design restriction. The ISE v12.1 software and later provides appropriate warnings for possible violations of these restrictions.This issue will not be fixed in the devices listed in Table1.Work-aroundThe recommended work-around is to configure the block RAM in WRITE_FIRST mode. WRITE_FIRST mode is available in block RAMs configured in TDP mode in all ISE software versions. WRITE_FIRST mode is available in block RAMs configured in SDP mode from ISE v12.2 and later. See Answer Record 34859.Synchronous Built-in FIFOWhen using the Built-In FIFO as a Synchronous FIFO (EN_SYN=TRUE) with asynchronous reset, correct behavior of the FIFO flags cannot be guaranteed after the first write.All configurations other than EN_SYN=TRUE are not affected by this issue.Work-aroundsTo work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.For more information and additional work-arounds see Answer Record 41099.ConfigurationPROGRAM_B Pin Behavior During Power-OnHolding the PROGRAM_B input statically Low prior to the completion of the power-on reset does not hold the FPGA in configuration reset. Instead, the FPGA proceeds with its standard power-on configuration sequence.This issue will not be fixed in the devices listed in Table1.Work-aroundFor systems that need to delay the FPGA configuration sequence at power-on, hold the INIT_B pin Low.See Answer Record 38134 for more information.RXRECCLK Static Operating BehaviorThe RXRECCLK output port might operate at reduced frequency in buffer bypass mode if conditions (1) and (2) persist for more than 15,000 cumulative hours at 65°C Tj, 2,500 cumulative hours at 85°C Tj, or 800 cumulative hours at 100°C Tj:1.Power has been applied to V CCINT.2.The device is in one of the following states:a.The FPGA is not configuredb.The FPGA is configured, but the transceiver is uninstantiatedc.The transceiver is instantiated, but no reference clock is togglingd.The transceiver is instantiated, but is held in reset or power-downWork-aroundTransceivers Uninstantiated in User Design but are Planned to be Used in the FutureFor transceivers that are not instantiated in the user design but are planned to be used in the future, power must be applied to MGTAVCC, and the user design must be implemented using ISE v12.1 (or later) software for automatic insertion of the work-around circuit.Transceivers Uninstantiated in User Design but are Not Planned to be Used in the FutureAutomatic insertion of the work-around circuit can be disabled for uninstantiated transceivers that will not beused..Date Version Description07/30/10 1.0Initial Xilinx release.09/21/10 1.1Added the LX75T device to the document, which includes an update to T able1. Added System Monitor Maximum DCLK Frequency. Updated System Monitor Internal Reference Voltage.11/16/10 1.2Updated JT AG ID Revision Codes in Table1. Added Restriction of Frequency Range for Bandwidth = HIGH or OPTIMIZED, Restriction of Clock Divider Values, PROGRAM_B Pin Behavior During Power-On,Configuration Switching Characteristics, and GTX T ransceiver Initialization for Proper TXOUTCLKFunctionality.12/23/10 1.3Added the following devices to the document, including an update to Table1: LX365T, LX550T, LX760, SX315T, and SX475T.01/17/11 1.4Updated TXOUTCLK and RXRECCLK Static Operating Behavior; no longer applicable to TXOUTCLK.Added GTX T ransceiver Delay Aligner per Xilinx Customer Notice XCN11009.04/11/11 1.5Added Synchronous Built-in FIFO and Input Logic Resets Using GSR.。

Chapter 1:Packaging OverviewPin DefinitionsTable1-7 lists the pin definitions used in Virtex-5 FPGA packages. Table 1-7:Virtex-5 FPGA Pin DefinitionsPin Name Direction DescriptionUser I/O PinsIO_LXXY_#Input/OutputAll user I/O pins are capable of differential signaling and can implement pairs.Each user I/O is labeled “IO_LXXY_#”, where:IO indicates a user I/O pin.LXXY indicates a differential pair, with XX a unique pair in the bank and Y =[P|N] for the positive/negative sides of the differential pair.Multi-Function PinsIO_LXXY_ZZZ_#Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZ represents one or more of the following functions in addition to being general purpose user I/O. If not used for their special function, these pins can be user I/O.DnInput In SelectMAP mode, D0 through D31 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained.ADDRnOutput ADDR0–ADDR25 BPI address output. These pins become user I/O after configuration.RSn Output RS0 and RS1 revision select output. FCS_B Output BPI and SPI flash chip select.FOE_B Output BPI flash output enable.FWE_B Output BPI flash write enable.MOSI Output SPI flash data output enable.CSO_B Output Parallel daisy chain chip select. FSn Input FS0–FS2 SPI Flash vendor selection.CCInput These clock pins connect to Clock Capable I/Os. These pins become regular user I/Os when not needed for clocks. If a single-ended clock is connected to the differential CC pair of pins, it must be connected to the positive (P) side of the pair. Clock capable I/Os in the center column can not drive BUFRs.GCInput These clock pins connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. If a single-ended clock is connected to the differential GC pair of pins, it must be connected to the positive (P) side of the pair.SMnP/SMnN Input System Monitor analog inputs.VREFN/A These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank).VRNN/A This pin is for the DCI voltage reference resistor of N transistor (per bank, to be pulled High with reference resistor).VRPN/A This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with reference resistor).Pin DefinitionsDedicated Configuration Pins (1)CCLK_0Input/OutputConfiguration clock. Output and input in Master mode or Input in Slave mode.CS_B_0Input In SelectMAP mode, this is the active-low Chip Select signal. D_IN_0Input In bit-serial modes, D_IN is the single-data input.DONE_0Input/OutputDONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence.D_OUT_BUSY_0OutputIn SelectMAP mode, BUSY controls the rate at which configuration data is loaded.In bit-serial modes, DOUT gives preamble and configuration data to down-stream devices in a daisy chain.Table 1-7:Virtex-5 FPGA Pin Definitions (Continued)Pin NameDirectionDescriptionFF324 Package—LX30 and LX50Table 2-2:FF324 Package—LX30 and LX50 (Continued)Bank Pin Description Pin Number No Connect (NC) 12IO_L8P_CC_12 H612IO_L8N_CC_12(2)H512IO_L9P_CC_12 D212IO_L9N_CC_12(2)C212IO_L10P_CC_12 A112IO_L10N_CC_12(2)A212IO_L11P_CC_12 G412IO_L11N_CC_12(2)F412IO_L12P_VRN_12 C112IO_L12N_VRP_12 B112IO_L13P_12 G312IO_L13N_12 F312IO_L14P_12 F112IO_L14N_VREF_12 E112IO_L15P_12 J512IO_L15N_12 J412IO_L16P_12 H312IO_L16N_12 J312IO_L17P_12 H212IO_L17N_12 J212IO_L18P_12 E212IO_L18N_12 F212IO_L19P_12 G112IO_L19N_12 H113IO_L0P_SM8P_13 K1513IO_L0N_SM8N_13 L1613IO_L1P_SM7P_13 L1713IO_L1N_SM7N_13 K1613IO_L2P_SM6P_13 K1413IO_L2N_SM6N_13 L1413IO_L3P_SM5P_13 M1813IO_L3N_SM5N_13 L1813IO_L4P_13 L1313IO_L4N_VREF_13 M1313IO_L5P_SM4P_13 P1813IO_L5N_SM4N_13 N1813IO_L6P_SM3P_13 M1413IO_L6N_SM3N_13 N1513IO_L7P_SM2P_13P17Table 2-2:FF324 Package—LX30 and LX50 (Continued)Bank Pin DescriptionPin NumberNo Connect (NC)NA MGTAVTTRX_125AM29NA MGTRXN0_125AP29NA MGTAVCCPLL_125AM26NA MGTRXN1_125AP28NA MGTREFCLKN_125AM28NA MGTRXP1_125AP27NA MGTREFCLKP_125AL28NA MGTTXN1_125AN27NA MGTTXP1_125AN26NAMGTTXP0_126AN4Table 2-7:FF1156 Package—TX150T (Continued)Bank Pin DescriptionPin NumberNo Connect (NC)。