AD408M94RTA-5中文资料

AD9959数据手册（部分）GENERALDESCRIPTION概述oa16-levelmodulationoffrequency,phase,oramplitude(FSK,PSK,ASK).Modulationisperformedb yapplyingdatatotheprofilepins.Inaddition,theAD9959alsosupportslinearsweepoffrequency,phase,or amplitudeforapplicationssuchasradarandinstrumentation.AD9959含有四个直接数字频率合成器（DDS），提供各通道独立的频率、相位和振幅控制。

这种灵活性可以用来纠正信号之间的不平衡，这种不平衡是由于模拟处理，如滤波，放大，或PCB布局相关的不匹配导致。

因为所有通道共用一个系统时钟，因此固有的同步。

也支持多个设备的同步。

AD9959可以执行16级频率、相位、振幅（FSK，PSK，ASK）调制，通过将数据传到配置引脚执行。

此外，AD9959还支持频率、线性扫频、相位或振幅的应用，如雷达和仪表。

TheAD9959serialI/Oportoffersmultipleconfigurationstoprovidesignificantflexibility.TheserialI/ OportoffersanSPI-compatiblemodeofoperationthatisvirtuallyidenticaltotheSPIoperationfoundinearl ierAnalogDevices,Inc.,DDSproducts.Flexibilityisprovidedbyfourdatapins(SDIO_0/SDIO_1/SDIO_2/S DIO_3)thatallowfourprogrammablemodesofserialI/Ooperation.AD9959的串行I/O端口提供了多种配置，提供显着的灵活性。

DDS模块设计DDS模块的设计是本系统的重点，也是本章阐述的重点。

DDS模块主要是围绕芯片AD9854进行设计的，设计要求既要满足性能指标，还要求优化电路，减小电路面积，否则13路DDS共同存在会使系统体积显得较大。

下面先介绍AD9854的基本特性。

4.2.1 AD9854介绍式参考时钟输入Ｄ更新读信号写信号行选择复位源地比较器输入模拟信号输出模拟信号输出比较器输出图4-2 AD9854功能结构框图chart4-2 AD9854 function and structure如图4-2所示，AD9854内部包括一个具有48位相位累加器、一个可编程时钟倍频器、一个反sinc滤波器、两个12位300MHz DAC，一个高速模拟比较器以及接口逻辑电路。

其主要性能特点如下：1.高达300MHz的系统时钟；2.能输出一般调制信号，FSK，BPSK，PSK，CHIRP，AM等；3.100MHz时具有80dB的信噪比；4.内部有4*到20*的可编程时钟倍频器；5.两个48位频率控制字寄存器，能够实现很高的频率分辨率。

6.两个14位相位偏置寄存器，提供初始相位设置。

7.带有100MHz的8位并行数据传输口或10MHz的串行数据传输口。

AD9854的芯片封装图如下：图4-3 AD9854芯片封装图chart4-3 AD9854 chip encapsulationAD9854有40个程序寄存器，对AD9854的控制就是对这些程序寄存器写数据实现的。

表4-1 AD9854并行接口寄存器功能并行地址寄存器功能默认值0x00 0x01 相位寄存器#1<13:8>(15,14位无效)相位寄存器#1<7:0>0x000x000x02 0x03 相位寄存器#2<13:8>(15,14位无效)相位寄存器#2<7:0>0x000x000x04 0x05 0x06 0x07 0x08 0x09 频率转换字#1<47:40>频率转换字#1<39:32>频率转换字#1<31:24>频率转换字#1<23:16>频率转换字#1<15:8>频率转换字#1<7:0>0x000x000x000x000x000x000x0A 频率转换字#1<47:40> 0x00表4-2 AD9854控制寄存器功能通过并行总线将数据写入程序寄存器时，实际上只是暂存在I/O缓冲区中，只有提供更新信号，这些数据才会更新到程序寄存器。

REV.AInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aLC 2MOS 4-/8-ChannelHigh Performance Analog MultiplexersADG408/ADG409FEATURES44 V Supply Maximum Ratings V SS to V DD Analog Signal Range Low On Resistance (100 ⍀ max)Low Power (I SUPPLY < 75 ␮A)Fast SwitchingBreak-Before-Make Switching Action Plug-in Replacement for DG408/DG409APPLICATIONSAudio and Video Routing Automatic Test Equipment Data Acquisition Systems Battery Powered Systems Sample and Hold Systems Communication Systems GENERAL DESCRIPTIONThe ADG408 and ADG409 are monolithic CMOS analogmultiplexers comprising eight single channels and four differen-tial channels respectively. The ADG408 switches one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1 and A2. The ADG409 switches one of four differential inputs to a common differential output as deter-mined by the 2-bit binary address lines A0 and A1. An EN input on both devices is used to enable or disable the device.When disabled, all channels are switched OFF.The ADG408/ADG409 are designed on an enhanced LC 2MOS process which provides low power dissipation yet gives high switching speed and low on resistance. Each channel conducts equally well in both directions when ON and has an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.The ADG408/ADG409 are improved replacements for the DG408/DG409 Analog Multiplexers.PRODUCT HIGHLIGHTS1.Extended Signal RangeThe ADG408/ADG409 are fabricated on an enhanced LC 2MOS process giving an increased signal range that extends to the supply rails.2.Low Power Dissipation 3Low R ON4.Single Supply OperationFor applications where the analog signal is unipolar, the ADG408/ADG409 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and will remain functional with single supplies as low as +5 V.FUNCTIONAL BLOCK DIAGRAMSOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 1998ADG408/ADG409–SPECIFICATIONSDUAL SUPPLY 1B VersionT Version–40؇C to–55؇C toParameter+25؇C +85؇C+25؇C +125؇CUnits Test Conditions/CommentsANALOG SWITCH Analog Signal Range V SS to V DD V SS to V DD VR ON 4040Ω typV D = ±10 V, I S = –10 mA 100125100125Ω max∆R ON1515Ω max V D = +10 V, –10 V LEAKAGE CURRENTSSource OFF Leakage I S (OFF)±0.5±50±0.5±50nA max V D = ±10 V, V S = ϯ10 V;Test Circuit 2Drain OFF Leakage I D (OFF)V D = ±10 V; V S = ϯ10 V;ADG408±1±100±1±100nA max Test Circuit 3ADG409±1±50±1±50nA max Channel ON Leakage I D , I S (ON)V S = V D = ±10 V;ADG408±1±100±1±100nA max Test Circuit 4ADG409±1±50±1±50nA max DIGITAL INPUTSInput High Voltage, V INH 2.4 2.4V min Input Low Voltage, V INL 0.80.8V max Input Current I INL or I INH±10±10µA max V IN = 0 or V DD C IN , Digital Input Capacitance 88pF typ f = 1 MHzDYNAMIC CHARACTERISTICS 2t TRANSITION 120120ns typ R L = 300 Ω, C L = 35 pF;250250ns max V S1 = ±10 V, V SS = ϯ10 V;Test Circuit 5t OPEN 10101010ns min R L = 300 Ω, C L = 35 pF;V S = +5 V; Test Circuit 6t ON (EN)8512585125ns typ R L = 300 Ω, C L = 35 pF;150225150225ns max V S = +5 V; Test Circuit 7t OFF (EN)6565ns typ R L = 300 Ω, C L = 35 pF;150150ns max V S = +5 V; Test Circuit 7Charge Injection 2020pC typ V S = 0 V, R S = 0 Ω, C L = 10 nF;Test Circuit 8OFF Isolation–75–75dB typ R L = 1 k Ω, f = 100 kHz;V EN = 0 V; Test Circuit 9Channel-to-Channel Crosstalk 8585dB typ R L = 1 k Ω, f = 100 kHz;Test Circuit 10C S (OFF)1111pF typ f = 1 MHz C D (OFF) f = 1 MHz ADG4084040pF typ ADG4092020pF typC D , C S (ON) f = 1 MHzADG4085454pF typ ADG4093434pF typPOWER REQUIREMENTS I DD 11µA typ V IN = 0 V, V EN = 0 V55µA max I SS 11µA typ 55µA max I DD100100µA typ V IN = 0 V, V EN = 2.4 V200500200500µA maxNOTES 1Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.2Guaranteed by design, not subject to production test.Specifications subject to change without notice.REV. A–2–(V DD = +15 V, V SS = –15 V, GND = 0 V, unless otherwise noted)ADG408/ADG409 SINGLE SUPPLY1(V DD = +12 V, V SS = 0 V, GND = 0 V, unless otherwise noted)B Version T Version–40؇C to–55؇C toParameter+25؇C+85؇C+25؇C+125؇C Units Test Conditions/Comments ANALOG SWITCHAnalog Signal Range0 to V DD0 to V DD VR ON9090Ω typ V D = +3 V, +10 V, I S = –1 mA LEAKAGE CURRENTSSource OFF Leakage I S (OFF)±0.5±50±0.5±50nA max V D =8 V/0 V, V S = 0 V/8V;Test Circuit 2Drain OFF Leakage I D (OFF)V D =8 V/0 V, V S = 0 V/8V;ADG408±1±100±1±100nA max Test Circuit 3ADG409±1±50±1±50nA maxChannel ON Leakage I D, I S (ON)V S = V D = 8 V/0 V;ADG408±1±100±1±100nA max Test Circuit 4ADG409±1±50±1±50nA maxDIGITAL INPUTSInput High Voltage, V INH 2.4 2.4V minInput Low Voltage, V INL0.80.8V maxInput CurrentI INL or I INH±10±10µA max V IN = 0 or V DDC IN, Digital Input Capacitance88pF typ f = 1 MHzDYNAMIC CHARACTERISTICS2t TRANSITION130130ns typ R L = 300 Ω, C L = 35 pF;V S1 = 8 V/0 V, V S8 = 0 V/8 V;Test Circuit 5t OPEN1010ns typ R L = 300 Ω, C L = 35 pF;V S = +5 V; Test Circuit 6t ON (EN)140140ns typ R L = 300 Ω, C L = 35 pF;V S = +5 V; Test Circuit 7t OFF (EN)6060ns typ R L = 300 Ω, C L = 35 pF;V S = +5 V; Test Circuit 7 Charge Injection55pC typ V S = 0 V, R S = 0 Ω, C L = 10 nF;Test Circuit 8OFF Isolation–75–75dB typ R L = 1 kΩ, f = 100 kHz;V EN = 0 V; Test Circuit 9 Channel-to-Channel Crosstalk8585dB typ R L = 1 kΩ, f = 100 kHz;Test Circuit 10C S (OFF)1111pF typ f = 1 MHzC D (OFF) f = 1 MHzADG4084040pF typADG4092020pF typC D, C S (ON) f = 1 MHzADG4085454pF typADG4093434pF typPOWER REQUIREMENTSI DD11µA typ V IN = 0 V, V EN = 0 V55µA maxI DD100100µA typ V IN = 0 V, V EN = 2.4 V200500200500µA maxNOTES1Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.2Guaranteed by design, not subject to production test.Specifications subject to change without notice.REV. A–3–ADG408/ADG409REV. A–4–ABSOLUTE MAXIMUM RATINGS 1(T A = +25°C unless otherwise noted)V DD to V SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V V DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +25 V V SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –25 V Analog, Digital Inputs 2 . . . . .V SS –2 V to V DD +2 V or 20 mA,Whichever Occurs FirstContinuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20 mA Peak Current, S or D(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . .40 mA Operating Temperature RangeIndustrial (B Version) . . . . . . . . . . . . . . . . .–40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . .–55°C to +125°C Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .900 mW θJA , Thermal Impedance . . . . . . . . . . . . . . . . . . . . .76°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+300°C Plastic Package, Power Dissipation . . . . . . . . . . . . . . .470 mW θJA , Thermal Impedance . . . . . . . . . . . . . . . . . . . .117°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . .+260°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . .450 mW θJA , Thermal Impedance . . . . . . . . . . . . . . . . . . . .155°C/W θJC , Thermal Impedance . . . . . . . . . . . . . . . . . . . . .50°C/W SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .600 mW θJA , Thermal Impedance . . . . . . . . . . . . . . . . . . . . .77°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°CNOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.2Overvoltages at A, EN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.ORDERING INFORMATIONModel 1Temperature Range Package Option 2ADG408BN –40°C to +85°C N-16ADG408BR –40°C to +85°C R-16A ADG408BRU –40°C to +85°C RU-16ADG408TQ –55°C to +125°C Q-16ADG409BN –40°C to +85°C N-16ADG409BR –40°C to +85°C R-16A ADG409TQ–55°C to +125°CQ-16NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.2N = Plastic DIP; Q = Cerdip; R = 0.15" Small Outline IC (SOIC);RU = Think Shrink Small Outline Package (TSSOP).CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test eq uipment and can discharge without detection.Although the ADG408/ADG409 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ADG408/ADG409REV. A –5–TERMINOLOGYV DD Most positive power supply potential.V SSMost negative power supply potential in dual supplies. In single supply applications, it may be connected to ground.GND Ground (0 V) reference.R ON Ohmic resistance between D and S.∆R ON Difference between the R ON of any two channels.I S (OFF)Source leakage current when the switch is off.I D (OFF)Drain leakage current when the switch is off.I D , I S (ON)Channel leakage current when the switch is on.V D (V S )Analog voltage on terminals D, S.C S (OFF)Channel input capacitance for “OFF”condition.C D (OFF)Channel output capacitance for “OFF”condition.C D , C S (ON)“ON” switch capacitance.C IN Digital input capacitance.t ON (EN)Delay time between the 50% and 90% points of the digital input and switch “ON” condition.t OFF (EN)Delay time between the 50% and 90% points of the digital input and switch “OFF” condition.t TRANSITIONDelay time between the 50% and 90% points of the digital inputs and the switch “ON” condition when switching from one address state to another.t OPEN“OFF” time measured between the 80% point of both switches when switching from one address state to another.V INL Maximum input voltage for Logic “0.”V INH Minimum input voltage for Logic “1.”I INL (I INH )Input current of the digital input.CrosstalkA measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance.Off Isolation A measure of unwanted signal coupling through an “OFF” channel.Charge A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.I DD Positive supply current.I SSNegative supply current.PIN CONFIGURATIONS (DIP/SOIC/TSSOP)A0EN V SS S1S2S3S4D A1A2GNDV DD S5S6S7S8V DDADG408 Truth TableONA2A1A0EN SWITCH X X X 0NONE 0001100112010130111410015101161101711118ADG409 Truth TableON SWITCH Al A0EN PAIR X X 0NONE 0011011210131114ADG408/ADG409REV. A–6–Typical Performance CharacteristicsV D (V S ) – VoltsR O N – ⍀Figure 1.R ON as a Function of V D (V S ): Dual Supply VoltageV D (V S ) – Volts10030R O N – ⍀807050406090Figure 2.R ON as a Function of V D (V S ) for Different Temperatures V D (V S ) – Volts0.2–0.2L E A K A G E C U R R E N T – n A–0.10.1Figure 3.Leakage Currents as a Function of V D (V S )V D (V S ) – Volts18040R O N – ⍀1401208060160100Figure 4.R ON as a Function of V D (V S ): Single Supply VoltageV D (V S ) – Volts13060R O N – ⍀100807090120110Figure 5.R ON as a Function of V D (V S ) for Different TemperaturesV D (V S) – VoltsL E A K A G E C U R R E N T – n AFigure 6.Leakage Currents as a Function of V D (V S )ADG408/ADG409REV. A –7–V IN – Volts12020t – n s604010080Figure 7.Switching Time vs. V IN (Bipolar Supply)V SUPPLY – Volts400t – n s200100300Figure 8.Switching Time vs. Single Supply FREQUENCY – Hz104103102I D D – ␮A10M101001k 10k 100k 1MFigure 9.Positive Supply Current vs. Switching FrequencyV IN – Voltst – n sFigure 10.Switching Time vs. V IN(Single Supply)V SUPPLY – Volts3000t – n s200100Figure 11.Switching Time vs. Bipolar SupplyFREQUENCY – Hz10410310–110M1M 10I S S – ␮A1001k 10k 100k 102101100Figure 12.Negative Supply Current vs. Switching FrequencyADG408/ADG409REV. A–8–FREQUENCY – Hz11070O F F I S O L A T I O N – d B9080100Figure 13.Off Isolation vs. Frequency FREQUENCY – Hz11070C R O S S T A L K – d B908010060Figure 14.Crosstalk vs. FrequencyTest CircuitsI V Test Circuit 1.On ResistanceV I S Test Circuit 2.I S(OFF)V V V (OFF)Test Circuit 3.I D (OFF)V V V (ON)Test Circuit 4. I D (ON)ADG408/ADG409REV. A –9–VVV 35pFTest Circuit 5.Switching Time of Multiplexer, t TRANSlTlONVVV Test Circuit 6.Break-Before-Make Delay, tOPENV V35pFV 3V 0VTest Circuit 7. Enable Delay, t ON (EN), t OFF (EN)ADG408/ADG409REV. A–10–VVOUT 3VV INVTest Circuit 8.Charge InjectionV OUTV OFF ISOLATION = 20 LOG V OUT /V IN Test Circuit 9.OFF Isolation VV OUTOUT INTest Circuit 10.Channel-to-Channel CrosstalkADG408/ADG409REV. A –11–OUTLINE DIMENSIONSDimensions shown in inches and (mm).Plastic DIP (N-16)Cerdip (Q-16)BSCSO (Narrow Body) (R-16A)°Thin Shrink Small Outline Package (TSSOP)(RU-16)PLANE BSC(1.10)MAX0.0035 (0.090)C 1824a –0–4/98P R I N T E D I N U .S .A .。

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .General DescriptionThe MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 are low-power transceivers for RS-485 and RS-422 communication. Each part contains one driver and one receiver. The MAX483, MAX487, MAX488, and MAX489feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables,thus allowing error-free data transmission up to 250kbps.The driver slew rates of the MAX481, MAX485, MAX490,MAX491, and MAX1487 are not limited, allowing them to transmit up to 2.5Mbps.These transceivers draw between 120µA and 500µA of supply current when unloaded or fully loaded with disabled drivers. Additionally, the MAX481, MAX483, and MAX487have a low-current shutdown mode in which they consume only 0.1µA. All parts operate from a single 5V supply.Drivers are short-circuit current limited and are protected against excessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-imped-ance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.The MAX487 and MAX1487 feature quarter-unit-load receiver input impedance, allowing up to 128 MAX487/MAX1487 transceivers on the bus. Full-duplex communi-cations are obtained using the MAX488–MAX491, while the MAX481, MAX483, MAX485, MAX487, and MAX1487are designed for half-duplex applications.________________________ApplicationsLow-Power RS-485 Transceivers Low-Power RS-422 Transceivers Level TranslatorsTransceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks__Next Generation Device Features♦For Fault-Tolerant ApplicationsMAX3430: ±80V Fault-Protected, Fail-Safe, 1/4Unit Load, +3.3V, RS-485 TransceiverMAX3440E–MAX3444E: ±15kV ESD-Protected,±60V Fault-Protected, 10Mbps, Fail-Safe, RS-485/J1708 Transceivers♦For Space-Constrained ApplicationsMAX3460–MAX3464: +5V, Fail-Safe, 20Mbps,Profibus RS-485/RS-422 TransceiversMAX3362: +3.3V, High-Speed, RS-485/RS-422Transceiver in a SOT23 PackageMAX3280E–MAX3284E: ±15kV ESD-Protected,52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422,True Fail-Safe ReceiversMAX3293/MAX3294/MAX3295: 20Mbps, +3.3V,SOT23, RS-855/RS-422 Transmitters ♦For Multiple Transceiver ApplicationsMAX3030E–MAX3033E: ±15kV ESD-Protected,+3.3V, Quad RS-422 Transmitters ♦For Fail-Safe ApplicationsMAX3080–MAX3089: Fail-Safe, High-Speed (10Mbps), Slew-Rate-Limited RS-485/RS-422Transceivers♦For Low-Voltage ApplicationsMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E: +3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited,True RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________Selection Table19-0122; Rev 8; 10/03Ordering Information appears at end of data sheet.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSSupply Voltage (V CC ).............................................................12V Control Input Voltage (RE , DE)...................-0.5V to (V CC + 0.5V)Driver Input Voltage (DI).............................-0.5V to (V CC + 0.5V)Driver Output Voltage (A, B)...................................-8V to +12.5V Receiver Input Voltage (A, B).................................-8V to +12.5V Receiver Output Voltage (RO).....................-0.5V to (V CC +0.5V)Continuous Power Dissipation (T A = +70°C)8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)..800mW 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 8-Pin µMAX (derate 4.1mW/°C above +70°C)..............830mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 14-Pin CERDIP (derate 9.09mW/°C above +70°C).......727mW Operating Temperature RangesMAX4_ _C_ _/MAX1487C_ A...............................0°C to +70°C MAX4__E_ _/MAX1487E_ A.............................-40°C to +85°C MAX4__MJ_/MAX1487MJA...........................-55°C to +125°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10sec).............................+300°CDC ELECTRICAL CHARACTERISTICS(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V V IN = -7VV IN = 12V V IN = -7V V IN = 12V Input Current (A, B)I IN2V TH k Ω48-7V ≤V CM ≤12V, MAX487/MAX1487R INReceiver Input Resistance -7V ≤V CM ≤12V, all devices except MAX487/MAX1487R = 27Ω(RS-485), Figure 40.4V ≤V O ≤2.4VR = 50Ω(RS-422)I O = 4mA, V ID = -200mV I O = -4mA, V ID = 200mV V CM = 0V-7V ≤V CM ≤12V DE, DI, RE DE, DI, RE MAX487/MAX1487,DE = 0V, V CC = 0V or 5.25VDE, DI, RE R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4R = 27Ωor 50Ω, Figure 4DE = 0V;V CC = 0V or 5.25V,all devices except MAX487/MAX1487CONDITIONSk Ω12µA ±1I OZRThree-State (high impedance)Output Current at ReceiverV 0.4V OL Receiver Output Low Voltage 3.5V OH Receiver Output High Voltage mV 70∆V TH Receiver Input Hysteresis V -0.20.2Receiver Differential Threshold Voltage-0.2mA 0.25mA-0.81.01.55V OD2Differential Driver Output (with load)V 2V 5V OD1Differential Driver Output (no load)µA±2I IN1Input CurrentV 0.8V IL Input Low Voltage V 2.0V IH Input High Voltage V 0.2∆V OD Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States V 0.2∆V OD Change in Magnitude of Driver Differential Output Voltage for Complementary Output States V 3V OC Driver Common-Mode Output VoltageUNITS MINTYPMAX SYMBOL PARAMETERMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________3SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)DC ELECTRICAL CHARACTERISTICS (continued)(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)ns 103060t PHLDriver Rise or Fall Time Figures 6 and 8, R DIFF = 54Ω, C L1= C L2= 100pF ns MAX490M, MAX491M MAX490C/E, MAX491C/E2090150MAX481, MAX485, MAX1487MAX490M, MAX491MMAX490C/E, MAX491C/E MAX481, MAX485, MAX1487Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pF MAX481 (Note 5)Figures 5 and 11, C RL = 15pF, S2 closedFigures 5 and 11, C RL = 15pF, S1 closed Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFFigures 6 and 8,R DIFF = 54Ω,C L1= C L2= 100pF Figures 6 and 10,R DIFF = 54Ω,C L1= C L2= 100pF CONDITIONS ns 510t SKEW ns50200600t SHDNTime to ShutdownMbps 2.5f MAX Maximum Data Rate ns 2050t HZ Receiver Disable Time from High ns 103060t PLH 2050t LZ Receiver Disable Time from Low ns 2050t ZH Driver Input to Output Receiver Enable to Output High ns 2050t ZL Receiver Enable to Output Low 2090200ns ns 134070t HZ t SKD Driver Disable Time from High |t PLH - t PHL |DifferentialReceiver Skewns 4070t LZ Driver Disable Time from Low ns 4070t ZL Driver Enable to Output Low 31540ns51525ns 31540t R , t F 2090200Driver Output Skew to Output t PLH , t PHL Receiver Input to Output4070t ZH Driver Enable to Output High UNITS MIN TYP MAX SYMBOL PARAMETERFigures 7 and 9, C L = 100pF, S2 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 7 and 9, C L = 15pF, S1 closed Figures 7 and 9, C L = 15pF, S2 closedM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 4_______________________________________________________________________________________SWITCHING CHARACTERISTICS—MAX483, MAX487/MAX488/MAX489(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (continued)(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)3001000Figures 7 and 9, C L = 100pF, S2 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 5 and 11, C L = 15pF, S2 closed,A - B = 2VCONDITIONSns 40100t ZH(SHDN)Driver Enable from Shutdown toOutput High (MAX481)nsFigures 5 and 11, C L = 15pF, S1 closed,B - A = 2Vt ZL(SHDN)Receiver Enable from Shutdownto Output Low (MAX481)ns 40100t ZL(SHDN)Driver Enable from Shutdown toOutput Low (MAX481)ns 3001000t ZH(SHDN)Receiver Enable from Shutdownto Output High (MAX481)UNITS MINTYP MAX SYMBOLPARAMETERt PLH t SKEW Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFt PHL Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFDriver Input to Output Driver Output Skew to Output ns 100800ns ns 2000MAX483/MAX487, Figures 7 and 9,C L = 100pF, S2 closedt ZH(SHDN)Driver Enable from Shutdown to Output High2502000ns2500MAX483/MAX487, Figures 5 and 11,C L = 15pF, S1 closedt ZL(SHDN)Receiver Enable from Shutdown to Output Lowns 2500MAX483/MAX487, Figures 5 and 11,C L = 15pF, S2 closedt ZH(SHDN)Receiver Enable from Shutdown to Output Highns 2000MAX483/MAX487, Figures 7 and 9,C L = 100pF, S1 closedt ZL(SHDN)Driver Enable from Shutdown to Output Lowns 50200600MAX483/MAX487 (Note 5) t SHDN Time to Shutdownt PHL t PLH , t PHL < 50% of data period Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 5 and 11, C RL = 15pF, S2 closed Figures 5 and 11, C RL = 15pF, S1 closed Figures 7 and 9, C L = 15pF, S2 closed Figures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFFigures 7 and 9, C L = 15pF, S1 closed Figures 7 and 9, C L = 100pF, S1 closed Figures 7 and 9, C L = 100pF, S2 closed CONDITIONSkbps 250f MAX 2508002000Maximum Data Rate ns 2050t HZ Receiver Disable Time from High ns 25080020002050t LZ Receiver Disable Time from Low ns 2050t ZH Receiver Enable to Output High ns 2050t ZL Receiver Enable to Output Low ns ns 1003003000t HZ t SKD Driver Disable Time from High I t PLH - t PHL I DifferentialReceiver SkewFigures 6 and 10, R DIFF = 54Ω,C L1= C L2= 100pFns 3003000t LZ Driver Disable Time from Low ns 2502000t ZL Driver Enable to Output Low ns Figures 6 and 8, R DIFF = 54Ω,C L1= C L2= 100pFns 2502000t R , t F 2502000Driver Rise or Fall Time ns t PLH Receiver Input to Output2502000t ZH Driver Enable to Output High UNITS MIN TYP MAX SYMBOL PARAMETERMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________530002.5OUTPUT CURRENT vs.RECEIVER OUTPUT LOW VOLTAGE525M A X 481-01OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )1.515100.51.02.0203540450.90.1-50-252575RECEIVER OUTPUT LOW VOLTAGE vs.TEMPERATURE0.30.7TEMPERATURE (°C)O U T P U TL O W V O L T A G E (V )500.50.80.20.60.40100125-20-41.5 2.0 3.0 5.0OUTPUT CURRENT vs.RECEIVER OUTPUT HIGH VOLTAGE-8-16M A X 481-02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )2.5 4.0-12-18-6-14-10-203.54.5 4.83.2-50-252575RECEIVER OUTPUT HIGH VOLTAGE vs.TEMPERATURE3.64.4TEMPERATURE (°C)O U T P UT H I G H V O L T A G E (V )0504.04.63.44.23.83.01001259000 1.0 3.0 4.5DRIVER OUTPUT CURRENT vs.DIFFERENTIAL OUTPUT VOLTAGE1070M A X 481-05DIFFERENTIAL OUTPUT VOLTAGE (V)O U T P U T C U R R E N T (m A )2.0 4.05030806040200.5 1.5 2.53.5 2.31.5-50-2525125DRIVER DIFFERENTIAL OUTPUT VOLTAGEvs. TEMPERATURE1.72.1TEMPERATURE (°C)D I F FE R E N T I A L O U T P U T V O L T A G E (V )751.92.21.62.01.8100502.4__________________________________________Typical Operating Characteristics(V CC = 5V, T A = +25°C, unless otherwise noted.)NOTES FOR ELECTRICAL/SWITCHING CHARACTERISTICSNote 1:All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to deviceground unless otherwise specified.Note 2:All typical specifications are given for V CC = 5V and T A = +25°C.Note 3:Supply current specification is valid for loaded transmitters when DE = 0V.Note 4:Applies to peak current. See Typical Operating Characteristics.Note 5:The MAX481/MAX483/MAX487 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for lessthan 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See Low-Power Shutdown Mode section.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 6___________________________________________________________________________________________________________________Typical Operating Characteristics (continued)(V CC = 5V, T A = +25°C, unless otherwise noted.)120008OUTPUT CURRENT vs.DRIVER OUTPUT LOW VOLTAGE20100M A X 481-07OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )6604024801012140-1200-7-5-15OUTPUT CURRENT vs.DRIVER OUTPUT HIGH VOLTAGE-20-80M A X 481-08OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )-31-603-6-4-2024-100-40100-40-60-2040100120MAX1487SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )20608050020060040000140100-50-2550100MAX481/MAX485/MAX490/MAX491SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )257550020060040000125100-50-2550100MAX483/MAX487–MAX489SUPPLY CURRENT vs. TEMPERATURE300TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )257550020060040000125MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________7______________________________________________________________Pin DescriptionFigure 1. MAX481/MAX483/MAX485/MAX487/MAX1487 Pin Configuration and Typical Operating CircuitM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487__________Applications InformationThe MAX481/MAX483/MAX485/MAX487–MAX491 and MAX1487 are low-power transceivers for RS-485 and RS-422 communications. The MAX481, MAX485, MAX490,MAX491, and MAX1487 can transmit and receive at data rates up to 2.5Mbps, while the MAX483, MAX487,MAX488, and MAX489 are specified for data rates up to 250kbps. The MAX488–MAX491 are full-duplex trans-ceivers while the MAX481, MAX483, MAX485, MAX487,and MAX1487 are half-duplex. In addition, Driver Enable (DE) and Receiver Enable (RE) pins are included on the MAX481, MAX483, MAX485, MAX487, MAX489,MAX491, and MAX1487. When disabled, the driver and receiver outputs are high impedance.MAX487/MAX1487:128 Transceivers on the BusThe 48k Ω, 1/4-unit-load receiver input impedance of the MAX487 and MAX1487 allows up to 128 transceivers on a bus, compared to the 1-unit load (12k Ωinput impedance) of standard RS-485 drivers (32 trans-ceivers maximum). Any combination of MAX487/MAX1487 and other RS-485 transceivers with a total of 32 unit loads or less can be put on the bus. The MAX481/MAX483/MAX485 and MAX488–MAX491 have standard 12k ΩReceiver Input impedance.Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 8_______________________________________________________________________________________Figure 2. MAX488/MAX490 Pin Configuration and Typical Operating CircuitFigure 3. MAX489/MAX491 Pin Configuration and Typical Operating CircuitMAX483/MAX487/MAX488/MAX489:Reduced EMI and ReflectionsThe MAX483 and MAX487–MAX489 are slew-rate limit-ed, minimizing EMI and reducing reflections caused by improperly terminated cables. Figure 12 shows the dri-ver output waveform and its Fourier analysis of a 150kHz signal transmitted by a MAX481, MAX485,MAX490, MAX491, or MAX1487. High-frequency har-monics with large amplitudes are evident. Figure 13shows the same information displayed for a MAX483,MAX487, MAX488, or MAX489 transmitting under the same conditions. Figure 13’s high-frequency harmonics have much lower amplitudes, and the potential for EMI is significantly reduced.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers_______________________________________________________________________________________9_________________________________________________________________Test CircuitsFigure 4. Driver DC Test Load Figure 5. Receiver Timing Test LoadFigure 6. Driver/Receiver Timing Test Circuit Figure 7. Driver Timing Test LoadM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 10_______________________________________________________Switching Waveforms_________________Function Tables (MAX481/MAX483/MAX485/MAX487/MAX1487)Figure 8. Driver Propagation DelaysFigure 9. Driver Enable and Disable Times (except MAX488 and MAX490)Figure 10. Receiver Propagation DelaysFigure 11. Receiver Enable and Disable Times (except MAX488and MAX490)Table 1. TransmittingTable 2. ReceivingLow-Power Shutdown Mode (MAX481/MAX483/MAX487)A low-power shutdown mode is initiated by bringing both RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled.In shutdown, the devices typically draw only 0.1µA of supply current.RE and DE may be driven simultaneously; the parts are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 600ns, the parts are guaranteed to enter shutdown.For the MAX481, MAX483, and MAX487, the t ZH and t ZL enable times assume the part was not in the low-power shutdown state (the MAX485/MAX488–MAX491and MAX1487 can not be shut down). The t ZH(SHDN)and t ZL(SHDN)enable times assume the parts were shut down (see Electrical Characteristics ).It takes the drivers and receivers longer to become enabled from the low-power shutdown state (t ZH(SHDN ), t ZL(SHDN)) than from the operating mode (t ZH , t ZL ). (The parts are in operating mode if the –R —E –,DE inputs equal a logical 0,1 or 1,1 or 0, 0.)Driver Output ProtectionExcessive output current and power dissipation caused by faults or by bus contention are prevented by two mechanisms. A foldback current limit on the output stage provides immediate protection against short cir-cuits over the whole common-mode voltage range (see Typical Operating Characteristics ). In addition, a ther-mal shutdown circuit forces the driver outputs into a high-impedance state if the die temperature rises excessively.Propagation DelayMany digital encoding schemes depend on the differ-ence between the driver and receiver propagation delay times. Typical propagation delays are shown in Figures 15–18 using Figure 14’s test circuit.The difference in receiver delay times, | t PLH - t PHL |, is typically under 13ns for the MAX481, MAX485,MAX490, MAX491, and MAX1487 and is typically less than 100ns for the MAX483 and MAX487–MAX489.The driver skew times are typically 5ns (10ns max) for the MAX481, MAX485, MAX490, MAX491, and MAX1487, and are typically 100ns (800ns max) for the MAX483 and MAX487–MAX489.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________1110dB/div0Hz5MHz500kHz/div10dB/div0Hz5MHz500kHz/divFigure 12. Driver Output Waveform and FFT Plot of MAX481/MAX485/MAX490/MAX491/MAX1487 Transmitting a 150kHz SignalFigure 13. Driver Output Waveform and FFT Plot of MAX483/MAX487–MAX489 Transmitting a 150kHz SignalM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 12______________________________________________________________________________________V CC = 5V T A = +25°CV CC = 5V T A = +25°CV CC = 5V T A = +25°CV CC = 5V T A = +25°CFigure 14. Receiver Propagation Delay Test CircuitFigure 15. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PHLFigure 16. MAX481/MAX485/MAX490/MAX491/MAX1487Receiver t PLHPHL Figure 18. MAX483, MAX487–MAX489 Receiver t PLHLine Length vs. Data RateThe RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 23.Figures 19 and 20 show the system differential voltage for the parts driving 4000 feet of 26AWG twisted-pair wire at 110kHz into 120Ωloads.Typical ApplicationsThe MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 transceivers are designed for bidirectional data communications on multipoint bus transmission lines.Figures 21 and 22 show typical network applications circuits. These parts can also be used as line repeaters, with cable lengths longer than 4000 feet, as shown in Figure 23.To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possi-ble. The slew-rate-limited MAX483 and MAX487–MAX489are more tolerant of imperfect termination.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________13DIV Y -V ZRO5V 0V1V0V -1V5V 0V2µs/divFigure 19. MAX481/MAX485/MAX490/MAX491/MAX1487 System Differential Voltage at 110kHz Driving 4000ft of Cable Figure 20. MAX483, MAX487–MAX489 System Differential Voltage at 110kHz Driving 4000ft of CableFigure 21. MAX481/MAX483/MAX485/MAX487/MAX1487 Typical Half-Duplex RS-485 NetworkM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 14______________________________________________________________________________________Figure 22. MAX488–MAX491 Full-Duplex RS-485 NetworkFigure 23. Line Repeater for MAX488–MAX491Isolated RS-485For isolated RS-485 applications, see the MAX253 and MAX1480 data sheets.MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________15_______________Ordering Information_________________Chip TopographiesMAX481/MAX483/MAX485/MAX487/MAX1487N.C. RO 0.054"(1.372mm)0.080"(2.032mm)DE DIGND B N.C.V CCARE * Contact factory for dice specifications.__Ordering Information (continued)M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 16______________________________________________________________________________________TRANSISTOR COUNT: 248SUBSTRATE CONNECTED TO GNDMAX488/MAX490B RO 0.054"(1.372mm)0.080"(2.032mm)N.C. DIGND Z A V CCYN.C._____________________________________________Chip Topographies (continued)MAX489/MAX491B RO 0.054"(1.372mm)0.080"(2.032mm)DE DIGND Z A V CCYREMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers______________________________________________________________________________________17Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)S O I C N .E P SM A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 18______________________________________________________________________________________Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX481/MAX483/MAX485/MAX487–MAX491Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________19©2003 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.M A X 481/M A X 483/M A X 485/M A X 487–M A X 491/M A X 1487P D I P N .E PSPackage Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)。

ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。

ADI常用集成电路功能一览表序号型号产品描述1AD1380JD16位20us高性能模数转换器(民用级2AD1380KD16位20us高性能模数转换器(民用级3AD1671JQ12位1.25MHz采样速率带宽2MHz模数转换器(民用级4AD1672AP12位3MHz采样速率带宽20MHz单电源模数转换器(工业级5AD1674JN12位100KHz采样速率带宽500KHz模数转换器(民用级6AD1674AD12位100KHz采样速率带宽500KHz模数转换器(工业级7AD202JN小型2KHz隔离放大器(民用级卧式8AD202JY小型2KHz隔离放大器(民用级立式9AD204JN小型5KHz隔离放大器(民用级卧式10AD22100KT带信号调理比率输出型温度传感器11AD22105AR可编程温控开关电阻可编程温度控制器SOIC12AD261BND-1数字隔离放大器13AD2S99AP可编程正弦波振荡器(工业级PLCC14AD420AN-3216位单电源4-20mA输出数模转换器(工业级DIP15AD420AR-3216位单电源4-20mA输出数模转换器(工业级SOIC16AD421BN16位环路供电符合HART协议4-20mA输出数模转换器(工业级DIP 17AD421BR16位环路供电符合HART协议4-20mA输出数模转换器(工业级SOIC 18AD515AJH低价格,低偏置电流,高输入阻抗运放(民用级TO-9919AD515ALH低价格,低偏置电流,高输入阻抗运放(民用级TO-9920AD517JH低失调电压,高性能运放(民用级TO-9921AD518JH宽带,低价格运放(民用级TO-9922AD521JD电阻设置增益精密仪表放大器(民用级DIP23AD524AD引脚设置增益高精度仪表放大器(工业级DIP24AD526BD软件编程仪表放大器(工业级DIP25AD526JN软件编程仪表放大器(民用级DIP26AD532JH模拟乘法器(民用级TO-9927AD534JD模拟乘法器(民用级DIP28AD534JH模拟乘法器(民用级TO-9929AD536AJH集成真有效值直流转换器(民用级TO-9930AD536AJD集成真有效值直流转换器(民用级DIP31AD536AJQ集成真有效值直流转换器(民用级DIP32AD537JH150KHZ集成压频转换器(民用级TO-9933AD537SH150KHZ集成压频转换器(军用级TO-9934AD538AD单片实时模拟乘法器(工业级DIP35AD539JN宽带双通道线性乘法器(民用级DIP36AD542JH低价格,低偏置电流,高输入阻抗运放(民用级TO-9937AD545ALH低偏置电流,高输入阻抗运放(民用级TO-9938AD546JN静电计放大器(民用级DIP39AD547JH低价格,低偏置电流,高输入阻抗运放(民用级TO-99 40AD548JN精密BiFET输入运放(民用级DIP41AD549JH低偏置电流,高输入阻抗运放(民用级TO-9942AD549LH低偏置电流,高输入阻抗运放(民用级TO-9943AD5539JN高速运放(民用级DIP44AD557JN微处理器兼容完整7位电压输出数模转换器(民用DIP 45AD558JN 微处理器兼容完整8位电压输出数模转换器(民用DIP 46AD565AJD12位0.25us电流输出数模转换器(民用DIP47AD568JQ12位超高速电流输出数模转换器(民用DIP48AD569JN16位3us电流输出数模转换器(民用DIP49AD570JD/+8位25us模数转换器(民用DIP50AD574AJD12位25us模数转换器(民用DIP51AD574AKD12位25us模数转换器(民用DIP52AD578KN12位3us模数转换器(民用DIP53AD580JH精密 2.5V电压基准源(民用级TO-5254AD580LH精密 2.5V电压基准源(民用级TO-5255AD581JH精密10V电压基准源(民用级TO-556AD582KD0.7us采样保持放大器(民用DIP57AD584JH引脚设置输出电压基准源(民用级TO-99 58AD584JN引脚设置输出电压基准源(民用级DIP59AD585AQ3us采样保持放大器(工业级DIP60AD586JN精密5V电压基准源(民用级DIP61AD586JQ精密5V电压基准源(民用级DIP62AD586KN精密5V电压基准源(民用级DIP63AD586KQ精密5V电压基准源(民用级DIP64AD586KR精密5V电压基准源(民用级SOIC65AD587KN精密10V电压基准源(民用级DIP66AD587KR精密10V电压基准源(民用级SOIC67AD588AQ精密可编程电压基准源(工业级DIP68AD589JH精密 1.235V电压基准源(民用级H-02A 69AD590JH—55℃~150℃测温范围温度传感器TO-52 70AD590KH—55℃~150℃测温范围温度传感器TO-52 71AD592AN低价格,精密单片温度传感器TO-9272AD592BN低价格,精密单片温度传感器TO-9273AD595AD K型(铬-铝热电偶信号调节器(工业级DIP74AD595AQ K型(铬-铝热电偶信号调节器(工业级DIP75AD598AD线性可变位移信号调节器(LVDT(工业级DIP76AD600XN低噪声宽带可变增益双运放(民用级DIP77AD602JN低噪声宽带可变增益双运放(民用级DIP78AD603AQ低噪声可变增益运放(工业级DIP79AD606JN50MHz,80db对数放大器(民用级DIP80AD607ARS低功耗混频器/AGC/RSSC3V接收机的IF子系统(工业级SSOP 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184AD7542JN12位250ns电流输出CMOS数模转换器(民用级DIP 185AD7543KN12位串行输入CMOS数模转换器(民用级DIP186AD7545AKN12位1us电流输出CMOS数模转换器(民用级DIP 187AD7564BN低功耗四路数模转换器(工业级DIP188AD7574JN8位15us电流输出CMOS数模转换器(民用级DIP189AD7590DIKN四单刀单掷CMOS带锁存介质隔离模拟开关9民用级DIP 190AD7660AST16位100KSPS CMOS模数转换器(工业级LQFP191AD7664AST16位570KSPS CMOS模数转换器(工业级LQFP192AD767JN12位高速电压输出数模转换器(民用级DIP193AD768AR16位高速电流输出数模转换器(民用级SOIC194AD7701AN16位∑–△模数转换器(工业级DIP195AD7703AN20位∑–△模数转换器(工业级DIP196AD7703BN20位∑–△模数转换器(工业级DIP197AD7705BN16位∑–△模数转换器(工业级DIP198AD7705BR16位∑–△模数转换器(工业级SOIC199AD7706BN16位∑–△模数转换器(工业级DIP200AD7707BR16位∑–△模数转换器(工业级SOIC201AD7710AN24位∑–△模数转换器(工业级DIP202AD7711AN24位∑–△模数转换器(工业级DIP203AD7712AN24位∑–△模数转换器(工业级DIP204AD7713AN24位∑–△模数转换器(工业级DIP205AD7714AN-324位∑–△模数转换器(工业级DIP3V电源206AD7714AN-524位∑–△模数转换器(工业级DIP5V电源207AD7715AN-516位∑–△模数转换器(工业级DIP5V电源208AD7715AR-516位∑–△模数转换器(工业级SOIC5V电源209AD7731BN24位∑–△模数转换器(工业级DIP210AD7741BN单通道输入6MHz压频转换器(工业级DIP211AD7742BN四通道输入6MHz压频转换器(工业级DIP212AD7750AN两通道乘积/频率转换器电度表专用芯片(工业级DIP 213AD7755AARS IEC521/1036标准电度表专用芯片(工业级DIP214AD7777AR10位多路T/H子系统(工业级SOIC215AD779JD14位128KSPS采样速率并行输出模数转换器(民用级DIP 216AD780AN 2.5V或3V可选输出高精度电压基准源(工业级DIP217AD781JN700ns采样保持放大器(民用级DIP218AD7820KN8位500KSPS采样速率模数转换器(民用级DIP219AD7821KN8位1MSPS采样速率模数转换器(民用级DIP220AD7822BN8位2MSPS采样速率模数转换器(工业级DIP221AD7824BQ8位四通道高速模数转换器(民用级DIP222AD7824KN8位四通道高速模数转换器(工业级DIP223AD7837AN12位双路乘法数模转换器(工业级DIP224AD7845JN12位乘法数模转换器(民用级DIP225AD7846JN16位电压输出数模转换器(民用级DIP226AD7847AN12位双路乘法数模转换器(工业级DIP227AD7856AN14位8通道285KSPS采样速率模数转换器(工业级DIP228AD7862AN-1012位4通道同时采样250KSPS速率模数转换器带2SHA and2ADCs(工业级DIP 229AD7864AS-112位4通道同时采样147KSPS速率模数转换器(工业级PQFP230AD7865AS-114位4通道同时采样175KSPS速率模数转换器带2SHA and2ADCs(工业级PQFP 231AD7872AN14位串行输出模数转换器(工业级DIP232AD7891AP-112位四通道同时采样模数转换器(工业级DIP233AD7892AN-112位四通道同时采样模数转换器(工业级SOIC234AD7895AN-1012位750KSPS采样速率模数转换器(民用级DIP235AD7874AN12位750KSPS采样速率模数转换器(民用级DIP236AD7874BR12位8通道200KSPS速率模数转换器(工业级SOIC237AD7886JD12位单电源八通道串行采样模数转换器(工业级DIP238AD7886KD12位单电源八通道串并行采样模数转换器(工业级DIP239AD7888AR12位600KSPS采样模数转换器(工业级DIP240AD7890AN-1012位单电源200KSPS采样速率模数转换器(工业级DIP241AD790JN高速精密比较器(民用级DIP242AD795JN低偏置电流低噪声运放(民用级DIP243AD797AN低失真低噪声运放(工业级DIP244AD797AR低失真低噪声运放(工业级SOIC245AD73360AR16位6通道数据采集子系统(三相电量测量IC(工业级SOIC 246AD8001AN800MHz电流反馈运放(工业级DIP247AD8002AN800MHz电流反馈双运放(工业级DIP248AD8009AR1GHz4500V/us电流反馈双运放(工业级DIP249AD8011AN340MHz电流反馈运放(工业级DIP250AD8015AR单电源真空管前置放大器(工业级SOIC251AD8018AR5V Rail-Rail大电流输出XDSL线性驱动放大器(工业级SOIC 252AD8031AN单电源Rail-Rail输入输出运放(工业级DIP253AD8032AN单电源Rail-Rail输入输出双运放(工业级DIP254AD8036AN低失真宽带240MHz电压输出运放(工业级DIP255AD8037AN低失真宽带270MHz电压输出运放(工业级DIP256AD8041AN120MHz带宽Rail-Rail输出运放(工业级DIP257AD8041AR120MHz带宽Rail-Rail输出运放(工业级SOIC258AD8042AN120MHz带宽Rail-Rail输出双运放(工业级DIP259AD8044AN80MHz带宽Rail-Rail输出四运放(工业级DIP260AD8047AN电压反馈运放(工业级DIP261AD8055AR电压反馈运放(工业级SOIC262AD8056AR低价格300MHz电压反馈双运放(工业级SOIC263AD8058AR电压反馈双运放(工业级SOIC264AD8079AR双通道260MHz缓冲器(工业级SOIC265AD8108AST8×8视频距阵开关(工业级LQFP266AD8109AST8×8视频距阵开关(工业级LQFP267AD810AN带电源休眠控制端的低功耗视频运放(工业级DIP 268AD8111AST16×8视频距阵开关(工业级LQFP269AD8115AST16×16视频距阵开关(工业级LQFP270AD8116AST16×16视频距阵开关(工业级LQFP271AD811AN高性能视频运放(工业级DIP272AD811JR高性能视频运放(工业级SOIC273AD812AN低功耗电流反馈双运放(工业级DIP274AD812AR低功耗电流反馈双运放(工业级SOIC275AD8131AR差分输入输出电压反馈放大器(工业级SOIC 276AD8138AR IF放大器(工业级SOIC277AD813AN单电源低功耗三视频运放(工业级DIP278AD813AR-14单电源低功耗三视频运放(工业级SOIC279AD815AY大电流输出,差动输入\输出运放(工业级280AD8170AN2选1视频多路转换器(工业级DIP281AD8174AN4选1视频多路转换器(工业级DIP282AD817AN高速低功耗宽电源运放(工业级DIP283AD8180AN差动2选1视频多路转换器(工业级DIP284AD8184AN4选1视频多路转换器(工业级DIP285AD818AN低价格高速电压反馈视频运放(工业级DIP286AD820AN单电源低功耗FET输入Rail-Rail输出运放(工业级DIP 287AD822AN双AD820(工业级DIP288AD822AN-3V双AD820(工业级DIP3V电源289AD823AN单电源Rail-Rail输出双运放(工业级DIP290AD824AN单电源Rail-Rail输出四运放(工业级DIP291AD826AN高速低功耗双运放(工业级DIP292AD827AQ双AD847(工业级DIP293AD827JN双AD847(民用级DIP294AD828AN双AD818(工业级DIP295AD829JN高速低噪声视频运放(工业级DIP296AD8307AN500MHz对数放大器(工业级DIP297AD8307AR500MHz对数放大器(工业级SOIC298AD8309ARU500MHz对数放大器(工业级TSSOP299AD830AN高速视频差动运放(工业级DIP300AD8313ARM 2.5GHz对数放大器(工业级RM-8301AD830AN高速视频差动运放(工业级DIP302AD8313ARM 2.5GHz对数放大器(工业级RM-8303AD8320ARP数字可变增益线性驱动器(工业级RP-20304AD834JN500MHz带宽四象限模拟乘法器(工业级DIP305AD8350AR15差分输入射频放大器(工业级SOIC306AD835AN250MHz带宽四象限电压输出模拟乘法器(工业级DIP 307AD8402AN-102通道数字电位器阻值10K(工业级DIP308AD8403AN1004通道数字电位器阻值100K(工业级DIP309AD840JN宽带高速运放(民用级DIP310AD843AQ34MHz带宽高速FET输入运放(工业级DIP311AD844AN2000V/us高速运放(工业级DIP312AD845JN16MHz带宽高速FET输入运放(民用级DIP313AD845KN16MHz带宽高速FET输入运放(民用级DIP314AD847AQ300V/us高速低功耗运放(工业级DIP315AD847JN300V/us高速低功耗运放(民用级DIP316AD847SQ300V/us高速低功耗运放(军用级DIP317AD849JN高速低功耗运放(民用级DIP318AD8522AN12位单电源双路电流输出型数模转换器(工业级DIP 319AD8551AR自稳零运放(工业级SOIC320AD8552AR自稳零双运放(工业级SOIC321AD8561AN单电源比较器(工业级DIP322AD8561AR单电源比较器(工业级SOIC323AD8564AN单电源TTL/CMOS四路比较器(工业级DIP324AD8598AN单电源双路比较器(工业级DIP325AD9042AST12位41MSPS模数转换器(工业级LQFP326AD9048JQ8位35MSPS视频模数转换器(民用级DIP327AD9049BRS9位30MSPS模数转换器(工业级SSOP328AD9050BR10位40MSPS模数转换器(工业级SOIC329AD9051BRS10位60MSPS模数转换器(工业级SSOP330AD9057BRS-408位40MSPSz视频模数转换器(工业级SSOP 331AD9057BRS-608位60MSPS视频模数转换器(工业级SSOP 332AD9058JJ双路8位50MSPS视频模数转换器(民用级LCC 333AD9059BRS双路8位60MSPS视频模数转换器(工业级SSOP 334AD9066JR双路6位60MSPS视频模数转换器(民用级SSOP 335AD9071BR10位TTL兼容100MSPS模数转换器(工业级SOIC 336AD9101AR7ns建立时间采样保持放大器(工业级SOIC337AD9200ARS10位20MSPS模数转换器(工业级SSOP338AD9203ARU10位40MSPS模数转换器(工业级TSSOP339AD9220AR12位10MSPS模数转换器(工业级SOIC340AD9221AR12位1MSPS模数转换器(工业级SOIC341AD9223AR12位3MSPS模数转换器(工业级SOIC342AD9225AR12位25MSPS模数转换器(工业级SOIC343AD9226ARS12位65MSPS模数转换器(工业级SSOP344AD9240AS14位10MSPS模数转换器(工业级MQFP345AD9243AS14位3MSPS模数转换器(工业级MQFP346AD9260AS16位2.5MSPS∑–△模数转换器(工业级MQFP347AD9280ARS单电源8位32MSPS模数转换器(工业级SSOP348AD9281ARS单电源8位双路32MSPS模数转换器(工业级SSOP 349AD9283BRS-100单电源8位100MSPS模数转换器(工业级SSOP350AD9283BRS-80单电源8位80MSPS模数转换器(工业级SSOP351AD9288BRS-80单电源8位双路80MSPS模数转换器(工业级SSOP 352AD9300KQ4选1宽带视频多路转换器(民用级DIP353AD9483KS-1008位100MSPS三视频模数转换器(民用级MQFP354AD9500BQ数字化可编程延迟信号发生器(工业级DIP355AD9501JN TTL/COMS数字化可编程延迟信号发生器(民用级DIP356AD9617JR1400V/us,140MHz带宽高速运放(民用级SOIC357AD9617JN1400V/us,140MHz带宽高速运放(民用级DIP358AD9618JN1800V/us,160MHz带宽高速运放(民用级DIP359AD9630AN低失真闭环缓冲放大器(工业级DIP360AD9631AN超低失真宽带电压反馈放大器(工业级DIP361AD96687BQ高速双电压比较器(工业级DIP362AD9698KN高速TTL兼容双电压比较器(工业级DIP363AD9708ARU8位100MSPS双路数模转换器(工业级TSSOP364AD9709AST8位125MSPS双路数模转换器(工业级PQFP365AD9713BAN12位80MSPS TTL兼容数模转换器(工业级DIP366AD9721BR10位400MSPS TTL兼容数模转换器(工业级SOIC367AD9731BR10位170MSPS双电源数模转换器(工业级SOIC368AD9732BRS10位200MSPS单电源数模转换器(工业级SSOP369AD9750AR10位125MSPS数模转换器(工业级SOIC370AD9752AR12位125MSPS数模转换器(工业级SOIC371AD9760AR10位100MSPS数模转换器(工业级SOIC372AD9762AR12位100MSPS数模转换器(工业级SOIC373AD9764AR14位100MSPS数模转换器(工业级SOIC374AD976CN16位100KSPS BiCMOS并行输出模数转换器(工业级DIP 375AD976AN16位100KSPS BiCMOS并行输出模数转换器(工业级DIP 376AD976AAN16位200KSPS BiCMOS并行输出模数转换器(工业级DIP 377AD9772AST14位300MSPS数模转换器(工业级LQFP378AD977AAN16位200KSPS BiCMOS串行输出数模转换器(工业级DIP379AD977AN16位100KSPS BiCMOS串行输出数模转换器(工业级DIP380AD9801JCST10位6MSPS CCD信号处理器(民用级LQFP381AD9802JST10位6MSPS CCD信号处理器(民用级LQFP382AD9803JST10位6MSPS CCD信号处理器(民用级LQFP383AD9805JS10位3通道6MSPS CCD信号处理器(民用级MQFP384AD9816JS12位3通道6MSPS CCD信号处理器(民用级MQFP385AD9822JR14位3通道12MSPS CCD信号处理器(民用级SOIC386AD9830AST带10位D/A,25MHz主频直接数字同步调制器(工业级PQFP 387AD9831AST带10位D/A,50MHz主频直接数字同步调制器(工业级PQFP388AD9832BRU带10位D/A,25MHz主频直接数字同步调制器(工业级TSSOP 389AD9850BRS带10位D/A,125MHz主频直接数字同步调制器(工业级SSOP390AD9851BRS带10位D/A,180MHz主频直接数字同步调制器(工业级SSOP391AD9852AST带12位D/A,200MHz主频直接数字同步调制器(工业级LQFP-80392 AD9852ASQ 393 AD9853AS 394 AD9854AST 395 AD9854ASQ 396AD9901KQ 397 ADG201AKN 398 ADG201HSJN 399 ADG211AKN 400ADG222AKN 401 ADG333ABN 402 ADG333ABR 403 ADG408BN 404 ADG409BN 405 ADG411BN 406 ADG417BN 407 ADG419BN 408 ADG431BN 409 ADG436BN 410 ADG441BN 411 ADG442BN 412 ADG506AKN 413 ADG507AKN 414ADG508AKN 415 ADG508FBN 416 ADG509AKN 417 ADG511BN 418 ADG608BN 419 ADG609BN 420 ADG719BRM 带散热器带 12 位 D/A，300MHz 主频直接数字同步调制器（工业级）LQFP-80 数字 QPSK/16 QAM 调整器（工业级） PQFP 带12 位 D/A，200MHz 主频直接数字同步调制器（工业级）LQFP-80 带散热器带 12 位 D/A，300MHz 主频直接数字同步调制器（工业级）LQFP-80 线性相位探测器/频率鉴别器（民用级） DIP 四单刀单掷模拟开关（民用级） DIP 四单刀单掷模拟开关（民用级） DIP 四单刀单掷模拟开关（民用级） DIP 四单刀单掷模拟开关（民用级） DIP 四单刀单掷模拟开关（工业级） DIP 四单刀单掷模拟开关（工业级） SOIC 8 选 1CMOS 模拟多路转换器（工业级） DIP 差动 4 选 1CMOS 模拟多路转换器（工业级） DIP 四单刀单掷模拟开关（工业级） DIP 单刀单掷模拟开关（工业级） DIP 单刀单掷模拟开关（工业级） DIP 四单刀单掷模拟开关（工业级） DIP 双单刀单掷模拟开关（工业级） DIP 四单刀单掷模拟开关（工业级）DIP 四单刀单掷模拟开关（工业级） DIP 16 选 1CMOS 模拟多路转换器（民用级） DIP 差动 8 选 1CMOS 模拟多路转换器（民用级） DIP 8 选 1CMOS 模拟多路转换器（民用级） DIP 8 选 1CMOS 带过压保护模拟多路转换器（工业级） DIP 差动 4 选 1CMOS 模拟多路转换器（民用级） DIP 单电源四单刀单掷模拟开关（工业级） DIP 8 选 1CMOS 模拟多路转换器（工业级） DIP 差动 4 选 1CMOS 模拟多路转换器（工业级） DIP 单路视频 CMOS 模拟开关（工业级）RM-6 421ADG736BRM 422 ADM660AN 423 ADM690AN 424 ADM708AN 双路视频 CMOS 模拟开关（工业级）RM-10 DC-DC 转换器（工业级）DIP 微处理器监控电路（工业级） DIP 微处理器监控电路（工业级） DIP 425 ADSP21060KS160 32 位浮点数字信号处理器内存 4M（民用级）PQFP 426 ADSP21060CZ-16 0 ADSP21062KS-16 0 32 位浮点数字信号处理器内存 4M（工业级）PQFP 427 32 位浮点数字信号处理器内存 2M（民用级）PQFP 428 ADSP2181KS-133 16 位定点数字信号处理器（民用级）PQFP-128429 ADSP2181KST-13 3 16 位定点数字信号处理器（民用级）TQFP-128 带单片机、8 路 12 位 A/D、2 路 D/A 的数采系统（工业级）PQFP 500KHz 工业标准压频转换器（民用级） DIP ±1g-±5g 带温度补偿加速度传感器（民用级）QC-14 ±2g 双路加速度传感器（工业级）QC-14 高精度仪表放大器（工业级） DIP 单电源精密仪表放大器（工业级） DIP 8 位高速电流输出型数模转换器（民用级） DIP 8 位双路电压输出型数模转换器（工业级） DIP 超低失调电压运放（军用级）DIP 超低失调电压运放（工业级）DIP 超低失调电压运放（工业级）SOIC 低失真低噪声运放（工业级）DIP 高精密运放（工业级） DIP 低噪声精密运放（工业级） DIP 单电源 Rail-Rail 输入输出双运放（工业级）DIP 单电源 Rail-Rail 输入输出双运放（工业级）DIP 微功耗 Rail-Rail 输入输出双运放（工业级）DIP 超低偏置电流精密双运放（工业级） DIP 超低偏置电流精密双运放（工业级） SOIC 低噪声精密运放（民用级） DIP 低噪声精密运放（工业级） DIP 单电源 Rail-Rail 输入输出四运放（工业级）DIP 超低偏置电流精密四运放（工业级） DIP OP07 改进型（工业级）DIP 低电压微功耗精密运放（工业级） DIP 微功耗精密运放（工业级） DIP 微功耗精密运放（工业级） SOIC 峰值检测器（工业级） DIP 精密 5V 电压基准源带温度传感器（工业级） DIP 精密低价格 2.5V 电压基准源（工业级） DIP 低功耗大电流输出 2.5V 电压基准源（工业级） DIP 低功耗大电流输出 2.5V 电压基准源（工业级） SOIC 低功耗大电流输出 4.5V 电压基准源（工业级） DIP 低功耗大电流输出 5V 电压基准源（工业级） SOIC 高精度 2.5V 电压基准源（工业级）DIP7us 四通道采样保持放大器（工业级） DIP 7us 八通道采样保持放大器（工业级）DIP 差动线路接收器 Gain=0dB(工业级） DIP 430 ADUC812BS 431 ADVF32KN 432 ADXL105JQC 433 ADXL202AQC 434 AMP02FP 435 AMP04FP 436 DAC08CP 437 DAC8228FP 438 OP07AZ/883C 439 OP07CP 440 OP07CS 441 OP176GP 442OP177GP 443 OP27GP 444 OP291GP 445 OP295GP 446 OP296GP 447 OP297GP 448 OP297GS 449 OP37EP 450 OP37GP 451 OP495GP 452 OP497GP 453 OP77GP 454 OP90GP 455 OP97FP 456 OP97FS 457 PKD01FP 458 REF02CP 459 REF03GP 460 REF192GP 461 REF192GS 462 REF194GP 463 REF195GS 464 REF43FZ 465SMP04EP 466 SMP08FP 467 SSM2141P468 SSM2142P 469 SSM2143P 470 SSM2211P 471 SSM2275P 472 TMP03FS 473 TMP04FS 474 TMP36GT9 平衡线路驱动器（工业级） DIP 差动线路接收器 Gain=-6dB(工业级） DIP 1W 功率差分输出音频功率放大器（工业级）DIP Rail-Rail 输出双音频功率放大器（工业级）DIP PWM 输出，直接与微处理器接口数字输出温度传感器 SOIC 反相 PWM 输出，直接与微处理器接口数字输出温度传感器 SOIC 电压输出温度传感器 TO-92。

AD09库中英参照net 网络标号BELL 铃,钟BRIDEG 1 整流桥(二极管)BUZZER 蜂鸣器BUZZER 蜂鸣器CAP 电容DIODE 二极管INDUCTOR 电感LAMP 灯泡LED 发光二极管NPN NPN三极管PNP 三极管SW-PB 开关DPY_7-SEG_DP 数码管RES1.2 电阻b 工具条选择eea 取消所有选择状态ctrl+del 删除pw 画导线pb 画总线pu画总线分支线pn 设置网络标号_________________________________________________________________________ 原理图常用库文件：Miscellaneous Devices.ddbDallas Microprocessor.ddbIntel Databooks.ddbProtel DOS Schematic Libraries.ddbPCB元件常用库：Advpcb.ddbGeneral IC.ddbMiscellaneous.ddb部分分立元件库元件名称及中英对照AND 与门ANTENNA 天线BATTERY 直流电源BELL 铃,钟BVC 同轴电缆接插件BRIDEG 1 整流桥(二极管)BRIDEG 2 整流桥(集成块)BUFFER 缓冲器BUZZER 蜂鸣器CAP 电容CAPACITOR 电容CAPACITOR POL 有极性电容CAPV AR 可调电容CIRCUIT BREAKER 熔断丝COAX 同轴电缆CON 插口CRYSTAL 晶体整荡器DB 并行插口DIODE 二极管DIODE SCHOTTKY 稳压二极管DIODE V ARACTOR 变容二极管DPY_3-SEG 3段LEDDPY_7-SEG 7段LEDDPY_7-SEG_DP 7段LED(带小数点) ELECTRO 电解电容FUSE 熔断器INDUCTOR 电感INDUCTOR IRON 带铁芯电感INDUCTOR3 可调电感JFET N N沟道场效应管JFET P P沟道场效应管LAMP 灯泡LAMP NEDN 起辉器LED 发光二极管METER 仪表MICROPHONE 麦克风MOSFET MOS管MOTOR AC 交流电机MOTOR SERVO 伺服电机NAND 与非门NOR 或非门NOT 非门NPN NPN三极管NPN-PHOTO 感光三极管OPAMP 运放OR 或门PHOTO 感光二极管PNP 三极管NPN DAR NPN三极管PNP DAR PNP三极管POT 滑线变阻器PELAY-DPDT 双刀双掷继电器RES1.2 电阻RES3.4 可变电阻RESISTOR BRIDGE ? 桥式电阻RESPACK ? 电阻SCR 晶闸管PLUG ? 插头PLUG AC FEMALE 三相交流插头SOCKET ? 插座SOURCE CURRENT 电流源SOURCE VOLTAGE 电压源SPEAKER 扬声器SW ? 开关SW-DPDY ? 双刀双掷开关SW-SPST ? 单刀单掷开关SW-PB 按钮THERMISTOR 电热调节器TRANS1 变压器TRANS2 可调变压器TRIAC ? 三端双向可控硅TRIODE ? 三极真空管V ARISTOR 变阻器ZENER ? 齐纳二极管DPY_7-SEG_DP 数码管SW-PB 开关74系列：74LS00 TTL 2输入端四与非门74LS01 TTL 集电极开路2输入端四与非门74LS02 TTL 2输入端四或非门74LS03 TTL 集电极开路2输入端四与非门74LS122 TTL 可再触发单稳态多谐振荡器74LS123 TTL 双可再触发单稳态多谐振荡器74LS125 TTL 三态输出高有效四总线缓冲门74LS126 TTL 三态输出低有效四总线缓冲门74LS13 TTL 4输入端双与非施密特触发器74LS132 TTL 2输入端四与非施密特触发器74LS133 TTL 13输入端与非门74LS136 TTL 四异或门74LS138 TTL 3-8线译码器/复工器74LS139 TTL 双2-4线译码器/复工器74LS14 TTL 六反相施密特触发器74LS145 TTL BCD—十进制译码/驱动器74LS15 TTL 开路输出3输入端三与门74LS150 TTL 16选1数据选择/多路开关74LS151 TTL 8选1数据选择器74LS153 TTL 双4选1数据选择器74LS154 TTL 4线—16线译码器74LS155 TTL 图腾柱输出译码器/分配器74LS156 TTL 开路输出译码器/分配器74LS157 TTL 同相输出四2选1数据选择器74LS158 TTL 反相输出四2选1数据选择器74LS16 TTL 开路输出六反相缓冲/驱动器74LS160 TTL 可预置BCD异步清除计数器74LS161 TTL 可予制四位二进制异步清除计数器74LS162 TTL 可预置BCD同步清除计数器74LS163 TTL 可予制四位二进制同步清除计数器74LS164 TTL 八位串行入/并行输出移位寄存器74LS165 TTL 八位并行入/串行输出移位寄存器74LS166 TTL 八位并入/串出移位寄存器74LS169 TTL 二进制四位加/减同步计数器74LS17 TTL 开路输出六同相缓冲/驱动器74LS170 TTL 开路输出4×4寄存器堆74LS173 TTL 三态输出四位D型寄存器74LS174 TTL 带公共时钟和复位六D触发器74LS175 TTL 带公共时钟和复位四D触发器74LS180 TTL 9位奇数/偶数发生器/校验器74LS181 TTL 算术逻辑单元/函数发生器74LS185 TTL 二进制—BCD代码转换器74LS190 TTL BCD同步加/减计数器74LS191 TTL 二进制同步可逆计数器74LS192 TTL 可预置BCD双时钟可逆计数器74LS193 TTL 可预置四位二进制双时钟可逆计数器74LS194 TTL 四位双向通用移位寄存器74LS195 TTL 四位并行通道移位寄存器74LS196 TTL 十进制/二-十进制可预置计数锁存器74LS197 TTL 二进制可预置锁存器/计数器74LS20 TTL 4输入端双与非门74LS21 TTL 4输入端双与门74LS22 TTL 开路输出4输入端双与非门74LS221 TTL 双/单稳态多谐振荡器74LS240 TTL 八反相三态缓冲器/线驱动器74LS241 TTL 八同相三态缓冲器/线驱动器74LS243 TTL 四同相三态总线收发器74LS244 TTL 八同相三态缓冲器/线驱动器74LS245 TTL 八同相三态总线收发器74LS247 TTL BCD—7段15V输出译码/驱动器74LS248 TTL BCD—7段译码/升压输出驱动器74LS249 TTL BCD—7段译码/开路输出驱动器74LS251 TTL 三态输出8选1数据选择器/复工器74LS253 TTL 三态输出双4选1数据选择器/复工器74LS256 TTL 双四位可寻址锁存器74LS257 TTL 三态原码四2选1数据选择器/复工器74LS258 TTL 三态反码四2选1数据选择器/复工器74LS259 TTL 八位可寻址锁存器/3-8线译码器74LS26 TTL 2输入端高压接口四与非门74LS260 TTL 5输入端双或非门74LS266 TTL 2输入端四异或非门74LS27 TTL 3输入端三或非门74LS273 TTL 带公共时钟复位八D触发器74LS279 TTL 四图腾柱输出S-R锁存器74LS28 TTL 2输入端四或非门缓冲器74LS283 TTL 4位二进制全加器74LS290 TTL 二/五分频十进制计数器74LS293 TTL 二/八分频四位二进制计数器74LS295 TTL 四位双向通用移位寄存器74LS298 TTL 四2输入多路带存贮开关74LS299 TTL 三态输出八位通用移位寄存器74LS30 TTL 8输入端与非门74LS32 TTL 2输入端四或门74LS322 TTL 带符号扩展端八位移位寄存器74LS323 TTL 三态输出八位双向移位/存贮寄存器74LS33 TTL 开路输出2输入端四或非缓冲器74LS347 TTL BCD—7段译码器/驱动器74LS352 TTL 双4选1数据选择器/复工器74LS353 TTL 三态输出双4选1数据选择器/复工器74LS365 TTL 门使能输入三态输出六同相线驱动器74LS365 TTL 门使能输入三态输出六同相线驱动器74LS366 TTL 门使能输入三态输出六反相线驱动器74LS367 TTL 4/2线使能输入三态六同相线驱动器74LS368 TTL 4/2线使能输入三态六反相线驱动器74LS37 TTL 开路输出2输入端四与非缓冲器74LS373 TTL 三态同相八D锁存器74LS374 TTL 三态反相八D锁存器74LS375 TTL 4位双稳态锁存器74LS377 TTL 单边输出公共使能八D锁存器74LS378 TTL 单边输出公共使能六D锁存器74LS379 TTL 双边输出公共使能四D锁存器74LS38 TTL 开路输出2输入端四与非缓冲器74LS380 TTL 多功能八进制寄存器74LS39 TTL 开路输出2输入端四与非缓冲器74LS390 TTL 双十进制计数器74LS393 TTL 双四位二进制计数器74LS40 TTL 4输入端双与非缓冲器74LS42 TTL BCD—十进制代码转换器74LS352 TTL 双4选1数据选择器/复工器74LS353 TTL 三态输出双4选1数据选择器/复工器74LS365 TTL 门使能输入三态输出六同相线驱动器74LS366 TTL 门使能输入三态输出六反相线驱动器74LS367 TTL 4/2线使能输入三态六同相线驱动器74LS368 TTL 4/2线使能输入三态六反相线驱动器74LS37 TTL 开路输出2输入端四与非缓冲器74LS373 TTL 三态同相八D锁存器74LS374 TTL 三态反相八D锁存器74LS375 TTL 4位双稳态锁存器74LS377 TTL 单边输出公共使能八D锁存器74LS378 TTL 单边输出公共使能六D锁存器74LS379 TTL 双边输出公共使能四D锁存器74LS38 TTL 开路输出2输入端四与非缓冲器74LS380 TTL 多功能八进制寄存器74LS39 TTL 开路输出2输入端四与非缓冲器74LS390 TTL 双十进制计数器74LS393 TTL 双四位二进制计数器74LS40 TTL 4输入端双与非缓冲器74LS42 TTL BCD—十进制代码转换器74LS447 TTL BCD—7段译码器/驱动器74LS45 TTL BCD—十进制代码转换/驱动器74LS450 TTL 16:1多路转接复用器多工器74LS451 TTL 双8:1多路转接复用器多工器74LS453 TTL 四4:1多路转接复用器多工器74LS46 TTL BCD—7段低有效译码/驱动器74LS460 TTL 十位比较器74LS461 TTL 八进制计数器74LS465 TTL 三态同相2与使能端八总线缓冲器74LS466 TTL 三态反相2与使能八总线缓冲器74LS467 TTL 三态同相2使能端八总线缓冲器74LS468 TTL 三态反相2使能端八总线缓冲器74LS469 TTL 八位双向计数器74LS47 TTL BCD—7段高有效译码/驱动器74LS48 TTL BCD—7段译码器/内部上拉输出驱动74LS490 TTL 双十进制计数器74LS491 TTL 十位计数器74LS498 TTL 八进制移位寄存器74LS50 TTL 2-3/2-2输入端双与或非门74LS502 TTL 八位逐次逼近寄存器74LS503 TTL 八位逐次逼近寄存器74LS51 TTL 2-3/2-2输入端双与或非门74LS533 TTL 三态反相八D锁存器74LS534 TTL 三态反相八D锁存器74LS54 TTL 四路输入与或非门74LS540 TTL 八位三态反相输出总线缓冲器74LS55 TTL 4输入端二路输入与或非门74LS563 TTL 八位三态反相输出触发器74LS564 TTL 八位三态反相输出D触发器74LS573 TTL 八位三态输出触发器74LS574 TTL 八位三态输出D触发器74LS645 TTL 三态输出八同相总线传送接收器74LS670 TTL 三态输出4×4寄存器堆74LS73 TTL 带清除负触发双J-K触发器74LS74 TTL 带置位复位正触发双D触发器74LS76 TTL 带预置清除双J-K触发器74LS83 TTL 四位二进制快速进位全加器74LS85 TTL 四位数字比较器74LS86 TTL 2输入端四异或门74LS90 TTL 可二/五分频十进制计数器74LS93 TTL 可二/八分频二进制计数器74LS95 TTL 四位并行输入\\输出移位寄存器74LS97 TTL 6位同步二进制乘法器CD系列：：CD4000 双3输入端或非门+单非门TICD4001 四2输入端或非门HIT/NSC/TI/GOLCD4002 双4输入端或非门NSCCD4006 18位串入/串出移位寄存器NSCCD4007 双互补对加反相器NSCCD4008 4位超前进位全加器NSCCD4009 六反相缓冲/变换器NSCCD4010 六同相缓冲/变换器NSCCD4011 四2输入端与非门HIT/TICD4012 双4输入端与非门NSCCD4013 双主-从D型触发器FSC/NSC/TOSCD4014 8位串入/并入-串出移位寄存器NSCCD4015 双4位串入/并出移位寄存器TICD4016 四传输门FSC/TICD4017 十进制计数/分配器FSC/TI/MOTCD4018 可预制1/N计数器NSC/MOTCD4019 四与或选择器PHICD4020 14级串行二进制计数/分频器FSCCD4021 08位串入/并入-串出移位寄存器PHI/NSCCD4022 八进制计数/分配器NSC/MOTCD4023 三3输入端与非门NSC/MOT/TICD4024 7级二进制串行计数/分频器NSC/MOT/TICD4025 三3输入端或非门NSC/MOT/TICD4026 十进制计数/7段译码器NSC/MOT/TICD4027 双J-K触发器NSC/MOT/TICD4028 BCD码十进制译码器NSC/MOT/TICD4029 可预置可逆计数器NSC/MOT/TICD4030 四异或门NSC/MOT/TI/GOLCD4031 64位串入/串出移位存储器NSC/MOT/TICD4032 三串行加法器NSC/TICD4033 十进制计数/7段译码器NSC/TICD4034 8位通用总线寄存器NSC/MOT/TICD4035 4位并入/串入-并出/串出移位寄存NSC/MOT/TI CD4038 三串行加法器NSC/TICD4040 12级二进制串行计数/分频器NSC/MOT/TICD4041 四同相/反相缓冲器NSC/MOT/TICD4042 四锁存D型触发器NSC/MOT/TICD4043 4三态R-S锁存触发器("1"触发) NSC/MOT/TI CD4044 四三态R-S锁存触发器("0"触发) NSC/MOT/TI CD4046 锁相环NSC/MOT/TI/PHICD4047 无稳态/单稳态多谐振荡器NSC/MOT/TICD4048 4输入端可扩展多功能门NSC/HIT/TICD4049 六反相缓冲/变换器NSC/HIT/TICD4050 六同相缓冲/变换器NSC/MOT/TICD4051 八选一模拟开关NSC/MOT/TICD4052 双4选1模拟开关NSC/MOT/TICD4053 三组二路模拟开关NSC/MOT/TICD4054 液晶显示驱动器NSC/HIT/TICD4055 BCD-7段译码/液晶驱动器NSC/HIT/TICD4056 液晶显示驱动器NSC/HIT/TICD4059 “N”分频计数器NSC/TICD4060 14级二进制串行计数/分频器NSC/TI/MOT CD4063 四位数字比较器NSC/HIT/TICD4066 四传输门NSC/TI/MOTCD4067 16选1模拟开关NSC/TICD4068 八输入端与非门/与门NSC/HIT/TICD4069 六反相器NSC/HIT/TICD4070 四异或门NSC/HIT/TICD4071 四2输入端或门NSC/TICD4072 双4输入端或门NSC/TICD4073 三3输入端与门NSC/TICD4075 三3输入端或门NSC/TICD4076 四D寄存器CD4077 四2输入端异或非门HITCD4078 8输入端或非门/或门CD4081 四2输入端与门NSC/HIT/TICD4082 双4输入端与门NSC/HIT/TICD4085 双2路2输入端与或非门CD4086 四2输入端可扩展与或非门CD4089 二进制比例乘法器CD4093 四2输入端施密特触发器NSC/MOT/STCD4094 8位移位存储总线寄存器NSC/TI/PHICD4095 3输入端J-K触发器CD4096 3输入端J-K触发器CD4097 双路八选一模拟开关CD4098 双单稳态触发器NSC/MOT/TICD4099 8位可寻址锁存器NSC/MOT/STCD40100 32位左/右移位寄存器CD40101 9位奇偶较验器CD40102 8位可预置同步BCD减法计数器CD40103 8位可预置同步二进制减法计数器CD40104 4位双向移位寄存器CD40105 先入先出FI-FD寄存器CD40106 六施密特触发器NSC\\TICD40107 双2输入端与非缓冲/驱动器HAR\\TICD40108 4字×4位多通道寄存器CD40109 四低-高电平位移器CD4529 双四路/单八路模拟开关CD4530 双5输入端优势逻辑门CD4531 12位奇偶校验器CD4532 8位优先编码器CD4536 可编程定时器CD4538 精密双单稳CD4539 双四路数据选择器CD4541 可编程序振荡/***CD4543 BCD七段锁存译码,驱动器CD4544 BCD七段锁存译码,驱动器CD4547 BCD七段译码/大电流驱动器CD4549 函数近似寄存器CD4551 四2通道模拟开关CD4553 三位BCD计数器CD4555 双二进制四选一译码器/分离器CD4556 双二进制四选一译码器/分离器CD4558 BCD八段译码器CD4560 "N"BCD加法器CD4561 "9"求补器CD4573 四可编程运算放大器CD4574 四可编程电压比较器CD4575 双可编程运放/比较器CD4583 双施密特触发器CD4584 六施密特触发器CD4585 4位数值比较器CD4599 8位可寻址锁存器CD40110 十进制加/减,计数,锁存,译码驱动STCD40147 10-4线编码器NSC\\MOTCD40160 可预置BCD加计数器NSC\\MOTCD40161 可预置4位二进制加计数器NSC\\MOTCD40162 BCD加法计数器NSC\\MOTCD40163 4位二进制同步计数器NSC\\MOTCD40174 六锁存D型触发器NSC\\TI\\MOTCD40175 四D型触发器NSC\\TI\\MOTCD40181 4位算术逻辑单元/函数发生器CD40182 超前位发生器CD40192 可预置BCD加/减计数器(双时钟) NSC\\TICD40193 可预置4位二进制加/减计数器NSC\\TICD40194 4位并入/串入-并出/串出移位寄存NSC\\MOTCD40195 4位并入/串入-并出/串出移位寄存NSC\\MOTCD40208 4×4多端口寄存器型号器件名称厂牌备注CD4501 4输入端双与门及2输入端或非门CD4502 可选通三态输出六反相/缓冲器CD4503 六同相三态缓冲器CD4504 六电压转换器CD4506 双二组2输入可扩展或非门CD4508 双4位锁存D型触发器CD4510 可预置BCD码加/减计数器CD4511 BCD锁存,7段译码,驱动器CD4512 八路数据选择器CD4513 BCD锁存,7段译码,驱动器(消隐)CD4514 4位锁存,4线-16线译码器CD4515 4位锁存,4线-16线译码器CD4516 可预置4位二进制加/减计数器CD4517 双64位静态移位寄存器CD4518 双BCD同步加计数器CD4519 四位与或选择器CD4520 双4位二进制同步加计数器CD4521 24级分频器CD4522 可预置BCD同步1/N计数器CD4526 可预置4位二进制同步1/N计数器CD4527 BCD比例乘法器CD4528 双单稳态触发器注：同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上是一样的。

14090fcFEATURESAPPLICATIONSDESCRIPTION2A High Voltage Bat-TrackBuck RegulatorThe L TC ®4090/L TC4090-5 are USB power managers plus high voltage Li-Ion/Polymer battery chargers. The devices control the total current used by the USB peripheral for operation and battery charging. Battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the programmed input current limit. The L TC4090/L TC4090-5 also accom-modate high voltage power supplies, such as 12V AC/DC wall adapters, Firewire, or automotive power .The L TC4090 provides a Bat-T rack adaptive output that tracks the battery voltage for high effi ciency charging from the high voltage input. The L TC4090-5 provides a fi xed 5V output from the high voltage input to charge single-cell Li-Ion batteries. The charge current is programmable and an end-of-charge status output (CHRG ) indicates full charge. Also featured are programmable total charge time, an NTC thermistor input used to monitor battery temperature while charging and automatic recharging of the battery.nSeamless T ransition Between Power Sources: Li-Ion Battery, USB, and 6V to 36V Supply (60V Max)n 2A Output High Voltage Buck Regulator with Bat-T rack™ Adaptive Output Control (L TC4090)n Internal 215m Ω Ideal Diode Plus Optional External Ideal Diode Controller Provides Low Loss Power Path When External Supply/USB Not Present n Load Dependent Charging from USB Input Guarantees Current Compliance n Full Featured Li-Ion Battery Chargern 1.5A Maximum Charge Current with Thermal Limiting n NTC Thermistor Input for Temperature Qualifi ed Charging n Tiny (3mm × 6mm × 0.75mm) 22-Pin DFN PackagenHDD-Based Media Players n Personal Navigation Devicesn Other USB-Based Handheld Products n Automotive Accessories4090 TAO1V OUT (TYP)V BAT + 0.3V5V 5V V BATAVAILABLE INPUT HV INPUT (L TC4090)HV INPUT (L TC4090-5)USB ONL Y BAT ONL YL TC4090/L TC4090-5 High VoltageBattery Charger Effi ciencyV BAT (V)2.0E F F I C I E N C Y (%)7080904.04090 TA01b6050204030 2.53.03.54.5T YPICAL APPLICATION L , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. Bat-T rack is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners./24090fcPIN CONFIGURATIONABSOLUTE MAXIMUM RATINGSHVIN, HVEN (Note 9) ................................................60V BOOST ......................................................................56V BOOST above SW .....................................................30V PG, SYNC ..................................................................30V IN, OUT , HVOUTt < 1ms and Duty Cycle < 1% ..................–0.3V to 7V Steady State .............................................–0.3V to 6V BAT , HPWR, SUSP , V C , CHRG , HVPR ...........–0.3V to 6V NTC, TIMER, PROG, CLPROG ..........–0.3V to V CC + 0.3V I IN , I OUT , I BAT (Note 5) ..............................................2.5A Operating Temperature Range......................–40 to 85°C Junction Temperature ...........................................110°C Storage Temperature Range .......................–65 to 125°C(Notes 1, 2, 3, 4)22212019181716151413121234567891011HVEN HVIN SW BOOST HVOUT TIMER SUSP HPWR CLPROG OUT INTOP VIEW23DJC PACKAGE22-LEAD (6mm s 3mm) PLASTIC DFNSYNC PG R T V C NTC VNTC HVPR CHRG PROGGATE BAT T JMAX = 110°C, θJA = 47°C/WEXPOSED PAD (PIN 23) IS GND, MUST BE SOLDERED TO PCBSYMBOL PARAMETERCONDITIONSMIN TYP MAX UNITSUSB Input Current LimitV IN USB Input Supply Voltage l 4.355.5V I IN Input Bias Current I BAT = 0 (Note 6)Suspend Mode; SUSP = 5V l l 0.5501100mA μA I LIM Current LimitHPWR = 5V HPWR = 0V l l47590500100525110mA mA I IN(MAX)Maximum Input Current Limit (Note 7) 2.4A R ON On-Resistance V IN to V OUTI OUT = 80mA 0.215ΩV CLPROG CLPROG Servo Voltage in Current Limit R CLPROG = 2k R CLPROG = 1kl l0.980.981.001.00 1.021.02V V I SSSoft-Start Inrush Current10mA/μsThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. HVIN = HVEN = 12V , BOOST = 17V, V IN = HPWR = 5V , V BAT = 3.7V,R PROG = 100k, R CLPROG = 2k and SUSP = 0V, unless otherwise noted.LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC4090EDJC#PBF L TC4090EDJC#TRPBF 409022-Lead (6mm × 3mm) Plastic DFN –40°C to 85°C L TC4090EDJC-5#PBFL TC4090EDJC-5#TRPBF4090522-Lead (6mm × 3mm) Plastic DFN–40°C to 85°CConsult L TC Marketing for parts specifi ed with wider operating temperature ranges.Consult L TC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ORDER INFORMATIONELECTRICAL CHARACTERISTICS/ELECTRICAL CHARACTERISTICSThel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. HVIN = HVEN = 12V, BOOST = 17V, V IN = HPWR = 5V, V BAT = 3.7V,R PROG = 100k, R CLPROG = 2k and SUSP = 0V, unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSV CLEN Input Current Limit Enable ThresholdVoltage (V IN - V OUT)(V IN - V OUT) Rising(V IN - V OUT) Falling20–8050–5080–20mVmVV UVLO Input Undervoltage Lockout V IN Rising l 3.6 3.84V ΔV UVLO Input Undervoltage Lockout Hysteresis V IN Rising – V IN Falling130mV High Voltage RegulatorV HVIN HVIN Supply Voltage l660V V OVLO HVIN Overvoltage Lockout Threshold l363840VI HVIN HVIN Bias Current Shutdown; HVEN = 0.2VNot Switching, HVOUT = 3.6V l 0.011300.5200μAμAV OUT Output Voltage with HVIN Present Assumes HVOUT to OUT Connection,0 ≤ V BAT ≤ 4.2V (L TC4090)3.45V BAT + 0.34.6VV OUT Output Voltage with HVIN Present Assumes HVOUT to OUT Connection(L TC4090-5)4.8555.15Vf SW Switching Frequency R T = 8.66kR T = 29.4kR T = 187k 2.10.91602.41.02002.71.15240MHzMHzkHzt OFF Minimum Switch Off-Time l60150ns I SW(MAX)Switch Current Limit Duty Cycle = 5% 3.0 3.5 4.0A V SAT Switch V CESAT I SW = 2A500mV I R Boost Schottky Reverse Leakage SW = 10V, HVOUT = 0V0.022μA V B(MIN)Minimum Boost Voltage (Note 8)l 1.5 2.1V I BST BOOST Pin Current I SW = 1A2235mA Battery ManagementI BAT Battery Drain Current V BAT = 4.3V, Charging StoppedSuspend Mode, SUSP = 5VV IN = 0V, BAT Powers OUT, No Load lll1522602735100μAμAμAV FLOAT V BAT Regulated Output Voltage I BAT = 2mAI BAT = 2mA; 0 ≤ T A ≤ 85°C 4.1654.1584.2004.2004.2354.242VVI CHG Constant-Current Mode Charge Current,No Load R PROG = 100kR PROG = 50k, 0 ≤ T A ≤ 85°Cl46590050010005351080mAmAI CHG(MAX)Maximum Charge Current 1.5AV PROG PROG Pin Servo Voltage R PROG = 100kR PROG = 50k ll0.980.981.001.001.021.02VVk EOC Ratio of End-of-Charge IndicationCurrent to Charge CurrentV BAT = V FLOAT (4.2V)l0.0850.10.11mA/mA I TRKL T rickle Charge Current BAT = 2V355060mA V TRKL T rickle Charge Threshold Voltage BAT Rising l 2.75 2.9 3.0VV CEN Charge Enable Threshold Voltage(V OUT – V BAT) Falling; V BAT = 4V(V OUT – V BAT) Rising; V BAT = 4V 5580mVmVΔV RECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to V FLOAT l–65–100–135mV /34090fc44090fcSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSt TIMERTIMER Accuracy V BAT = 4.3V–1010%Recharge TimePercent of Total Charge Time 50%Low Battery T rickle Charge TimePercent of Total Charge Time,V BAT <2.9V25%T LIMJunction Temperature in Constant-Temperature Mode105°CInternal Ideal Diode R FWD Incremental Resistance, V ON Regulation I OUT = 100mA 125m ΩR DIO, ON On-Resistance V BAT to V OUT I OUT = 600mA 215m ΩV FWDVoltage Forward Drop (V BAT – V OUT )I OUT = 5mA I OUT = 100mA I OUT = 600mAl10305516050mV mV mV V OFF Diode Disable Battery Voltage 2.7V I FWD Load Current Limit for V ON Regulation 550mA I D(MAX)Diode Current Limit2.2A External Ideal DiodeV FWD, EXT External Diode Forward Voltage 20mVLogic (CHRG , HVPR , TIMER, SUSP , HPWR, HVEN, PG, SYNC)V CHG, SD Charger Shutdown Threshold Voltage on TIMERl0.140.4V I CHG, SD Charger Shutdown Pull-Up Current on TIMERV TIMER = 0Vl 514μAV OL Output Low Voltage (CHRG , HVPR ); I SINK = 5mA l0.10.4V V IH Input High Voltage SUSP , HPWR 1.2V V IL Input Low Voltage SUSP , HPWR0.4V V HVEN, H HVEN High Threshold 2.3VV HVEN, L HVEN Low Threshold 0.3V I PULLDN Logic Input Pull-Down Current SUSP , HPWR 2μAI HVEN HVEN Pin Bias Current HVEN = 2.5V 510μA V PG PG Threshold HVOUT Rising2.8V ΔV PG PG Hysteresis 35mVI PGLK PG Leakage PG = 5V 0.11μA I PG PG Sink Current PG = 0.4Vl100900μA V SYNC, L SYNC Low Threshold 0.5VV SYNC, H SYNC High Threshold 0.8V I SYNCSYNC Pin Bias CurrentV SYNC = 0V 0.1μAELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operatingtemperature range, otherwise specifi cations are at T A = 25°C. HVIN = HVEN = 12V , BOOST = 17V , V IN = HPWR = 5V , V BAT = 3.7V ,R PROG = 100k, R CLPROG = 2k and SUSP = 0V , unless otherwise noted./54090fcI BAT (mA)4.00V F L O A T (V )4.054.104.154.204.254.302004006008004090 G011000TEMPERATURE (°C)–50V F L O A T (V )4.1954.2004.20525754090 G024.1904.1854.180–250504.2104.2154.220100TIME (MIN)V B A T , V O U T , V C H R G B (V )I BAT (mA)232004090 G03105010015054600900300015001200Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L TC4090/L TC4090-5 are guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 110°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may result in device degradation or failure.Note 4: V CC is the greater of V IN , V OUT , and V BATNote 5: Guaranteed by long term current density limitations.Note 6: Total input current is equal to this specifi cation plus 1.002 • I BAT where I BAT is the charge current.Note 7: Accuracy of programmed current may degrade for currents greater than 1.5A.Note 8: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the switch.Note 9: Absolute Maximum Voltage at HVIN and HVEN pins is for nonrepetative 1 second transients; 40V for continuous operation.ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operatingtemperature range, otherwise specifi cations are at T A = 25°C. HVIN = HVEN = 12V , BOOST = 17V , V IN = HPWR = 5V , V BAT = 3.7V ,R PROG = 100k, R CLPROG = 2k and SUSP = 0V , unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NTC I VNTC VNTC Pin Current VNTC = 2.5V l 1.4 2.5 3.5mA V VNTC VNTC Bias Voltage I VNTC = 500μA l4.44.85V I NTC NTC Input Leakage Current NTC = 1V 0±1μA V COLD Cold Temperature Fault Threshold VoltageRising NTC Voltage Hysteresis 0.738 • VNTC 0.02 • VNTC V V V HOT Hot Temperature Fault Threshold VoltageFalling NTC Voltage Hysteresis 0.29 • VNTC 0.01 • VNTCV VV DISNTC Disable Threshold VoltageFalling NTC Voltage Hysteresisl 7510035125mV mVV FLOAT Load RegulationBattery Regulation (Float) Voltage vs TemperatureBattery Current and Voltage vs Time (L TC4090)TYPICAL PERFORMANCE CHARACTERISTICS/64090fcSWITCH CURRENT (mA)040050070015004090 G123002005001000200025001000600V O L T A G E D R O P (m V)300040005000804090 G072000100025003500450015005000204060100V FWD (mV)I O U T (m A )V BAT (V)00I B A T (m A )10030040050012 2.5 4.54090 G042000.5 1.53 3.54600TEMPERATURE (°C)–50I B A T (m A )40050060025754090 G05300200–250501001251000V FWD (mV)I O U T (m A )1003004005001000700501004090 G06200800900600150200I OUT (A)E F F I C I E N C Y (%)80901000.84090 G0870607585956555500.20.40.61.0HVIN (V)51.8I O U T (A )2.02.22.42.63.0101520254090 G1030352.8TEMPERATURE (˚C)M I N I M U M S W I T C H O N T I M E (n s )801001204090 G116040200140–5025–255075100150125TYPICAL PERFORMANCE CHARACTERISTICSCharging from USB, I BAT vs V BATCharge Current vs Temperature (Thermal Regulation)Ideal Diode Current vs Forward Voltage and Temperature (No External Device)Ideal Diode Current vs Forward Voltage and Temperature with External DeviceL TC4090 High Voltage Regulator Effi ciency vs Output LoadHigh Voltage Regulator Maximum Load CurrentHigh Voltage Regulator Minimum Switch On-Time vs TemperatureHigh Voltage Regulator Switch Voltage DropI OUT (A)E F F I C I E N C Y (%)80901000.84090 G0970607585956555500.20.40.61.0L TC4090-5 High Voltage Regulator Effi ciency vs Output Load/74090fcTEMPERATURE (°C)–50H V O U T T H R E S H O L D V O L T A G E (V )2.802.852.9025751504090 G212.752.702.65–2550100125DUTY CYCLE (%)S W I T C H C U R R E N T L I M I T (A )404090 G162.520601.51.04.03.53.02.080100HVEN PIN VOLTAGE (V)0S W I T C H C U R R E N T L I M I T (A )3.5 1.54090 G152.01.00.5120.54.03.02.51.5 2.53 3.5TEMPERATURE (°C)–50500F R E Q U E N C Y (k H z )6007008009000501001504090 G1310001100–252575125HVOUT (V)0S W I T C H I N G F R E Q U E N C Y (k H z )1003004005001000700124090 G1420080090060034BOOST DIODE CURRENT (A)B O O S T D I O D E V f (V )0.81.01.22.04090 G190.60.400.5 1.0 1.50.21.4LOAD CURRENT (mA)15.0H V I N (V )6.07.01010010004090 G184.04.55.56.53.53.0TEMPERATURE (°C)V C V O L T A G E (V )1.502.002.504090 G201.000.500–5025–255075100150125TYPICAL PERFORMANCE CHARACTERISTICSHigh Voltage Regulator Switch FrequencyHigh Voltage Regulator Frequency FoldbackHigh Voltage Regulator Soft-StartHigh Voltage Regulator Switch Current LimitHigh Voltage Regulator Minimum Input VoltageHigh Voltage Regulator Boost Diode V F vs I FHigh Voltage Regulator V C VoltagesHigh Voltage Regulator Power Good ThresholdTEMPERATURE (°C)S W I T C H C U R R E N T L I M I T (A )2.02.53.53.04090 G171.51.00.54.54.0–5025–255075100150125High Voltage Regulator Switch Current Limit/84090fc100μs/DIVHPWR5V/DIVI IN 0.5A/DIV I BAT 0.5A/DIV4090 G27V BAT = 3.85V I OUT= 50mATYPICAL PERFORMANCE CHARACTERISTICSL TC4090 Input Connect WaveformsL TC4090 Input Disconnect WaveformsL TC4090 Response to SuspendL TC4090 High Voltage Input Connect WaveformsL TC4090 High Voltage Input Disconnect WaveformsL TC4090 High Voltage Regulator Load T ransientL TC4090 High Voltage Regulator Load T ransient1ms/DIVV IN 5V/DIV V OUT 5V/DIVI IN 0.5A/DIV I BAT 0.5A/DIV4090 G22V BAT = 3.85V I OUT= 100mA1ms/DIVV IN 5V/DIV V OUT 5V/DIVI IN 0.5A/DIV I BAT 0.5A/DIV4090 G23V BAT = 3.85V I OUT= 100mA1ms/DIVSUSP 5V/DIV V OUT 5V/DIVI IN 0.5A/DIV I BAT 0.5A/DIV4090 G24V BAT = 3.85V I OUT= 50mA2ms/DIVV HVIN 10V/DIV V OUT 5V/DIV I HVIN 1A/DIV I BAT 1A/DIV4090 G25V BAT = 3.85V I OUT= 100mA2ms/DIVV HVIN 5V/DIV V OUT 5V/DIV I HVIN 1A/DIV I BAT 1A/DIV4090 G26V BAT = 3.85V I OUT= 100mAL TC4090 Response to HPWR25μs/DIVHVOUT 50mV/DIVI OUT 1A/DIV4090 G28I LOAD= 500mA25μs/DIVHVOUT 50mV/DIVI L 1A/DIV4090 G29I LOAD= 500mA/PIN FUNCTIONSSYNC (Pin 1): External Clock Synchronization Input. See synchronizing section in the Applications Information section. Ground pin when not used.PG (Pin 2): Open Collector Output of an Internal Compara-tor. PG remains low until the HVOUT pin is above 2.8V. PG output is valid when HVIN is above 3.6V and HVEN is high.R T (Pin 3): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency.V C (Pin 4): High Voltage Buck Regulator Control Pin. The voltage on this pin controls the peak switch current in the high voltage regulator. Tie an RC network from this pin to ground to compensate the control loop.NTC (Pin 5): Input to the NTC Thermistor Monitoring Circuits. The NTC pin connects to a negative temperature coeffi cient thermistor which is typically co-packaged with the battery pack to determine if the battery is too hot or too cold to charge. If the battery temperature is out of range, charging is paused until the battery temperature re-enters the valid range. A low drift bias resistor is required from VNTC to NTC and a thermistor is required from NTC to ground. If the NTC function is not desired, the NTC pin should be grounded.VNTC (Pin 6): Output Bias Voltage for NTC. A resistor from this pin to the NTC pin will bias the NTC thermistor. HVPR (Pin 7): High Voltage Present Output (Active Low).A low on this pin indicates that the high voltage regulator has suffi cient voltage to charge the battery. This feature is enabled if power is present on HVIN, IN, or BAT (i.e., above UVLO thresholds).CHRG (Pin 8): Open-Drain Charge Status Output. When the battery is being charged, the CHRG pin is pulled low by an internal N-channel MOSFET. When the timer runs out or the charge current drops below 10% of the programmed charge current or the input supply is removed, the CHRG pin is forced to a high impedance state.PROG (Pin 9): Charge Current Program Pin. Connecting a resistor from PROG to ground programs the charge current:I CHG(A)=50,000VR PROGGATE (Pin 10): External Ideal Diode Gate Connection. This pin controls the gate of an optional external P-channel MOSFET transistor used to supplement the internal ideal diode. The source of the P-channel MOSFET should be connected to OUT and the drain should be connected to BAT. When not in use, this pin should be left fl oating. It is important to maintain high impedance on this pin and minimize all leakage paths.BAT (Pin 11): Single-Cell Li-Ion Battery. This pin is used as an output when charging the battery and as an input when supplying power to OUT. When the OUT pin potential drops below the BAT pin potential, an ideal diode function connects BAT to OUT and prevents OUT from dropping more than 100mV below BAT. A precision internal resistor divider sets the fi nal fl oat (charging) potential on this pin. The internal resistor divider is disconnected when IN and HVIN are in undervoltage lockout.IN (Pin 12): Input Supply. Connect to USB supply, V BUS. Input current to this pin is limited to either 20% or 100% of the current programmed by the CLPROG pin as deter-mined by the state of the HPWR pin. Charge current (to the BAT pin) supplied through the input is set to the current programmed by the PROG pin but will be limited by the input current limit if charge current is set greater than the input current limit or if the sum of charge current plus load current is greater than the input current limit.OUT (Pin 13): Voltage Output. This pin is used to provide controlled power to a USB device from either USB V BUS (IN), an external high voltage supply (HVIN), or the battery (BAT) when no other supply is present. The high voltage supply is prioritized over the USB V BUS input. OUT should be bypassed with at least 4.7μF to GND./94090fcCLPROG (Pin 14): Current Limit Program and Input Cur-rent Monitor. Connecting a resistor, R CLPROG, to ground programs the input to output current limit. The current limit is programmed as follows:I CL(A)=1000V R CLPROGIn USB applications, the resistor R CLPROG should be set to no less than 2.1k. The voltage on the CLPROG pin is always proportional to the current fl owing through the IN to OUT power path. This current can be calculated as follows:I IN(A)=V CLPROGR CLPROG•1000HPWR (Pin 15): High Power Select. This logic input is used to control the input current limit. A voltage greater than 1.2V on the pin will set the input current limit to 100% of the current programmed by the CLPROG pin. A voltage less than 0.4V on the pin will set the input current limit to 20% of the current programmed by the CLPROG pin. A 2μA pull-down current is internally connected to this pin to ensure it is low at power up when the pin is not being driven externally.SUSP (Pin 16): Suspend Mode Input. Pulling this pin above 1.2V will disable the power path from IN to OUT. The supply current from IN will be reduced to comply with the USB specifi cation for suspend mode. Both the ability to charge the battery from HVIN and the ideal diode function (from BAT to OUT) will remain active. Suspend mode will reset the charge timer if OUT is less than BAT while in suspend mode. If OUT is kept greater than BAT, such as when the high voltage input is present, the charge timer will not be reset when the part is put in suspend. A 2μA pull-down current is internally connected to this pin to ensure it is low at power up when the pin is not being driven externally.TIM ER (Pin 17): Timer Capacitor. Placing a capacitor, C TIMER, to GND sets the timer period. The timer period is:t TIMER(hours)=C TIMER•R PROG•3hours0.1µF•100kCharge time is increased if charge current is reduceddue to load current, thermal regulation and current limitselection (HPWR low).Shorting the TIME R pin to GND disables the batterycharging functions.HVOUT (Pin 18): Voltage Output of the High VoltageRegulator. When suffi cient voltage is present at HVOUT,the low voltage power path from IN to OUT will be discon-nected and the HVPR pin will be pulled low to indicatethat a high voltage wall adapter has been detected. TheL TC4090 high voltage regulator will maintain just enoughdifferential voltage between HVOUT and BAT to keep thebattery charger MOSFET out of dropout (typically 300mVfrom OUT to BAT). The L TC4090-5 high voltage regulatorwill provide a 5V output to the battery charger MOSFET.HVOUT should be bypassed with at least 22μF to GND.BOOST (Pin 19): This pin is used to provide drive voltage,higher than the input voltage, to the internal bipolar NPNpower switch.SW (Pin 20): The SW pin is the output of the internal highvoltage power switch. Connect this pin to the inductor,catch diode and boost capacitor.HVIN (Pin 21): High Voltage Regulator Input. The HVIN pinsupplies current to the internal high voltage regulation andto the internal high voltage power switch. The presenceof a high voltage input takes priority over the USB V BUSinput (i.e., when a high voltage input supply is detected,the USB IN to OUT path is disconnected). This pin mustbe locally bypassed.HVEN (Pin 22): High Voltage Regulator Enable Input. TheHVEN pin is used to disable the high voltage input path.Tie to ground to disable the high voltage input or tie to atleast 2.3V to enable the high voltage path. If this featureis not used, tie HVEN to the HVIN pin. This pin can alsobe used to soft-start the high voltage regulator; see theApplications Information section for more information.Exposed Pad (Pin 23): Ground. The exposed package padis ground and must be soldered to the PC board for properfunctionality and for maximum heat transfer (use severalvias directly under the L TC4090/L TC4090-5).PIN FUNCTIONS/104090fc分销商库存信息:LINEAR-TECHNOLOGYLTC4090EDJC#PBF LTC4090EDJC-5#PBF LTC4090EDJC#TRPBF LTC4090EDJC-5#TRPBF。

AD4Q數位四頻道接收機User guide for the Shure AD4Q Axient Digital quad channel receiver Version: 10.5 (2023-C)Table of ContentsAD4Q 數位四頻道接收機4 AD4Q Axient Digital Four-Channel Wireless Receiver4 Features 4附帶組件5安裝說明5硬體6接收機前面板 6 Receiver Back Panel 8功能表和設定9存取裝置設定功能表或頻道功能表 10主螢幕 10螢幕圖示 10裝置設定功能表11 AD4D 裝置設定參數 12頻道功能表參數 16 RF 設定18設定 RF（射頻）調整波段 18 IR Sync（紅外同步） 18手動設定頻率 19頻道掃描和群組掃描 19從頻譜管理器要求新頻率 20傳輸模式 20將發射機分配至發射機槽 21干擾管理 21頻道品質量表 22頻率分集 22 Quadversity（四元） 23天線偏移 23 RF 級聯連接埠 24韌體 24音訊設置24調節頻道增益和音訊輸出 24音調產生器 25耳機監聽 25系統增益 26連網26 Networking Receivers 26網路瀏覽器 30網路故障排除 30操作30分配裝置 ID 30分配頻道名稱 31控制器的鎖定和解鎖 31顯示屏幕選項 31將接收機設定儲存為使用者預設 31使用 IR（紅外）預設編程發射機 32加密 32冷卻風扇 32將接收機恢復為原廠設定 32故障排除33功率 33增益 33纜線 33介面鎖定 33加密不匹配 33韌件不匹配 33 Tx 電池過熱 33無線電頻率 (RF) 34聯絡客戶支援部門35規格35表格和示意圖 38接收機 頻帶39重要安全事項！40澳大利亞無線警告40認證41•••••••••◦◦•••••••••••AD4Q數位四頻道接收機AD4Q Axient Digital Four-Channel Wireless ReceiverThe AD4Q Axient Digital four-channel wireless receiver sets a new standard in transparent digital audio and maximum spectral efficiency. Groundbreaking performance features include wide tuning, low latency, high density (HD) mode, and Quadversity , ensuring solid performance in the most challenging RF environments. Networked control, AES3, AES67, and Dante output, and signal routing options bring a new level of management and flexibility to your entire workflow. Compatible with all Axient Digital transmitters.FeaturesAudio60 dB of gain adjustment offers compatibility with a wide range of input sources Dante networking for quick and easy channel managementDante Browse feature for headphone monitoring of all Dante channels, including third party components AES 256 encryption to protect audio channelsAutomatic limiter function protects against signal clipping, allowing for higher gain settings and preventing unexpected signal peaks Front panel connection for headphones with adjustable volumeI/OFour transformer-balanced XLR outputs (outputs 3 and 4 switchable AES3 digital)Four transformer-balanced 1/4'' outputsTwo Dante-enabled Ethernet ports, Two network control Ethernet ports with PoESplit-Redundant mode: two ports of Ethernet, two ports of DanteSwitched mode: four ports of Ethernet, Four ports of DanteNote : The receiver can only power 1 PoE device at a time.Locking AC power connectionAC power cascade to additional componentsOptional DC module available to support redundant powerRFTrue digital diversity reception per channel Quadversity mode for enhanced coverage Up to 210 MHz of tuning rangeChannel Quality meter displays signal-to-noise ratio of RF signalFrequency diversity with selection or combining modes for transmitters Antenna cascade for one additional receiverPreprogrammed group and channel maps with options to create custom groups Search for open frequencies via receiver using group and channel scan™™•••••••Perform full bandwidth scan for frequency coordination via Wireless Workbench Register up to eight transmitters to one receiver channelHigh Density transmission mode enables up to 47 active transmitters in one 6 MHz TV channel (up to 63 in one 8 MHz TV channel)Network ControlWireless Workbench control softwareShurePlus Channels mobile device control Console integrationControl systems support附帶組件接收機內含下列組件：硬體套件90XN1371隔板轉接器，BNC 95A89941/2 波長寬頻天線 (2)根據地區不同有所差別用於隔板安裝的 BNC-BNC 同軸射頻纜線（短）95B9023用於隔板安裝的 BNC-BNC 同軸射頻纜線（長）95C9023同軸 RF （射頻）級聯纜線95N2035交流電纜，VLock 根據地區不同有所差別交流電跨接纜線根據地區不同有所差別乙太網線纜 3 英尺95A33402乙太網跨接線纜95B33402安裝說明本元件設計適合用於音響架。

AD9954芯片中文数据表（部分）操作模式单音信号模式在单音信号模式下，DDS核使用了一个单独的调谐字（tuningword）。

存储在FTW0中的任何值可被用来做相位累加。

这个值仅能手动改变，通过向FTW0写一个新值并更新I/O来实现。

相位调整可通过相位偏置寄存器实现。

RAM可控制操作模式直接转换模式直接转换模式使能FSK调制或PSK调制。

AD9954在直接转换模式可以编程，其通过写RAM使能位为真并将每个期望的profile的RAM片段模式控制位编程成逻辑000（b）实现。

对于当前profile，该模式仅读取了RAM片段起始地址的内容。

直接转换模式下，没有地址ramping可用。

为了执行4-toneFSK，对于直接转换模式及一个唯一的起始地址值，使用者对每一个RAM片段控制字编程。

另外，RAM使能位被写为真，这使得RAM、RAM目的文件位被写成fale，设置RAM输出为频率调谐字。

Profile〈1：0〉输入为4-toneFSK数据输入。

当profile被改变时，存储在新的profile中的频率调谐字被加载到相位累加器中并且被用做相位连续型式中的当前存储值的增量。

相位-偏置字驱使相位偏置加法器。

对于数据而言，2-toneFSK可通过仅使用一个profilepin来完成。

对于为了PSK调制将AD9954编程和FSK是相似的，除了RAM目的文件位设置为逻辑“1”外，使RAM输出驱动相位偏置加法器。

FTW0驱动输入至相位累加器。

Togglingtheprofilepin改变（调制）当前相位值。

RAM的upper14位驱动相位加法器（〈31：18〉）。

当RAM目的文件位被设置时，RAM输出的Bit〈17:0〉未被使用。

直接转换模式下，无停留位（no-dwell）是一项禁忌注意事项。

Ramp-Up模式Ramp-Up模式，结合分割的RAM容量，允许多达4种不同的“weepprofile”在AD9954中编程。

海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ目录摘要 —————————————————————————2 创新之处 ———————————————————————2 关键词 ————————————————————————2 引言 —————————————————————————2 系统工作原理 —————————————————————3 直接数字频率合成 ———————————————————4 DDS 基本原理及性能特点 —————————————————5 采用 DDS 的 AD9851 ———————————————————6 AD9851 的原理 —————————————————————7 AD9851 在信号源中的应用 ————————————————8 AD9851 在本系统的应用电路 ———————————————9 低通滤波器（LPF） ——————————————————10 锁相环频率合成 ———————————————————11 锁相环频率合成 MC145151 在本电路中的应用 ————————12 压控振荡器（VCO） ———————————————————12 缓冲放大器 ——————————————————————13 单片机控制的整体电路 —————————————————14 功率放大 ———————————————————————15 本系统的软件设计 ———————————————————15 总调试 ————————————————————————25 结束语 ————————————————————————25 DDS 短波信号发生器技术指标 ——————————————26 所采用的仪器设备 ———————————————————26 所用软件 ———————————————————————26 参考文献 ———————————————————————26 参考网站 ———————————————————————27ｗｗｗ．ｆｐｇａ－ａｒ ｍ1．海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍDDS 短波信号发生器摘要： 本文主要介绍的是采用直接数字频率合成的短波信号发生器， 它 主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相 环频率合成部分、背光液晶显示部分、功率放大部分等组成。

AD9954- Direct Digital Synthesizer400 MSPS 14-Bit, 1.8 V CMOS功能： (2)应用 (2)概述 (2)AD9954电气特性 (3)最大操作范围 (4)Table 2. (4)管脚定义 (4)管脚功能描述 (4)典型的性能特性 (6)原理 (7)器件块 (7)控制寄存器位描述 (10)Other Register Descriptions 其他寄存器描述 (14)Programming AD9954 Features-- AD9954编程特性 (18)SERIAL PORT OPERATION串口操作 (19)INSTRUCTION BYTE指令字节 (20)SERIAL INTERFACE PORT PIN DESCRIPTION串行接口管脚描述 (20)MSB/LSB TRANSFERS (20)RAM I/O VIA SERIAL PORT (21)Power-Down Functions of the AD9954 AD9954省电功能 (21)功能：400MSPS 内部时钟 集成14位DAC可编程相位/幅度抖动 32位控制字相位噪声小于等于-120dbc/Hz@1kHz(DAC 输出)出色的动态性能>80db SFDR@160MHz （偏离100KHz ） 串行I/O 口控制 超高速模拟比较器 自动线性和非线性扫频能力 4种频率/相位偏移坡面 1.8v 电压供电软件或者硬件控制休眠内部集成1024字节*32位RAM 大多数输入口支持5v 电平PLL REFCLK 乘法器（4倍-20倍） 单晶振驱动内部时钟 相位调制能力 多芯片同步 应用敏捷LO 频率输出 可编程的时钟发生器雷达和扫频系统中的FM 啁啾源自动雷达测试和测量设备 声光设备驱动概述AD9954具有一个14位DAC 最高达400 MSPS 的DDS 。

AD9954使用了先进的DDS 技术，内部集成高速，高性能的DAC 形成数字可编程，完整的高频合成器，能产生高达200MHz 模拟正弦波的能力。

目前生产AD/DA的主要厂家有ADI、TI、BB、PHILIP、MOTOROLA等，武汉力源公司拥有多年从事电子产品的经验和雄厚的技术力量支持，已取得排名世界前列的模拟IC生产厂家ADI、TI 公司代理权，经营全系列适用各种领域/场合的AD/DA器件。

1. AD公司AD/DA器件AD公司生产的各种模数转换器(ADC)和数模转换器(DAC)(统称数据转换器)一直保持市场领导地位，包括高速、高精度数据转换器和目前流行的微转换器系统（MicroConvertersTM )。

1）带信号调理、1mW功耗、双通道16位AD转换器：AD7705AD7705是AD公司出品的适用于低频测量仪器的AD转换器。

它能将从传感器接收到的很弱的输入信号直接转换成串行数字信号输出，而无需外部仪表放大器。

采用Σ-Δ的ADC，实现16位无误码的良好性能，片内可编程放大器可设置输入信号增益。

通过片内控制寄存器调整内部数字滤波器的关闭时间和更新速率，可设置数字滤波器的第一个凹口。

在+3V电源和1MHz主时钟时， AD7705功耗仅是1mW。

AD7705是基于微控制器（MCU）、数字信号处理器（DSP）系统的理想电路，能够进一步节省成本、缩小体积、减小系统的复杂性。

应用于微处理器（MCU）、数字信号处理（DSP）系统，手持式仪器，分布式数据采集系统。

2）3V/5V CMOS信号调节AD转换器：AD7714AD7714是一个完整的用于低频测量应用场合的模拟前端，用于直接从传感器接收小信号并输出串行数字量。

它使用Σ-Δ转换技术实现高达24位精度的代码而不会丢失。

输入信号加至位于模拟调制器前端的专用可编程增益放大器。

调制器的输出经片内数字滤波器进行处理。

数字滤波器的第一次陷波通过片内控制寄存器来编程，此寄存器可以调节滤波的截止时间和建立时间。

AD7714有3个差分模拟输入（也可以是5个伪差分模拟输入）和一个差分基准输入。

单电源工作（+3V或+5V）。

AD420中文资料摘要：AD420是具有灵活串行数字接口的16住数模转换器，它带有SPI和Microwire总线接口，使用方便、性价比高。

介绍了AD420的引脚功能、电气特性,阐述了AD420与MSP430的接口技术，并给出了在MSP430控制下的实际应用电路及程序。

关键词：AD420；D/A转换；MSP430；电流环1 概述AD420是ADI公司生产的高精度、低功耗全数字电流环输出转换器。

AD420的输出信号可以是电流信号，也可以是电压信号。

其中电流信号的输出范围为4mA~20mA，0mA~20mA或0mA~24mA，具体可通过引脚RANGE SELECTl，RANGE SELECT2进行配置。

当需要输出电压信号时，它也能从一个隔离引脚提供电压输出，这时需外接一个缓冲放大器，可输出0V～5V，0V~10V，±5V 或±10V电压。

AD420具有灵活的串行数字接口(最大速率可达3.3 Mb/s)，使用方便、性价比高、抑制干扰能力强，非常适合用于高精度远程控制系统。

AD420与单片机的接口方式有2种：3线制和异步制。

单片机系统通过AD420可实现连续的模拟量输出。

其主要特点如下：宽泛的电源电压范围为12 V~32 V，输出电压范围为0V~-2.5 V；带有3线模式的SPI或Microwire接口，可采集连续的模拟输入信号，采用异步模式时仅需少量的信号线；数据输出引脚可将多个AD420器件连接成菊链型；上电初始化时，其输出最小值为0 mA，4 mA或O V；具有异步清零引脚，可将输出复位至最小值(0mA、4 mA或0V)；BOOST引脚可连接一个外部晶体管来吸收回路电流，降低功耗；只需外接少量的外部器件，就能达到较高的精度。

AD420采用24引脚SOIC和PDIP封装，表1是其引脚功能说明。

2 工作原理在AD420中，二阶调节器用于保持最小死区。

从调节器发出的单字节流控制开关电流源，两个连续的电阻电容装置进行过滤。

14-Bit, 105/125 MSPS, IF Sampling ADCAD9445 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.FEATURES125 MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p) 74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p) 77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p) 74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p) 73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p) 102 dBFS 2-tone SFDR with 30 MHz and 31 MHz92 dBFS 2-tone SFDR with 170 MHz and 171 MHz60 fsec rms jitterExcellent linearityDNL = ±0.25 LSB typicalINL = ±0.8 LSB typical2.0 V p-p to 4.0 V p-p differential full-scale inputBuffered analog inputsLVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available3.3 V and 5 V supply operationAPPLICATIONSMulticarrier, multimode cellular receiversAntenna array positioningPower amplifier linearizationBroadband wirelessRadarInfrared imagingMedical imagingCommunications instrumentationGENERAL DESCRIPTIONThe AD9445 is a 14-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip IF sampling track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates at up to a 125 MSPS conversion rate and is designed for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment.The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.FUNCTIONAL BLOCK DIAGRAMVREF05489-1REFBSENSE REFTFigure 1.Optional features allow users to implement various selectable operating conditions, including input range, data format select, high IF sampling mode, and output data mode.The AD9445 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C.PRODUCT HIGHLIGHTS1.High performance: outstanding SFDR performance for IFsampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.2.Ease of use: on-chip reference and high input impedancetrack-and-hold with adjustable analog input range and an output clock simplifies data capture.3.Packaged in a Pb-free, 100-lead TQFP/EP package.4.Clock duty cycle stabilizer (DCS) maintains overall ADCperformance over a wide range of clock pulse widths.5.OR (out-of-range) outputs indicate when the signal isbeyond the selected input range.6.RF enable pin allows users to configure the device foroptimum SFDR when sampling frequencies above 210 MHz (AD9445-125) or 240 MHz (AD9445-105).AD9445Rev. 0 | Page 2 of 40TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Product Highlights...........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 DC Specifications.........................................................................3 AC Specifications..........................................................................4 Digital Specifications...................................................................6 Switching Specifications..............................................................6 Timing Diagrams..........................................................................7 Absolute Maximum Ratings............................................................8 Thermal Resistance......................................................................8 ESD Caution..................................................................................8 Terminology.......................................................................................9 Pin Configurations and Function Descriptions.........................10 Equivalent Circuits.........................................................................15 Typical Performance Characteristics...........................................16 Theory of Operation......................................................................24 Analog Input and Reference Overview...................................24 Clock Input Considerations......................................................26 Power Considerations................................................................27 Digital Outputs...........................................................................27 Timing.........................................................................................27 Operational Mode Selection.....................................................28 Evaluation Board............................................................................29 Outline Dimensions.......................................................................37 Ordering Guide.. (37)REVISION HISTORY10/05—Revision 0: Initial VersionAD9445Rev. 0 | Page 3 of 40SPECIFICATIONSDC SPECIFICATIONSAVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND. Table 1.AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −7 +7 −7 +7 mV 25°C ±3 ±3 mV Gain Error Full −3 +3 −3 +3 % FSR 25°C −2 +2 −2 +2 % FSRDifferential Nonlinearity (DNL)1Full −0.6 ±0.25 +0.65 −0.6 ±0.25 +0.65 LSB 5 5Integral Nonlinearity (INL)125°C ±0.65 ±0.8 LSB Full −1.6 +1.6 −2 +2 LSBVOLTAGE REFERENCEOutput Voltage VREF = 1.0 V Full 0.9 1.0 1.1 0.9 1.0 1.1 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External VREF = 1.6 V) Full μA INPUT REFERRED NOISE 25°C 1.0 1.0 LSB rms ANALOG INPUT Input Span VREF = 1.6 V Full 3.2 3.2 V p-p VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 VExternal Input Common-Mode Voltage Full 3.1 3.9 3.1 3.9 VInput Resistance 2Full 1 1 kΩ Input Capacitance 2Full 6 6 pF POWER SUPPLIES Supply Voltage AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 VDRVDD—LVDS Outputs Full 3.0 3.6 3.0 3.6 VDRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 VSupply Current 1AVDD1 Full 335 364 384 424 mAAVDD21, 3Full 169 196 172 199 mA I DRVDD 1—LVDS Outputs Full 63 78 63 78 mAI DRVDD 1—CMOS Outputs Full 14 14 mAPSRROffset Full 1 1 mV/V Gain Full 0.2 0.2 %/VPOWER CONSUMPTIONLVDS Outputs Full 2.2 2.4 2.3 2.6 W CMOS Outputs (DC Input) Full 2.0 2.1 W1Measured at the maximum clock rate, f IN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 2Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3For RF ENABLE = AVDD1, I AVDD2 increases by ~30 mA, which increases power dissipation.AD9445Rev. 0 | Page 4 of 40AC SPECIFICATIONSAVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal trimmed reference (1.0 V mode), A IN = −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted. Table 2.AD9445BSVZ-105 AD9445BSVZ-125Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f IN = 10 MHz 25°C 74.3 74.1 dB f IN = 30 MHz 25°C 73.3 74.3 72.9 73.8 dB Full 73 72.5 dB f IN = 170 MHz 25°C 72.9 73.6 72.3 73.2 dBf IN = 225 MHz 125°C 72.2 73 72 72.9 dB Full 72.2 71.4 dBf IN = 300 MHz 225°C 71.4 72.1 71.3 72 dB f IN = 400 MHz 225°C 71 71 dBf IN = 450 MHz 225°C 70.5 70.5 dB f IN = 10 MHz (3.2 V p-p Input) 25°C 77.6 77.3 dB f IN = 30 MHz (3.2 V p-p Input) 25°C 77.5 77.3 dB f IN = 170 MHz (3.2 V p-p Input) 25°C 76 76 dBf IN = 225 MHz (3.2 V p-p Input)125°C 75.3 75.4 dB f IN = 300 MHz (3.2 V p-p Input)225°C 73.7 73.5 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) f IN = 10 MHz 25°C 74.2 73.9 dB f IN = 30 MHz 25°C 73.2 74.2 72.8 73.7 dB Full 72.8 72.3 dB f IN = 170 MHz 25°C 72.3 73.3 72.4 73.0 dBf IN = 225 MHz 125°C 71.4 72.5 71.9 72.5 dB Full 71.3 70.7 dB f IN = 300 MHz 225°C 70.2 71.7 69.3 71.5 dBf IN = 400 MHz 225°C 67.2 66.3 dB f IN = 450 MHz 225°C 65.2 64.3 dB f IN = 10 MHz (3.2 V p-p Input) 25°C 77.4 76.9 dB f IN = 30 MHz (3.2 V p-p Input) 25°C 77.3 76.8 dB f IN = 170 MHz (3.2 V p-p Input) 25°C 75.7 75.4 dBf IN = 225 MHz (3.2 V p-p Input)125°C 75.1 75.2 dBf IN = 300 MHz (3.2 V p-p Input)225°C 72.5 71.8 dB EFFECTIVE NUMBER OF BITS (ENOB) f IN = 10 MHz 25°C 12.2 12.2 Bits f IN = 30 MHz 25°C 12.2 12.1 Bits f IN = 170 MHz 25°C 12.1 12.0 Bitsf IN = 225 MHz 125°C 12.0 12.0 Bits f IN = 300 MHz 225°C 11.8 11.8 Bitsf IN = 400 MHz 225°C 11.7 11.7 Bits f IN = 450 MHz 225°C 11.6 11.6 BitsAD9445Rev. 0 | Page 5 of 40AD9445BSVZ-105 AD9445BSVZ-125Parameter Temp Min Typ Max Min Typ Max UnitSPURIOUS-FREE DYNAMIC RANGE(SFDR, Second or Third Harmonic) f IN = 10 MHz 25°C 95 95 dBc f IN = 30 MHz 25°C 84 92 85 94 dBc Full 83 82 dBc f IN = 170 MHz 25°C 82 94 80 91 dBc f IN = 225 MHz 125°C 76 87 83 88 dBc Full 75 75 dBc f IN = 300 MHz 225°C 76 87 75 87 dBcf IN = 400 MHz 225°C 75 73 dBc f IN = 450 MHz 225°C 70 69 dBc f IN = 10 MHz (3.2 V p-p Input) 25°C 92 92 dBc f IN = 30 MHz (3.2 V p-p Input) 25°C 88 91 dBc f IN = 170 MHz (3.2 V p-p Input) 25°C 86 86 dBc f IN = 225 MHz (3.2 V p-p Input)125°C 81 80 dBcf IN = 300 MHz (3.2 V p-p Input)225°C 77 76 dBcWORST SPUR EXCLUDING SECOND ORTHIRD HARMONICS f IN = 10 MHz 25°C −97 −97 dBc f IN = 30 MHz 25°C −99 −90 −98 −89 dBc Full −90 −88 dBc f IN = 170 MHz 25°C −99 −92 −93 −85 dBc f IN = 225 MHz 125°C −94 −88 −94 −84 dBc Full −86 −80 dBc f IN = 300 MHz 225°C −97 −90 −92 −82 dBcf IN = 400 MHz 225°C −93 −93 dBc f IN = 450 MHz 225°C −82 −87 dBc f IN = 10 MHz (3.2 V p-p Input) 25°C −97 −95 dBc f IN = 30 MHz (3.2 V p-p Input) 25°C −97 −95 dBc f IN = 170 MHz (3.2 V p-p Input) 25°C −97 −95 dBc f IN = 225 MHz (3.2 V p-p Input)125°C −95 −94 dBcf IN = 300 MHz (3.2 V p-p Input)225°C −93 −91 dBc TWO-TONE SFDRf IN = 30.3 MHz @ −7 dBFS,31.3 MHz @ −7 dBFS25°C 102 102 dBFS f IN = 170.3 MHz @ −7 dBFS,171.3 MHz @ −7 dBFS 25°C 92 91 dBFS ANALOG BANDWIDT H Full 615 615 M H z1 RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125. 2RF ENABLE = high (AVDD1).AD9445Rev. 0 | Page 6 of 40DIGITAL SPECIFICATIONSAVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , R LVDS_BIAS = 3.74 kΩ, unless otherwise noted. Table 3.AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full 2.0 2.0 V Low Level Input Voltage Full 0.8 0.8 VHigh Level Input Current Full 200 200 μALow Level Input Current Full −10 +10 −10 +10 μAInput Capacitance Full 2 2 pFDIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)1DRVDD = 3.3 VHigh Level Output Voltage Full 3.25 3.25 VLow Level Output Voltage Full 0.2 0.2 V DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)V OD Differential Output Voltage 2Full 247 545 247 545 mVV OS Output Offset Voltage Full 1.125 1.375 1.125 1.375 VCLOCK INPUTS (CLK+, CLK−)Differential Input Voltage Full 0.2 0.2 VCommon-Mode Voltage Full 1.3 1.5 1.6 1.3 1.5 1.6 V Differential Input Resistance Full 1.1 1.4 1.7 1.1 1.4 1.7 kΩDifferential Input Capacitance Full 2 2 pF1 Output voltage levels measured with 5 pF load on each output.2LVDS R TERM = 100 Ω.SWITCHING SPECIFICATIONSAVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , unless otherwise noted. Table 4.AD9445BSVZ-105 AD9445BSVZ-125 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full 105 125 MSPS Minimum Conversion Rate Full 10 10 MSPS CLK Period Full 9.5 8.0 nsCLK Pulse Width High 1(t CLKH ) Full 3.8 3.2 nsCLK Pulse Width Low 1 (t CLKL ) Full 3.8 3.2 ns DATA OUTPUT PARAMETERSOutput Propagation Delay—CMOS (t PD )2(Dx, DCO+) Full 3.35 3.35 ns Output Propagation Delay—LVDS (t PD )3 (Dx+), (t CPD )3 (DCO+) Full 2.1 3.6 4.8 2.3 3.6 4.8 ns Pipeline Delay (Latency) Full 13 13 CyclesAperture Delay (t A ) Full nsAperture Uncertainty (Jitter, t J ) Full 60 60 fsecrms1 With duty cycle stabilizer (DCS) enabled.2Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. 3LVDS R TERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.AD9445Rev. 0 | Page 7 of 40TIMING DIAGRAMSA INCLK+CLK–DATA OUTDCO+DCO–CPD05489-002Figure 2. LVDS Mode Timing Diagram05489-003VINCLK+CLK–DX DCO+DCO–Figure 3. CMOS Timing DiagramAD9445Rev. 0 | Page 8 of 40ABSOLUTE MAXIMUM RATINGSTable 5.Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.With Respect To Parameter RatingELECTRICAL AVDD1 AGND −0.3 V to +4 V AVDD2 AGND −0.3 V to +6 V DRVDD DGND −0.3 V to +4 V AGND DGND −0.3 V to +0.3 V THERMAL RESISTANCEAVDD1 DRVDD −4 V to +4 V The heat sink of the AD9445 package must be soldered to ground. AVDD2 DRVDD −4 V to +6 V AVDD2 AVDD1 −4 V to +6 V Table 6.D0± to D13± DGND –0.3 V to DRVDD + 0.3 V Package Type θJA θJB θJCUnit CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V100-lead TQFP/EP19.88.3 2 °C/WAGND –0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCSMODE, DFS, SFDR, RF ENABLETypical θJA = 19.8°C/W (heat sink soldered) for multilayerboard in still air.VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V VREF AGND –0.3 V to AVDD1 + 0.3 V Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board in still air.SENSE AGND –0.3 V to AVDD1 + 0.3 V REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path.ENVIRONMENTAL–65°C to +125°C Storage TemperatureRangeAirflow increases heat dissipation, effectively reducing θJA . Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θJA . It is required that the exposed heat sink be soldered to the ground plane.–40°C to +85°C Operating Temperature Range300°C Lead Temperature(Soldering 10 sec) Junction Temperature 150°CESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD9445Rev. 0 | Page 9 of 40TERMINOLOGYAnalog Bandwidth (Full Power Bandwidth)Minimum Conversion RateThe clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.Aperture Delay (t A )Offset ErrorThe major carry transition should occur for an analog value of ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, t J )Out-of-Range Recovery TimeThe sample-to-sample variation in aperture delay.The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.Clock Pulse Width and Duty CyclePulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Output Propagation Delay (t PD )The delay between the clock rising edge and the time when all bits are within valid logic levels.Differential Nonlinearity (DNL, No Missing Codes)Power-Supply Rejection RatioAn ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit.Signal-to-Noise and Distortion (SINAD)Effective Number of Bits (ENOB)The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:()6.021.76−=SINAD ENOB Signal-to-Noise Ratio (SNR)The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc.Gain ErrorThe first code transition should occur at an analog value of½ LSB above negative full scale. The last transition should occur at an analog value of 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.Spurious-Free Dynamic Range (SFDR)The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale).Integral Nonlinearity (INL)The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.Temperature DriftThe temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at T MIN or T MAX .Total Harmonic Distortion (THD)The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components.Maximum Conversion RateThe clock rate at which parametric testing is performed.Two-Tone SFDRThe ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.AD9445Rev. 0 | Page 10 of 40PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSD8+D8–D7+D6–D6+D7–DRGND DCO+DCO–D5+DRVDD DRGND D4+D4–D3+D3–D2+D2–D1+D1–D0+D0– (LSB)DNC DNCD5–F E N A B L EG N DG N DV D D 1V D D 1V D D 1V D D 1V D D 1V D D 1G N DR +R –R V D DR G N D 13+ (M S B )13–12+12–11+11–10+10–9+9–R V D DA V D D 2A V D D 2A V D D 2A V D D 2A V D D 2A V D D 2A V D D 1A V D D 1A V D D 1A V D D 2A V D D 1A V D D 2A V D D 1A G N DC L K +C L K –A G N DA V D D 1A V D D 1A V D D 1A G N DD R G N DD R V D DD N CD N CDNCOUTPUT MODEDFSSENSE AVDD1LVDS_BIASDCS MODE VREF AGNDREFT AVDD2AVDD2AVDD2AVDD2AVDD2AVDD2AVDD1AVDD1AVDD1AGNDVIN+VIN–AGND AVDD2REFB 05489-004Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS ModeTable 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS ModePin No. Mnemonic Description1 DCSMODEClock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) toenable DCS (recommended); DCS = high (AVDD1) to disable DCS.2, 49 to 52 DNC Do Not Connect. These pins should float.3 OUTPUTMODECMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;OUTPUT MODE = 1 (AVDD1) for LVDS outputs.4 DFSData Format Select Pin. CMOS control pin that determines the format of the output data.DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.6, 18 to 20, 32 to 34, 36, 38,43 to 45, 92 to 97AVDD1 3.3 V (±5%) Analog Supply.7 SENSEReference Mode Selection. Connect to AGND for internal 1 V reference; connect toAVDD1 for external reference.8 VREF1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.Decouple to ground with 0.1 μF and 10 μF capacitors.9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.10 REFTDifferential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB(Pin 14) with 0.1 μF and 10 μF capacitors.11 REFBDifferential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT(Pin 13) with 0.1 μF and 10 μF capacitors.12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).22 VIN+AnalogInput—True.23 VIN−AnalogInput—Complement.40 CLK+ClockInput—True.41 CLK−ClockInput—Complement.47, 63, 75, 87 DRGND Digital Output Ground.48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).53 D0− (LSB) D0 Complement Output Bit (LVDS Levels).54D0+ D0 True Output Bit.55D1− D1 Complement Output Bit.56D1+ D1TrueOutputBit.57D2− D2 Complement Output Bit.58D2+ D2TrueOutputBit.59D3− D3 Complement Output Bit.60D3+ D3TrueOutputBit.61D4− D4 Complement Output Bit.62D4+ D4TrueOutputBit.65 D5− D5 Complement Output Bit.66 D5+D5TrueOutputBit.67 DCO− Data Clock Output—Complement.68 DCO+ Data Clock Output—True.69 D6− D6 Complement Output Bit.70 D6+D6TrueOutputBit.71 D7− D7 Complement Output Bit.72 D7+D7TrueOutputBit.73 D8− D8 Complement Output Bit.74 D8+D8TrueOutputBit.77 D9− D9 Complement Output Bit.78 D9+D9TrueOutputBit.79D10− D10 Complement Output Bit.80D10+ D10 True Output Bit.81D11− D11 Complement Output Bit.82D11+ D11 True Output Bit.Rev. 0 | Page 11 of 40Pin No. Mnemonic Description83 D12− D12 Complement Output Bit.84 D12+ D12 True Output Bit.85 D13− D13 Complement Output Bit.86 D13+ (MSB) D13 True Output Bit.89 OR− Out-of-Range Complement Output Bit.90 OR+ Out-of-Range True Output Bit.ENABLE100 RFRF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration ofthe AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDRperformance for applications with analog input frequencies <210 MHz for 125 MSPSspeed grade and <230 MHz for the 105 MSPS speed grade. For applications with analoginputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speedgrade, this pin should be connected to AVDD1 for optimum SFDR performance. Powerdissipation from AVDD2 increases by 150 mW to 200 mW.Rev. 0 | Page 12 of 40Rev. 0 | Page 13 of 40D2D1D0 (LSB)DNC DNC DNC DRGND DCO+DCO–DNC DRVDD DRGND DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNC DNCDNC F E N A B L EG N DG N DV D D 1V D D 1V D D 1V D D 1V D D 1V D D 1G N DR13 (M S B )R V D DR G N D 1211109876543R V D DA V D D 2A V D D 2A V D D 2A V D D 2A V D D 2A V D D 2A V D D 1A V D D 1A V D D 1A V D D 2A V D D 1A V D D 2A V D D 1A G N DC L K +C L K –A G N DA V D D 1A V D D 1A V D D 1A G N DD R G N DD R V D DD N CD N CDNCOUTPUT MODEDFSSENSE AVDD1LVDS_BIASDCS MODE VREF AGNDREFT AVDD2AVDD2AVDD2AVDD2AVDD2AVDD2AVDD1AVDD1AVDD1AGNDVIN+VIN–AGNDAVDD2REFB 05489-005Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS ModeTable 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS ModePin No. Mnemonic Description1 DCSMODEClock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enableDCS (recommended); DCS = high (AVDD1) to disable DCS.2, 49 to 62, 65 to 66, 69 to 71 DNC Do Not Connect. These pins should float.3 OUTPUTMODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode; OUTPUT MODE = 1 (AVDD1) for LVDS outputs.4 DFSData Format Select Pin. CMOS control pin that determines the format of the output data.DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.6, 18 to 20, 32 to 34, 36, 38,43 to 45, 92 to 97AVDD1 3.3 V (±5%) Analog Supply.7 SENSEReference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 forexternal reference.8 VREF1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.Decouple to ground with 0.1 μF and 10 μF capacitors.9, 21, 24, 39, 42, 46, 91, 98, 99, Exposed Heat Sink AGND Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND.10 REFTDifferential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB(Pin 14) with 0.1 μF and 10 μF capacitors.11 REFBDifferential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT(Pin 13) with 0.1 μF and 10 μF capacitors.12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).22 VIN+AnalogInput—True.23 VIN−AnalogInput—Complement.40 CLK+ClockInput—True.41 CLK−ClockInput—Complement.47, 63, 75, 87 DRGND Digital Output Ground.48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).67 DCO− Data Clock Output—Complement.68 DCO+ Data Clock Output—True.72 D0 (LSB) D0 True Output Bit (CMOS levels).73 D1D1TrueOutputBit.74 D2D2TrueOutputBit.77 D3D3TrueOutputBit.78 D4D4TrueOutputBit.79 D5D5TrueOutputBit.80 D6D6TrueOutputBit.81 D7D7TrueOutputBit.82 D8D8TrueOutputBit.83 D9D9TrueOutputBit.84 D10 D10 True Output Bit.85 D11 D11 True Output Bit.86 D12 D12 True Output Bit.89 D13 (MSB) D13 True Output Bit.90 OR Out-of-Range True Output Bit.100 RFENABLERF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog inputfrequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade.For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHzfor the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR.Power dissipation from AVDD2 increases by 150 mW to 200 mW.Rev. 0 | Page 14 of 40。