93C46

93C46/93c06/93c56/93c66/93c86的驱动程序(C51)/*————————————————————〖说明〗SPI总线驱动程序包括的普通封装标准模式,特殊封装标准模式默认的晶振。

〖文件〗﹫2003/5/12—————————————————————*//*通用93c06-93c86系列使用说明93c06=93c4693c56=93c6693c76=93c86dipx 可以自行定义*/#include ““#include ““/*-----------------------------------------------------SPI 93cXX系列时序函数调用（普通封装）调用方式：自行定义﹫2001/05/12函数说明：私有函数，封装各接口定义-----------------------------------------------------*/#define di_93 dip3#define sk_93 dip2#define cs_93 dip1#define do_93 dip4#define gnd_93 dip5#define org_93 dip6sbit cs_93=P1 ;sbit sk_93=P1;sbit di_93=P1;sbit do_93=P1;sbit org_93=P0;/*-----------------------------------------------------SPI93cXX系列时序函数调用（普通封装）调用方式：void high46(void) ---高8位函数调用void low46(void) ---低8位函数调用﹫2001/05/12函数说明：私有函数，SPI专用93c46普通封装驱动程序-----------------------------------------------------*/void high46(void){di_93=1;sk_93=1; _nop_();sk_93=0;_nop_();}void low46(void){di_93=0;sk_93=1;_nop_();sk_93=0;_nop_();}void wd46(unsigned char dd) {unsigned char i;for (i=0;i=0x80) high46(); else low46();dd=dd=0x80) high46a(); else low46a();dd=dd>1;address=address|0x80; address=address|0x80;high46();wd46(address);dat1=rd46();dat0=rd46();cs_93=0;dat=dat1*256 dat0;return(dat);}bit write93c46_word(unsigned char address,unsigned int dat) {unsigned char e,temp=address;e=0;while (e>=1;//??address|=0x40;wd46(address);wd46(dat/256);wd46(dat%6);cs_93=0;_nop_();cs_93=1;time=0;do_93=1;while (1){if (do_93==1) break;if (time>20) break;}cs_93=0;if (read93c46_word(temp)==dat)return(0);}e ;}return(1);}/*-----------------------------------------------------SPI93c57系列函数调用（举例）调用方式：bit write93c57_word(unsigned int address,unsigned int dat) ﹫2001/05/12函数说明：私有函数，SPI专用-----------------------------------------------------*/void ewen57(void){_nop_();cs_93=1;dip7=0;high46();low46();wd46(0x60);cs_93=0;unsigned int read93c57_word(unsigned int address){unsigned int dat;unsigned char dat0,dat1;gnd_93=0;cs_93=sk_93=0;org_93=1;cs_93=1;address=address>>1;high46();high46();wd46(address);dat1=rd46();dat0=rd46();cs_93=0;dat=dat1*256 dat0;return(dat);}bit write93c57_word(unsigned int address,unsigned int dat) {unsigned char e;unsigned int temp=address;e=0;while (e>=1;address|=0x80;wd46(address);wd46(dat/256);wd46(dat%6);cs_93=0;_nop_();cs_93=1;time=0;do_93=1;while (1){if (do_93==1) break;if (time>20) break;}cs_93=0;if (read93c57_word(temp)==dat) {return(0);}e ;}return(1);}/*-----------------------------------------------------SPI93c56系列函数调用（举例）调用方式：bit write93c56_word(unsigned int address,unsigned int dat) ﹫2001/05/12函数说明：私有函数，SPI专用-----------------------------------------------------*/void ewen56(void){_nop_();cs_93=1;high46();low46();low46();wd46(0xc0);cs_93=0;}unsigned int read93c56_word(unsigned char address){unsigned int dat;unsigned char dat0,dat1;gnd_93=0;cs_93=sk_93=0;org_93=1;cs_93=1;address=address>>1;high46();high46();low46();wd46(address);dat1=rd46();dat0=rd46();cs_93=0;dat=dat1*256 dat0;return(dat);}bit write93c56_word(unsigned char address,unsigned int dat) {unsigned char e;unsigned int temp=address;e=0;while (e>=1;wd46(address);wd46(dat/256);wd46(dat%6);cs_93=0;_nop_();cs_93=1;TH0=0;time=0;do_93=1;while (1){if (do_93==1) break;if (time) break;}cs_93=0;if (read93c56_word(temp)==dat) {return(0);}e ;}return(1);}/*-----------------------------------------------------SPI93c76与SPI93c86系列函数调用（举例）调用方式：bit write93c76_word(unsigned int address,unsigned int dat) ﹫2001/05/12函数说明：私有函数，SPI专用-----------------------------------------------------*/void ewen76(void){_nop_();cs_93=1;dip7=1;high46();low46();low46();high46();high46();wd46(0xff);cs_93=0;}unsigned int read93c76_word(unsigned int address){unsigned char dat0,dat1;gnd_93=0;cs_93=sk_93=0;org_93=1;cs_93=1;address>>=1;high46();high46();low46();if((address&0x200)==0x200) high46();else low46();if ((address&0x100)==0x100) high46();else low46();wd46(address);dat1=rd46();dat0=rd46();cs_93=0;return(dat1*256|dat0);}bit write93c76_word(unsigned int address,unsigned int dat) {unsigned char e;unsigned int temp=address;e=0;address>>=1;while (e10) break;}cs_93=0;e ;}return(1);}/*----------------------------------------------------- 主函数调用（举例）调用方式：main() ﹫2001/05/12函数说明：私有函数，SPI专用-----------------------------------------------------*/ main(){ bit b;unsigned int i;unsigned int j[32],k;for(i=0;i<32;i )j[i]=read93c56_word(i);for(i=0;i<32;i )write93c56_word(i,0x0909);i=0;b=write93c56_word(i,0x0909); j[i]=read93c56_word(i);i=1;b=write93c56_word(i,0x1111); j[i]=read93c56_word(i);i=2;b=write93c56_word(i,0x2222); j[i]=read93c56_word(i);}。

IS93C46BISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1,024-BIT SERIAL ELECTRICALLY ERASABLE PROMJULY 2003FUNCTIONAL BLOCK DIAGRAMFEATURES•Industry-standard Microwire Interface —Non-volatile data storage —Low voltage operation: Vcc = 2.5V to 5.5V—Full TTL compatible inputs and outputs —Auto increment for efficient data dump •x16 bit organization•Hardware and software write protection—Defaults to write-disabled state at power-up —Software instructions for write-enable/disable •Enhanced low voltage CMOS E 2PROM technology•Versatile, easy-to-use Interface —Self-timed programming cycle —Automatic erase-before-write —Programming status indicator —Word and chip erasable—Chip select enables power savings •Durable and reliable—40-year data retention after 1M write cycles —1 million write cycles —Unlimited read cycles — Schmitt-trigger inputs•Industrial and Automotive Temperature GradeDESCRIPTIONThe IS93C46B is a low-cost 1kb non-volatile,ISSI ® serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46B contains power-efficient read/write memory, and organization of 64 words of 16 bits.The IS93C46B is fully backward compatible with IS93C46.An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The self-timed write cycle includes an automatic erase-before-writecapability. The device can output any number of consecutive words using a single READ instruction.2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A IS93C46BISSI®PIN CONFIGURATIONS8-Pin JEDEC SOIC “G”8-Pin JEDEC SOIC “GR”PIN DESCRIPTIONSCS Chip Select SK Serial Data Clock D IN Serial Data Input D OUT Serial Data Output NC Not Connected Vcc Power GNDGroundinstruction begins with a start bit of the logical “1” or HIGH. Following this are the opcode (2 bits),address field (6 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clock-speed flexibility. Upon completion of buscommunication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.Read (READ)The READ instruction is the only instruction that outputs serial data on the D OUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical “0” bit precedes the actual 16-bit output data string.) The output on D OUT changes during the low-to-high transitions of SK (see Figure 3).Low Voltage ReadThe IS93C46B has been designed to ensure that data read operations are reliable in low voltage environments.They provide accurate operation with Vcc as low as 2.5V.Auto Increment Read OperationsIn the interest of memory transfer operation applications,the IS93C46B has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location ad-dress. Once the 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continu-ously with CS HIGH until the chip select (CS) control pin is brought LOW . This allows for single instruction data dumps to be executed with a minimum of firmware overhead.ApplicationsThe IS93C46B is very popular in many high-volume applications which require low-power, low-density storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics.Endurance and Data RetentionThe IS93C46B is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles.Device OperationsThe IS93C46B is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each12348765CS SK D IN D OUTVCC NC NC GND12348765NC VCC CS SKNC GND D OUT D IN12348765CS SK D IN D OUTVCC NC NC GND(Rotated)8-Pin DIP, 8-Pin TSSOPIS93C46BISSI®Write All (WRALL)The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 250 ns (t CS ), the D OUT pin indicates the READY/BUSY status of the chip (see Figure 6).Write Disable (WDS)The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against acci-dental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.Erase Register (ERASE)After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of t CS , will cause D OUT to indicate the READ/BUSY status of the chip: a logical “0” indicates programming is still in progress;a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).Erase All (ERAL)Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9).Write Enable (WEN)The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL,ERASE, and ERAL) can be done. When Vcc is applied,this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)Write (WRITE)The WRITE instruction includes 16 bits of data to be written into the specified register. After the last data bit has been applied to D IN , and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN).If CS is brought HIGH, after a minimum wait of 250 ns (5V operation) after the falling edge of CS (t CS ) D OUT will indicate the READY/BUSY status of the chip. Logical “0”means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle,t WP ; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.INSTRUCTION SET - IS93C46B16-bit OrganizationInstruction Start BitOP Code Address (1)Input DataREAD110(A 5-A 0)—WEN (Write Enable)10011xxxx —WRITE101(A 5-A 0)(D 15-D 0) (2)WRALL (Write All Registers)10001xxxx (D 15-D 0) (2)WDS (Write Disable)10000xxxx —ERASE111(A 5-A 0)—ERAL (Erase All Registers)10010xxxx—Notes:1. x = Don't care bit.2.If input data is not 16 bits exactly, the last 16 bits will be taken as input data.IS93C46B ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV GND Voltage with Respect to GND–0.3 to +6.5VT BIAS Temperature Under Bias (Industrial)–40 to +85°CT BIAS Temperature Under Bias (Automotive)–40 to +125°CT STG Storage Temperature–65 to +150°CNotes:1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGERange Ambient Temperature V C CCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5V or 4.5V to 5.5VCAPACITANCESymbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V5pFC OUT Output Capacitance V OUT = 0V5pF4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®DC ELECTRICAL CHARACTERISTICST A = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial, and –40°C to +125°C for Automotive.Symbol Parameter Test Conditions Vcc Min.Max.Unit V OL Output LOW Voltage I OL = 100 µA 2.5V to 5.5V—0.2V V OL1Output LOW Voltage I OL = 2.1 mA 4.5V to 5.5V—0.4V V OH Output HIGH Voltage I OH = –100 µA 2.5V to 5.5V V CC – 0.2—V V OH1Output HIGH Voltage I OH = –400 µA 4.5V to 5.5V 2.4—V V IH Input HIGH Voltage 2.5V to 5.5V0.7X V CC V CC+1V4.5V to5.5V0.7X V CC V CC+1V IL Input LOW Voltage 2.5V to 5.5V–0.30.2X V CC V4.5V to5.5V–0.30.8I LI Input Leakage V IN = 0V to V CC (CS, SK,D IN,ORG)0 2.5µA I LO Output Leakage V OUT = 0V to V CC, CS = 0V0 2.5µA N o t e s:Automotive grade devices in this table are tested with Vcc = 2.7V to 5.5V and 4.5V to 5.5V.IS93C46B ISSI®POWER SUPPLY CHARACTERISTICST A = 0°C to +70°C for CommercialSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—10µA5.0V—30µAPOWER SUPPLY CHARACTERISTICST A = –40°C to +85°C for IndustrialSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—2µA5.0V—4µAPOWER SUPPLY CHARACTERISTICST A = –40°C to +125°C for AutomotiveSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—3µA5.0V—8µA6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC ELECTRICAL CHARACTERISTICST A = T A = 0°C to +70°C for Commercial, –40°C to +85°C for IndustrialSymbol Parameter Test Conditions Vcc Min.Max.Unitf SK SK Clock Frequency 2.5V to 5.5V01Mhz2.7V to 5.5V01Mhz4.5V to5.5V02Mhzt SKH SK HIGH Time 2.5V to 5.5V500—ns2.7V to 5.5V350—ns4.5V to5.5V250—nst SKL SK LOW Time 2.5V to 5.5V500—ns2.7V to 5.5V350—ns4.5V to5.5V250—nst CS Minimum CS LOW Time 2.5V to 5.5V500—ns2.7V to 5.5V250—ns4.5V to5.5V250—nst CSS CS Setup Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V50—ns4.5V to5.5V50—nst DIS Din Setup Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V100—ns4.5V to5.5V100—nst CSH CS Hold Time Relative to SK 2.5V to 5.5V0—ns2.7V to 5.5V0—ns4.5V to5.5V0—nst DIH Din Hold Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V100—ns4.5V to5.5V100—nst PD1Output Delay to “1”AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—350ns4.5V to5.5V—250nst PD0Output Delay to “0”AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—350ns4.5V to5.5V—250nst SV CS to Status Valid AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—250ns4.5V to5.5V—250nst DF CS to Dout in 3-state AC Test, CS=VIL 2.5V to 5.5V—200ns2.7V to 5.5V—200ns4.5V to5.5V—100nst WP Write Cycle Time 2.5V to 5.5V—10ms2.7V to 5.5V—10ms4.5V to5.5V—5msN o t e s:1. C L = 100pFIS93C46B ISSI®AC ELECTRICAL CHARACTERISTICST A = –40°C to +125°C for AutomotiveSymbol Parameter Test Conditions Vcc Min.Max.Unitf SK SK Clock Frequency 2.7V to 5.5V01Mhz4.5V to5.5V02Mhzt SKH SK HIGH Time 2.7V to 5.5V500—ns4.5V to5.5V250—nst SKL SK LOW Time 2.7V to 5.5V500—ns4.5V to5.5V250—nst CS Minimum CS LOW Time 2.7V to 5.5V250—ns4.5V to5.5V250—nst CSS CS Setup Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V50—nst DIS Din Setup Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V100—nst CSH CS Hold Time Relative to SK 2.7V to 5.5V0—ns4.5V to5.5V0—nst DIH Din Hold Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V100—nst PD1Output Delay to “1”AC Test 2.7V to 5.5V—400ns4.5V to5.5V—250nst PD0Output Delay to “0”AC Test 2.7V to 5.5V—400ns4.5V to5.5V—250nst SV CS to Status Valid AC Test 2.7V to 5.5V—250ns4.5V to5.5V—250nst DF CS to Dout in 3-state AC Test, CS=VIL 2.7V to 5.5V—200ns4.5V to5.5V—100nst WP Write Cycle Time 2.7V to 5.5V—10ms4.5V to5.5V—5msN o t e s:1. C L = 100pF8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC WAVEFORMSFIGURE 2. SYNCHRONOUS DATA TIMINGNotes:To determine address bits An-A0 and data bits Dm-Do, see Instruction Set.IS93C46B ISSI®AC WAVEFORMSFIGURE 4. WRITE ENABLE (WEN) TIMINGNotes:1. After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status(D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.2. To determine address bits A n-A0 and data bits D m-D0, see Instruction Set.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC WAVEFORMSFIGURE 6. WRITE ALL (WRALL) TIMINGIntegrated Silicon Solution, Inc. — — 1-800-379-477411 R e v.A07/23/03IS93C46B ISSI®AC WAVEFORMSFIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMINGNote for Figures 8 and 9:After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status (D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A07/23/03IS93C46B ISSI®ORDERING INFORMATIONCommercial: 0ºC to +70ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.5V to 5.5V IS93C46B-3P300-mil Plastic DIPIS93C46B-3G SOIC (rotated) JEDECIS93C46B-3GR SOIC JEDECIS93C46B-3Z169-mil TSSOPORDERING INFORMATIONIndustrial Range: -40ºC to +85ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.5V to 5.5V IS93C46B-3PI300-mil Plastic DIPIS93C46B-3GI SOIC (rotated) JEDECIS93C46B-3GRI SOIC JEDECIS93C46B-3ZI169-mil TSSOPORDERING INFORMATIONAutomotive Range: -40ºC to +125ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.7V to 5.5V IS93C46B-3PA300-mil Plastic DIPIS93C46B-3GRA SOIC JEDEC* The specification allows for higher speed. Please see the AC Charateristics for more information. Integrated Silicon Solution, Inc. — — 1-800-379-477413 R e v.A07/23/03。

AT93C46中文资料详解AT93C46 是1K的串行EEPROM存储器器件，它们可配置为16位(ORG 管脚接Vcc)或者8位(ORG管脚接GND)的寄存器。

每个寄存器都可通过DI(或DO管脚)串行写入(或读出)。

AT93C46 内部有一个指令缓存器储存传输进来的串行数据，再由指令译码控制逻辑与内部频率产生器，在指定的地址将数据作读取或写入的动作。

AT93C46采用Catalyst公司先进的CMOS EEPROM浮动闸(floating gate)技术制造而成。

器件可采用8脚DIP，8脚SOIC或8脚TSSOP 的封装形式。

AT93C46 集成电路AT93C46 功能介绍AT93C46 是一片串行数据存储器芯片，其接脚说明如表1 及内部结构如图3。

不论写入或读取数据，皆采用串行传输的模式作动，虽然没有比并列传输来的快速，但是在传递远距离的数据，却可以大量减少使用传输线的需求，也缩小了系统整体的占有面积。

因此，非常适合用于微控制器或是微处理器，表2是对AT93C 系列作容量上的比较。

AT93C46 内部有一个指令缓存器储存传输进来的串行数据，再由指令译码控制逻辑与内部频率产生器，在指定的地址将数据作读取或写入的动作。

AT93C46 共有7 个功能指令，我们用表3来说明之;另外，也将其控制动作用表4说明，而AT93C46 特性说明概要如下：保存的资料约40 年之久。

● 可以重复写入超过1 百万次。

● 可以记录64 组16bit 的数字。

● 采用微金属丝接口(Microwire Interface)。

● 有4 条串行金属线总线。

● 1024bit 的串行数据存储器。

● 内部是采用CMOS EEPROM 的方式。

READ：允许数据从指定的地址读出，当接受到有效的输入讯号时，数据将会被放在输出缓存器内，随着频率讯号上升同步输出，在DO 输出数据前会先输出一个“ 假的位”，如同起始位的功能一样，再由D15 一直到D0 输出为止。

1 概述CSI93c46是一种存储器可以定义为16 位ORG 引脚接Vcc 或者定义为8 位ORG 引脚接GND 的1K/2K/2K/4K/16K 位的串行E2PROM 每一个的存储器都可以通过DI 引脚或DO 引脚进行写入或读出每一片CSI93c46/56/57/66/86 都是采用CSIalyst 公司先进的CMOS E2PROM 浮动门工艺加工器件可以经受1000000 次的写入/擦除操作片内数据保存寿命达到100 年器件可提供的封装有DIP-8 SOIC-8 TSSOP-82 器件特性高速度操作1MHz低功耗工艺电源电压宽1.8 伏到6.0 伏存储器可选择8 位或者16 位结构写入时自动清除存储器内容硬件和软件写保护1000000 次写入/擦除周期100 年数据保存寿命商业级工业级和汽车级温度范围连续读操作除93c46外写入允许引脚PE 只有93C86 有3 管脚配置及其方框图3 1 管脚3 2 管脚说明说明当ORG 接Vcc 时存储器为16 位结构当ORG 接GND 是存储器为8 位结构当ORG引脚悬空时内部的上拉电阻把存储器选择为16 位结构管脚名称功能CS 片选信号SK 时钟输入DI 串行数据输入DO 串行数据输出Vcc 电源+1.8 伏到6 伏GND 接地ORG 存储器结构选择NC 不用连接PE* 写入保护4 器件操作简介CSI93c46/56 57 /66/86 是一个有1024/2048/4096/16384 位内含工业标准微处理器的非易失的存储器CSI93c46/56/57/66/86 可以选择为16 位或8 位结构当选择16 位结构时93c46有7 条9 位的指令93C57 有7 条10 位的指令93C56 和93C66 有7 条11 位的指令93C86 有7 条13 位的指令用来控制对器件进行读写和擦除操作当选择8 位结构时93c46有7 条10 位的指令93C57 有7 条11 位的指令93C56 和93C66 有7 条12 位的指令93C86 有7 条14 位的指令来控制对器件进行读写和擦除操作CSI93c46/56/57/66/86 的所有操作都在单电源上进行当执行任何的写操作时内部的升压电路将提供高压给芯片指令地址和写入的数据在时钟信号SK 的上升沿时由DI 引脚输入DO 引脚除了从器件读取数据或在进行了写操作后查询准备/繁忙ready/busy 的器件工作状态外平常是高阻态的准备/繁忙ready/busy 是开始了一个写操作后选择器件CS 为高电平后从DO 引脚读得用来测定期间工作状态的信号DO 为低电平则表示写操作还没有完成当DO 为高电平时则表示器件可以输入下一条指令此时如果有需要可以在DI 引脚移入一个高电平DO 会进入高阻态DO 引脚会在时钟SK的下降沿时进入高阻态将DO 引脚恢复高阻态是值得推荐在DI 和DO 合用一个I/O 口来读/写的应用中所有送往器件的指令格式为一个高电平1 的开始位一个2 位或4 位的操作码6 位93c46/7 位93C57 /8 位(93C56 或93C66)/10 位(93C86)(当选择8 位结构时加一位)及写入数据时的16 位数据选择8 位结构时为8 位注当器件为93C86 时执行写入擦除写全部和擦全部操作时写允许引脚PE 必须为1 如果PE 引脚悬空93C86 为允许写入模式当执行写允许和写禁止指令后PE 可以不必理会93c46是1k位串行EEPROM储存器。

Rev.3.2_01应用手册 No.M103CMOS串行E2PROMS-2900A/29xxxA/93CxxA系列的使用方法目录1. 关于输入端子的连接 (2)2. 输入、输出端子等效电路 (2)2-1.输入端子 (2)2-2.输出端子 (3)3. 程序禁止指令 (4)4. 电源接通清除电路 (4)4-1.电源电压的上升方法 (4)4-2.初始化时间 (6)5. 关于往E2PROM传送16位写入数据的途中、CS下降时的写入工作 (7)6. 关于E2PROM的奇偶校验工作 (8)7. 关于输入端子噪声抑制时间 (9)8. 注意事项 (9)CMOS串行E2PROMS-2900A/29xxxA/93CxxA系列的使用方法Rev.3.2_01注意 不仅限于本公司的产品，由于E2PROM「在电源ON/OFF时工作于低电压领域内」以及「输入噪声信号而导致的指令的误识别」，具有引起误工作(误写入)的危险性。

特别是，负责传送指令给E2PROM的微机的电压，处于低于最低工作电压的电压范围内时，有可能发生这些故障。

在此所记载的内容是关于使用本E2PROM的重要内容，请务必认真阅读。

1.关于输入端子的连接S-2900A/29xxxA/93CxxA系列产品的输入端子全部为CMOS构造，所以在E2PROM工作时请设计为不能输入高阻抗。

特别是「电源ON/OFF时」和「工作待机时」，请设置CS输入为非选择状态。

数据的误写入在CS端子为非选择状态时(CS为Low、CS为High)不会发生。

因此，当CS极性为High 动态的情况下，推荐连接10 kΩ ~ 100 kΩ的下拉电阻。

为了更确实地防止误工作，虽然CS端子连接下拉／上拉电阻是最重要的，但也推荐除此以外的其他端子也连接同样的下拉／上拉电阻。

表1CS端子 High动态 Low动态CS端子的处理下拉电阻：10 kΩ ~ 100 kΩ上拉电阻：10 kΩ ~ 100 kΩ代表产品S-93C46A, S-29130A S-29194A2.输入、输出端子等效电路表示E2PROM输入端子的等效电路。

1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•User-selectable Internal Organization –1K: 128 x 8 or 64 x 16–2K: 256 x 8 or 128 x 16–4K: 512 x 8 or 256 x 16•3-wire Serial Interface • 2 MHz Clock Rate (5V)•Self-timed Write Cycle (10 ms max)•High Reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free Devices Available•8-lead PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP , 8-lead TSSOP and 8-ball dBGA2™ PackagesDescriptionThe AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-grammable read only memory (EEPROM), organized as 64/128/256 words of 16 bits each when the ORG pin is connected to VCC, and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and com-mercial applications where low-power and low-voltage operations are essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP , 8-lead TSSOP , and 8-ball dBGA2™ packages.20172X–SEEPR–7/04The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the DO pin. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” fol-lowing the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part.The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.Block DiagramNote:1.When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. The feature is not available on the 1.8V devices.2.For the A T93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends usingthe A T93C46A device. For more details, see the AT93C46A datasheet.Absolute Maximum Ratings*Operating Temperature ......................................−55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilityStorage T emperature .........................................−65°C to +150°C Voltage on Any Pinwith Respect to Ground ........................................−1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA30172X–SEEPR–7/04IL IH Pin Capacitance (1)DC CharacteristicsApplicable over recommended operating range from: T AI = −40°C to +85°C, V CC = +1.8V to +5.5V , T = -40°C to +125°C, V = +1.8V to +5.5V (unless otherwise noted).AC CharacteristicsApplicable over recommended operating range from T AI = −40°C to + 85°C, T AE = −40°C to +125°C, V CC = As Specified,40172X–SEEPR–7/0450172X–SEEPR–7/04Note:The X’s in the address field represent don’t care values and must be clocked.2.This device is not recommended for new designs. Please refer to AT93C66A.3.The X’s in the address field represent don’t care values and must be clocked.Instruction Set for the AT93C46Instruction Set for the AT93C56(1) and AT93C66(2)60172X–SEEPR–7/04Functional DescriptionThe AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro-cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory address location.READ (READ): The Read (READ) instruction contains the address code for the mem-ory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or V CC power is removed from the part.ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ).A logic “1” at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction.WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle t WP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle t WP .ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-ory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). The ERAL instruction is valid only at V CC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ).The WRAL instruction is valid only at V CC = 5.0V ± 10%.ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.70172X–SEEPR–7/04Timing DiagramsSynchronous Data TimingNote: 1.This is the minimum SK period.2.This device is not recommended for new designs. Please refer to AT93C66A.3.A 8 is a DON’T CARE value, but the extra clock is required.4.A 7 is a DON’T CARE value, but the extra clock is required.READ TimingOrganization Key for Timing DiagramsEWDS TimingWRITE Timing80172X–SEEPR–7/0490172X–SEEPR–7/04Note:1.Valid only at V CC = 4.5V to 5.5V .ERASE TimingNote: 1.Valid only at V CC = 4.5V to 5.5V.100172X–SEEPR–7/04110172X–SEEPR–7/04AT93C46 Ordering InformationNote: 1.This device is not recommended for new designs. Please refer to AT93C56A.2.For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.120172X–SEEPR–7/04130172X–SEEPR–7/04Notes:1.This device is not recommended for new designs. Please refer to AT93C66A.2.For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.Packaging Information8P3 – PDIP140172X–SEEPR–7/04150172X–SEEPR–7/04160172X–SEEPR–7/04170172X–SEEPR–7/048A2 – TSSOP8U3-1 – dBGA2180172X–SEEPR–7/04190172X–SEEPR–7/048Y1 – MAP0172X–SEEPR–7/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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“93c46读写程序”#include <reg52.h>sbit CS=P2^7;sbit SK=P2^6;sbit DI=P2^5;sbit DO=P2^4;/*extern unsigned char ReadChar(unsigned char address);extern void WriteChar(unsigned char address,unsigned char InData);extern void ReadString(unsigned char data *RamAddress,unsigned char RomAddress, unsigned char Number);extern void WriteString(unsigned char data *RamAddress,unsigned char RomAddress, unsigned char Number);*/// Write enable must precede all programming modes.void Ewen(void) {unsigned char temp,InData;CS=0;SK=0;CS=1;InData=0x98; // 10011XXXXfor(temp=9;temp!=0;temp--) { // 9DI=InData&0x80;SK=1; SK=0;InData<<=1;}CS=0;}// Disables all programming instructions.void Ewds(void) {unsigned char temp,InData;CS=0;SK=0;CS=1;InData=0x80; // 10000XXXXfor(temp=9;temp!=0;temp--) { // 9DI=InData&0x80;SK=1; SK=0;InData<<=1;}CS=0;}// Reads data stored in memory, at specified address.unsigned int Read(unsigned char address) {unsigned char temp;unsigned int result;Ewen();SK=0; DI=1; // 110 A5-A0CS=0; CS=1;SK=1; SK=0; // 1address=address&0x3f|0x80;for(temp=8;temp!=0;temp--) { // 8DI=address&0x80;SK=1; SK=0;address<<=1;}DO=1;for(temp=16;temp!=0;temp--) { // 16SK=1;result=(result<<1)|DO;SK=0;}CS=0;Ewds();return(result);}// Writes memory location An - A0.void Write(unsigned char address,unsigned int InData) {unsigned char temp;Ewen();SK=0; DI=1; // 101 A5-A0CS=0; CS=1;SK=1; SK=0; // 1address=address&0x3f|0x40;for(temp=8;temp!=0;temp--) { // 8DI=address&0x80;SK=1; SK=0;address<<=1;}for(temp=16;temp!=0;temp--) { // 16DI=InData&0x8000;SK=1; SK=0;InData<<=1;}CS=0; DO=1;CS=1; SK=1;while(DO==0) { // busy testSK=0; SK=1;}SK=0; CS=0;Ewds();}/*// Erase memory location An - A0.void Erase(unsigned char address) {unsigned char temp;Ewen();SK=0; DI=1; // 111 A5-A0CS=0; CS=1;SK=1; SK=0; // 1address|=0xc0;for(temp=8;temp!=0;temp--) { // 8DI=address&0x80;SK=1; SK=0;address<<=1;}CS=0; DO=1;CS=1; SK=1;while(DO==0) {SK=0; SK=1;}SK=0; CS=0;Ewds();}// Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. void Eral(void) {unsigned char temp,InData;Ewen();CS=0;SK=0;CS=1;InData=0x90; // 10010XXXXfor(temp=9;temp!=0;temp--) { // 9DI=InData&0x80;SK=1; SK=0;InData<<=1;}CS=0; DO=1;CS=1; SK=1;while(DO==0) {SK=0; SK=1;}SK=0; CS=0;Ewds();}// Writes all memory locations. Valid only at VCC = 4.5V to 5.5V. void Wral(unsigned int InData) {unsigned char temp,address;Ewen();CS=0;SK=0;CS=1;address=0x88; // 10001XXXXfor(temp=9;temp!=0;temp--) { // 9DI=address&0x80;SK=1; SK=0;address<<=1;}for(temp=16;temp!=0;temp--) { // 16DI=InData&0x8000;SK=1; SK=0;InData<<=1;}CS=0; DO=1;CS=1; SK=1;while(DO==0) {SK=0; SK=1;}SK=0; CS=0;Ewds();}*/unsigned char ReadChar(unsigned char address) {unsigned char temp=address>>1;if(address&0x01) return((unsigned char)(Read(temp)>>8));else return((unsigned char)(Read(temp)));}void WriteChar(unsigned char address,unsigned char InData) {unsigned char temp=address>>1;if(address&0x01) Write(temp,(unsigned int)(Read(temp)&0x00ff|(InData<<8)));else Write(temp,(unsigned int)(Read(temp)&0xff00|InData));}void ReadString(unsigned char data *RamAddress,unsigned char RomAddress,unsigned char Number) {while(Number!=0) {*RamAddress=ReadChar(RomAddress);RamAddress++;RomAddress++;Number--;}}void WriteString(unsigned char data *RamAddress,unsigned char RomAddress,unsigned char Number) {unsigned int temp;if(Number==0) return;if(RomAddress&0x01) {WriteChar(RomAddress,*RamAddress);RamAddress++;RomAddress++;Number--;}if(Number==0) return;while(Number>>1) {temp=*RamAddress;RamAddress++;temp=temp|(*RamAddress)<<8;RamAddress++;Write(RomAddress>>1,temp);RomAddress++;RomAddress++;Number--;Number--;}if(Number) WriteChar(RomAddress,*RamAddress);。

1024-BITS SERIAL ELECTRICALLY ERASABLE PROMFeaturesState-of-the-art architecture-Non-volatile data storage-Operating voltage Vcc : 2.7-5.5V-Full TTL compatible inputs and outputs -Auto increment read efficient data dump Hardware and software write protection-Defaults to write-disabled state at power up -Software instructions for write-enable/disable -Vcc level verification before self-timed programming cycleAdvanced low voltage CMOS EEPROM technologyGeneral DescriptionThe AV93LC46 is a 1024-bit, non-volatile, serial EEPROM. It is manufactured by using advanced CMOS EEPROM technology. The AV93C46 provides efficient non-volatile read/write memory arranged as 64registers of 16 bits each. Seven 9-bit instructions control the operation of the device, which includes read,write and write enable/disable functions. The data out pin (DO) indicates the status of the device during the self-timed non-volatile programming cycle.The self-timed write cycle includes an automatic erase-before write capability. Only when the chip is in the WRITE ENABLE state and proper Vcc operation range is the WRITE instruction accepted and thus to protect Against inadvertent writes, Data is written in 16 bits per write instruction into the selected register. If chip select (CS) is brought HIGH after initiation of the write cycle, the data output (DO) pin will indicate the READY/BUSY status of the chip.The AV93C46 is available in space-saving 8-lead PDIP, 8-lead SOP and rotated 8-lead SOP package.CONNECTION DIAGRAMPIN ASSIGNMENTCSChip Select SK Serial Data Clock DI Serial Data Input DO Serial Data OutputGND Ground VCC Power Supply NCNo ConnectionORDERING INFORMATIONAV93LC46 XXAV ----------AVIC Electronics CO.,LTDLC ----------Operating Voltage : 2.7~5.5V, CMOS46 ----------Type : 1KXX --------- SC/PC/SI/PI/TC/TI(S----SOP8; P----DIP8; T----TSSOP; C----0℃~+70℃; I---- -45℃~+80℃)Block DiagramAbsolute Maximum RatingsStorage Temperature…………………. –65℃ to +125℃Voltage with Respect to Ground………-0.3 to +6.5 VNOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. Operating ConditionsTemperature under bias AV93LC46……………0℃ to +70℃DC Electrical Characteristics (Vcc=2.7V-5.5V,Ta=25℃, unless otherwise noted)symbolParameterconditionsMinMaxUnitsIcc1 Operating Current (Program)SCL=10KHz CMOS Input Leavels - 3 mAIcc2 Operating Current (Read)SCL=10KHz CMOS Input Leavels - 200 uAI SB1 Stabdby Current SCL =SDA =0V,Vcc =5V - 10 uA I SB2 Stabdby Current SCL =SDA =0V,Vcc =3V - 1 uA I IL Input Leakage V IN =0V to Vcc -1 +1 uA I OL Output Leakage Vout=0V to Vcc -1 +1 uA V IL Input Low Voltage**-0.1 Vcc X 0.3 VV IH Input High Voltage** Vcc X 0.7Vcc+0.2 VV OL1 Output Low Voltage I OL =2.1mA TTL - 0.4 V V OL2 Output Low Voltage I OL =10uA CMOS - 0.2 V V LK Vcc Lockout Voltage Programming Command Can Be ExecutedDefault - VNote. ** V IL min and V IH max are reference only and are not testedAC Electrical Characteristics (Vcc=2.7V – 5.5V, Ta=25℃ unless otherwise noted ) Symbol Parameter Conditions Min Max Units F SK SK Clock Frequency 0 1 MHzT SKH SK High Time 250 ns T SKL SK Low Time 250 ns T CS Minimum CS Low Time 250 nsT CSS CS Setup Time Relative to SK 50 ns T DIS DI Setup Time Relative to SK 100 ns T CSH CS Hold Time Relative to SK 0 ns T DIH DI Hold Time Relative to SK 100 ns T PD1 Output Delay to “1” AC Test 500 ns T PD0 Output Delay to “0” AC Test 500 ns T SVCS to Status Valid AC Test CL=100pF500 nsT DF CS to DO in 3-state CS=VIL 100 ns T WP Write Cycle Time 10 ms Endurance** 5V,25℃,Page Mode1M Write cycles Note. ** The Parameter is characterized and isn’t 100% tested.Instruction SetInstruction Start Bit OP Code Address Input Data10A5-A0READ 1WEN(Write Enable) 1 00 11XXXXD15-D0*A5-A0WRITE 101WRALL (Write all Registers) 1 00 01XXXX D15-D0* WDS (Write Disable) 1 00 00XXXXA5-A011ERASE 1ERAL (Erase All Registers) 1 00 10XXXX* If input Data is not 16 bits exactly, the last 16 bits will be taken as input data ( a word )Pin Capacitance ** (Ta=25℃, f=1MHz)Symbol Parameter Max UnitsCapacitance 5 pF Cout OutputCapacitance 5 pFC IN InputFunctional DescriptionsApplicationsThe AV93LC46 is ideal for high volume applications requiring low power and low density storage. This device uses a low cost, space saving 8-pin package. Typical applications include robotics, alarm devices, electronic locks, meters and instrumentation settings such as LAN cards, monitors and MODEM. Endurance and Data RetentionThe AV93LC46 is designed for applications requiring up to 1000K programming cycles (WRITE, WRALL, EARSE and ERAll). It provides 40 years of secure data retention without power after the execution of 1000K programming cycles.Device OperationThe AV93LC46 is controlled by seven 9-bit instructions. Instructions are clocked in (serially) on the DI pin.Each instruction begins with a logical “1” (the start bit). This is followed by the opcode (2 bits), the address field (6 bits), and data, if appropriate. The clock signal (SK) may be halted at any time and theAV93LC46 will remain in its last state. This allows full static flexibility and maximum power conservation.Read (READ)The READ instruction is the only instruction that outputs serial data on the DO pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a 16-bit serial shift register. (Please note that one logical “0” bit precedes the actual 16-bit output data string.) the output on DO changes during the rising edge transitions of SK. (Shown in Figure 3 )Auto Increment Read OperationsSequential read is possible, since the AV93LC46 has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 16 bits of the addressed word have been clocked out, the data in consecutively higher address locations (the address “0000” is assumed as the higher address of “111111”) is output. The address will wrap around continuously with CS high until the chip select (CS) control pin is brought low. This allows for single instruction data dumps to executed with a minimum of firmware overhead.Write Enable (WEN)Before any device programming (WRITE, WRAll, ERASE, and ERAl) can be done, the WRITE ENABLE (WEN) instruction must be executed first. When Vcc is applied, this device powers up in the WRITE DISABLE state. The device then remains in a WRITE DISABle state until a WEN instruction is executed. Thereafter the device remains enabled until a WDS instruction is executed or until Vcc is removed. (NOTE: Neither the Wen nor the WDS instruction has any effect on the READ instruction.) (Shown in Figure 4.)Write Disable (WDS)The WRITE DISABLE (WDS) instruction disables all programming capabilities. This protects the entire part against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the WRITE DISABLE state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. (NOTE: Neither the WEN nor the WDS instruction has any effect on the READ instruction.) (Shown in Figure 5.)Functional Description (Continued)Write (WRITE)The WRITE instruction includes 16 bits of data to be written into the specified register . After the last bit has been applied to DI, and before the next rising edge of SK, CS must be brought LOW. The falling edge of CS initiates the selftimed programming cycle.After a minimum wait of 250ns (5V operation) from the falling edge of CS (tcs), DO will indicate the READY/BUSY status of the chip if CS is brought HIGH. This means that logical “0” implies the programming is still in progress while logical “1” indicates the selected register has been written, and the part is ready for another instruction.(See Figure 6.)Note: The combination of CS HIGH, DI HIGH and the rising edge of the SK clock, resets theREADY/BUSY flag. Therefore, it is important if you want to access the READY/BUSY flag,not to reset it through this combination of control signals.Before a WRITE instruction can be executed, the device must be in the WRITE ENABLE (WEN) state. Write All (WRALL)The write All (WRALL) instruction programs all registers with the data pattern specified in the instruction. While the WRALL instruction is being loaded, the address field becomes a sequence of DON’T-CARE bits. (Shown in Figure 7.)As with the WRITE instruction, if CS is brought HIGH after a minimum wait of of 250ns (tcs), the DO pin indicates the READY/BUSY status of the chip. (Shown Figure 7.)ERASE (ERASE)After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after minimum of tcs, will cause DO to indicate the READY/BUSY status of the chip. To explain this, a logical “0” indicates the programming is still in progress while a logical “1” indicates the erase cycle is complete and the part is ready for another instruction. (Shown in Figure 8.)Erase All (ERALL)Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all the entire memory array a logical “1”. (Shown in Figure 9.)Security ConsiderationTo protect the entire part against accidental modification of data, each programming instruction (WRITE, WRALL, ERASE, and ERALL) must satisfy two conditions before user initiate self-timed programming cycle (the falling edge of CS). One is that the AV93LC46 is at WEN status. The other is that Vcc value must exceed a lock-out value which can be adjusted by AVIC.Timing Diagram (1)Organization KeyI/OAV93LC46 (1K) AV93LC56 (2K)X 8 X 16 X 8 X 16A N A6A5A8(1)A7(2)D N D7D15D7D15 Note : (1). A8 is a DON’T CARE value, but the extra clock is required.(2). A7 is a DON’T CARE value, but the extra clock is required.Timing Diagram (2)Timing Diagram (3)。

AT93C46中文资料详解AT93C46 是1K的串行EEPROM存储器器件，它们可配置为16位(ORG 管脚接Vcc)或者8位(ORG管脚接GND)的寄存器。

每个寄存器都可通过DI(或DO管脚)串行写入(或读出)。

AT93C46 部有一个指令缓存器储存传输进来的串行数据，再由指令译码控制逻辑与部频率产生器，在指定的地址将数据作读取或写入的动作。

AT93C46采用Catalyst公司先进的CMOS EEPROM浮动闸(floating gate)技术制造而成。

器件可采用8脚DIP，8脚SOIC或8脚TSSOP的封装形式。

AT93C46 集成电路AT93C46 功能介绍AT93C46 是一片串行数据存储器芯片，其接脚说明如表1 及部结构如图3。

不论写入或读取数据，皆采用串行传输的模式作动，虽然没有比并列传输来的快速，但是在传递远距离的数据，却可以大量减少使用传输线的需求，也缩小了系统整体的占有面积。

因此，非常适合用于微控制器或是微处理器，表2是对AT93C 系列作容量上的比较。

AT93C46 部有一个指令缓存器储存传输进来的串行数据，再由指令译码控制逻辑与部频率产生器，在指定的地址将数据作读取或写入的动作。

AT93C46 共有7 个功能指令，我们用表3来说明之;另外，也将其控制动作用表4说明，而AT93C46 特性说明概要如下：保存的资料约40 年之久。

● 可以重复写入超过1 百万次。

● 可以记录64 组16bit 的数字。

● 采用微金属丝接口(Microwire Interface)。

● 有4 条串行金属线总线。

● 1024bit 的串行数据存储器。

● 部是采用CMOS EEPROM 的方式。

READ：允许数据从指定的地址读出，当接受到有效的输入讯号时，数据将会被放在输出缓存器，随着频率讯号上升同步输出，在DO 输出数据前会先输出一个“ 假的位”，如同起始位的功能一样，再由D15 一直到D0 输出为止。

CAT93C461 kb Microwire Serial EEPROMDescriptionThe CAT93C46 is a 1 kb Serial EEPROM memory device which is configured as either 64 registers of 16 bits (ORG pin at V CC ) or 128registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46 features a self −timed internal write with auto −clear. On −chip Power −On Reset circuit protects the internal logic against powering up in the wrong state.Features•High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)•1.8 V (1.65 V*) to 5.5 V Supply V oltage Range •Selectable x8 or x16 Memory Organization •Self −Timed Write Cycle with Auto −Clear •Sequential Read (New Product)•Software Write Protection•Power −up Inadvertant Write Protection •Low Power CMOS Technology •1,000,000 Program/Erase Cycles •100 Year Data Retention•Industrial and Extended Temperature Ranges•8−pin PDIP , SOIC, TSSOP and 8−pad UDFN and TDFN Packages •This Device is Pb −Free, Halogen Free/BFR Free and RoHS Compliant †Figure 1. Functional SymbolDOV ORG CS SK DI*CAT93C46xx −xxL (T A = −20°C to +85°C)†For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.ORDERING INFORMATIONPIN CONFIGURATIONSGNDNC V CC DODI SK CS1ORG PDIP (L), SOIC (V, X),TSSOP (Y), UDFN (HU4),TDFN (VP2)**(Top View)Chip Select CS Clock Input SK Serial Data Input DI Serial Data Output DOPower Supply V CC GroundGND FunctionPin NamePIN FUNCTIONMemory Organization ORGNo ConnectionNCNote: When the ORG pin is connected to V CC , the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.SOIC −8V, W** SUFFIX CASE 751BDPDIP −8L SUFFIX CASE 646AA TDFN −8**VP2 SUFFIX CASE 511AKTSSOP −8Y SUFFIX CASE 948AL SOIC −8X SUFFIX CASE 751BE DIGND ORGSK CSV CC NC 1DO SOIC (W)**(Top View)UDFN −8HU4 SUFFIX CASE 517AZ ** Not recommended for new designs.Table 1. ABSOLUTE MAXIMUM RATINGSParameter Value UnitsStorage Temperature−65 to +150°CVoltage on Any Pin with Respect to Ground (Note 1)−0.5 to +6.5VStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.The DC input voltage on any pin should not be lower than −0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin mayundershoot to no less than −1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.Table 2. RELIABILITY CHARACTERISTICS (Note 2)Symbol Parameter Min Units N END (Note 3)Endurance1,000,000Program / Erase Cycles T DR Data Retention100Years2.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.3.Block Mode, V CC = 5 V, 25°CTable 3. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT (Not Recommended for New Designs)(V CC = +1.8 V to +5.5 V, T A = −40°C to +85°C, unless otherwise specified.)Symbol Parameter Test Conditions Min Max Units1mAI CC1Power Supply Current (Write)f SK = 1 MHzV CC = 5.0 VI CC2Power Supply Current (Read)f SK = 1 MHz500m AV CC = 5.0 V2m AI SB1Power Supply Current (Standby) (x8 Mode)V IN = GND or V CC,CS = GNDORG = GNDI SB2Power Supply Current (Standby) (x16Mode)V IN = GND or V CC,1m ACS = GNDORG = Float or V CCI LI Input Leakage Current V IN = GND to V CC1m AI LO Output Leakage Current V OUT = GND to V CC,1m ACS = GNDV IL1Input Low Voltage 4.5 V v V CC < 5.5 V−0.10.8V V IH1Input High Voltage 4.5 V v V CC < 5.5 V2V CC + 1V V IL2Input Low Voltage 1.8 V v V CC < 4.5 V0V CC x 0.2V V IH2Input High Voltage 1.8 V v V CC < 4.5 V V CC x 0.7V CC + 1V V OL1Output Low Voltage 4.5 V v V CC < 5.5 V0.4VI OL = 2.1 mA2.4VV OH1Output High Voltage 4.5 V v V CC < 5.5 VI OH = −400 m AV OL2Output Low Voltage 1.8 V v V CC < 4.5 V0.2VI OL = 1 mAV OH2Output High Voltage 1.8 V v V CC < 4.5 VV CC− 0.2VI OH = −100 m ASymbol Parameter Test Conditions Min Max Units I CC1Supply Current (Write)Write, V CC = 5.0 V1mA I CC2Supply Current (Read)Read, DO open, f SK = 2 MHz, V CC = 5.0 V500m AI SB1Standby Current(x8 Mode)V IN = GND or V CCCS = GND, ORG = GNDT A = −40°C to +85°C2m AT A = −40°C to +125°C5I SB2Standby Current(x16 Mode)V IN = GND or V CCCS = GND,ORG = Float or V CCT A = −40°C to +85°C1m AT A = −40°C to +125°C3I LI Input Leakage Current V IN = GND to V CC T A = −40°C to +85°C1m AT A = −40°C to +125°C2I LO Output LeakageCurrent V OUT = GND to V CCCS = GNDT A = −40°C to +85°C1m AT A = −40°C to +125°C2V IL1Input Low Voltage 4.5 V ≤ V CC < 5.5 V−0.10.8V V IH1Input High Voltage 4.5 V ≤ V CC < 5.5 V2V CC + 1V V IL2Input Low Voltage 1.8 V ≤ V CC < 4.5 V0V CC x 0.2V V IH2Input High Voltage 1.8 V ≤ V CC < 4.5 V V CC x 0.7V CC + 1V V OL1Output Low Voltage 4.5 V ≤ V CC < 5.5 V, I OL = 3 mA0.4V V OH1Output High Voltage 4.5 V ≤ V CC < 5.5 V, I OH = −400 m A 2.4V V OL2Output Low Voltage 1.8 V ≤ V CC < 4.5 V, I OL = 1 mA0.2V V OH2Output High Voltage 1.8 V ≤ V CC < 4.5 V, I OH = −100 m A V CC− 0.2VTable 5. PIN CAPACITANCE (T A = 25°C, f = 1 MHz, V CC = 5 V)Symbol Test Conditions Min Typ Max UnitsC OUT (Note 4)Output Capacitance (DO)V OUT = 0 V5pFC IN (Note 4)Input Capacitance (CS, SK, DI, ORG)V IN = 0 V5pF4.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT (Not Recommended for New Designs)(V CC = +1.8 V to +5.5 V, T A = −40°C to +85°C, unless otherwise specified.)(Note 5)Symbol Parameter Min Limit Max Limit Units t CSS CS Setup Time50ns t CSH CS Hold Time0ns t DIS DI Setup Time100ns t DIH DI Hold Time100ns t PD1Output Delay to 10.25m s t PD0Output Delay to 00.25m s t HZ (Note 6)Output Delay to High−Z100ns t EW Program/Erase Pulse Width5ms t CSMIN Minimum CS Low Time0.25m s t SKHI Minimum SK High Time0.25m s t SKLOW Minimum SK Low Time0.25m s t SV Output Delay to Status Valid0.25m s SK MAX Maximum Clock Frequency DC2000kHz5.Test conditions according to “AC Test Conditions” table.6.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.Symbol Parameter V CC = 1.8 V − 5.5 V V CC = 4.5 V − 5.5 VUnits Min Max Min Maxt CSS CS Setup Time5050ns t CSH CS Hold Time00ns t DIS DI Setup Time10050ns t DIH DI Hold Time10050ns t PD1Output Delay to 10.250.1m s t PD0Output Delay to 00.250.1m s t HZ (Note 7)Output Delay to High−Z100100ns t EW Program/Erase Pulse Width55ms t CSMIN Minimum CS Low Time0.250.1m s t SKHI Minimum SK High Time0.250.1m s t SKLOW Minimum SK Low Time0.250.1m s t SV Output Delay to Status Valid0.250.1m s SK MAX Maximum Clock Frequency DC2000DC4000kHz 7.This parameter is tested initially and after a design or process change that affects the parameter.Table 8. POWER−UP TIMING(Notes 8 and 9)Symbol Parameter Max Units t PUR Power−up to Read Operation1ms t PUW Power−up to Write Operation1ms 8.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.9.t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.Table 9. A.C. TEST CONDITIONSInput Rise and Fall Times v 50 nsInput Pulse Voltages0.4 V to 2.4 V 4.5 V v V CC v 5.5 V Timing Reference Voltages0.8 V, 2.0 V 4.5 V v V CC v 5.5 V Input Pulse Voltages0.2 V CC to 0.7 V CC 1.8 V v V CC v 4.5 V Timing Reference Voltages0.5 V CC 1.8 V v V CC v 4.5 V Output Load Current Source I OLmax/I OHmax; C L = 100 pFDevice OperationThe CAT93C46 is a 1024−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10−bit instructions control the reading, writing and erase operations of the device. The CAT93C46 operates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 2.The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state.The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organization).ReadUpon receiving a READ command (Figure 3) and an address (clocked into the DI pin), the DO pin of the CAT93C46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (t PD0 or t PD1).After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is proceeded by a dummy zero bit. All sunsequent data words will follow without a dummy zero bit. Note: The sequential READ mode is available for CAT93C46 New Product only.Erase/Write Enable and DisableThe CA T93C46 powers up in the write disable state. Any writing after power−up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4.Table 10. INSTRUCTION SETInstruction Start Bit OpcodeAddress DataComments x8x16x8x16READ110A6−A0A5−A0Read Address AN–A0 ERASE111A6−A0A5−A0Clear Address AN–A0 WRITE101A6−A0A5−A0D7−D0D15−D0Write Address AN–A0 EWEN10011XXXXX11XXXX Write EnableEWDS10000XXXXX00XXXX Write DisableERAL*10010XXXXX10XXXX Clear All Addresses WRAL*10001XXXXX01XXXX D7−D0D15−D0Write All Addresses * Not available at V CC < 1.8 VFigure 2. Synchronous Data TimingSKDICSDOFigure 3. Read Instruction TimingSKCSDIDOor D 7 . . .orD 7 . . . D 0orD 7 . . . D 0D 7 . . . D 0Figure 4. EWEN/EWDS Instruction TimingCSDI STANDBY** ENABLE = 11 DISABLE = 00SK01WriteAfter receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of t CSMIN . The falling edge of CS will start the self clocking for auto −clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CA T93C46can be determined by selecting the device and polling the DO pin. Since this device features Auto −Clear before write,it is NOT necessary to erase a memory location before it is written into.EraseUpon receiving an ERASE command and address, the CS (Chip Select) pin must be de −asserted for a minimum of t CSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state.Erase AllUpon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of t CSMIN . The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state.Write AllUpon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of t CSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device.The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.Figure 5. Write Instruction TimingSKCSDIDOFigure 6. Erase Instruction TimingSKCSDIDOFigure 7. ERAL Instruction TimingSKCS DI DOFigure 8. WRAL Instruction TimingSKCS DI DOCASE 646AA −01cTOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters.(2) Complies with JEDEC MS-001.SYMBOLMINNOMMAX A A1A2bb2c D e E1L0.382.920.366.101.140.209.022.54 BSC3.305.334.950.567.111.780.3610.16eB7.8710.92E 7.628.252.923.803.300.466.351.520.259.277.87CASE 751BD −01ISSUE OIDENTIFICATIONTOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MS-012.SYMBOLMIN NOMMAX θA A1b cD E E1e h 0º8º0.100.330.190.254.805.803.801.27 BSC1.750.250.510.250.505.006.204.00L0.40 1.271.35分销商库存信息:ONSEMICAT93C46WI-GT3CAT93C46VI-GT3CAT93C46VI-G CAT93C46YI-G CAT93C46LI-G CAT93C46WI-G CAT93C46YI-GT3CAT93C46VP2I-GT3CAT93C46XI-T2 CAT93C46XI。

1/31August 2004M93C86, M93C76, M93C66M93C56, M93C4616Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)MICROWIRE® Serial Access EEPROMFEATURES SUMMARYs Industry Standard MICROWIRE Bus sSingle Supply Voltage:– 4.5 to 5.5V for M93Cx6– 2.5 to 5.5V for M93Cx6-W – 1.8 to 5.5V for M93Cx6-Rs Dual Organization: by Word (x16) or Byte (x8) s Programming Instructions that work on: Byte, Word or Entire Memorys Self-timed Programming Cycle with Auto-Erases sSpeed:–1MHz Clock Rate, 10ms Write Time(Current product, identified by process identification letter F or M)–2MHz Clock Rate, 5ms Write Time (NewProduct, identified by process identification letter W or G or S) s Sequential Read Operations Enhanced ESD/Latch-Up Behaviour s More than 1 Million Erase/Write Cycles sMore than 40 Year Data RetentionTable 1. Product ListReferencePart Number ReferencePart Number M93C86M93C86M93C56M93C56M93C86-W M93C56-W M93C86-R M93C56-R M93C76M93C76M93C46M93C46M93C76-W M93C46-W M93C76-R M93C46-RM93C66M93C66M93C66-W M93C66-RM93C86, M93C76, M93C66, M93C56, M93C46TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 3.Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 4.Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 3.DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 POWER-ON DATA PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..5INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 5.Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 6.Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 7.Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Erase/Write Enable and Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4.READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 5.ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Erase All. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 6.WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 7.Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 8.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9.Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 10.Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 11.Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 12.AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 13.AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . .14 Figure 8.AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142/31M93C86, M93C76, M93C66, M93C56, M93C46Table 14.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 15.DC Characteristics (M93Cx6, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 16.DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 17.DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 18.DC Characteristics (M93Cx6-W, Device Grade 7 or 3). . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 19.DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 20.AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 21.AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 22.AC Characteristics (M93Cx6-W, Device Grade 7 or 3). . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 23.AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 9.Synchronous Timing (Start and Op-Code Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .23 Table 24.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .23 Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .24 Table 25.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 24Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline 25Table 26.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.25Figure 15.TSSOP8 3x3mm²– 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline 26Table 27.TSSOP8 3x3mm²– 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data 26Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .27 Table 28.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .27PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 29.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 30.How to Identify Current and New Products by the Process Identification Letter. . . . . . .29REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 31.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303/31M93C86, M93C76, M93C66, M93C56, M93C464/31SUMMARY DESCRIPTIONThese electrically erasable programmable memo-ry (EEPROM) devices are accessed through a Se-rial Data Input (D) and Serial Data Output (Q)using the MICROWIRE bus protocol.Table 2. Signal NamesThe memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on Organization Se-lect (ORG). The bit, byte and word sizes of the memories are as shown in Table 3..Table 3. Memory Size versus OrganizationThe M93Cx6 is accessed by a set of instructions,as summarized in Table 4., and in more detail in Table 5. to Table 7.).Table 4. Instruction Set for the M93Cx6A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The ad-dress register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached).Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cy-cle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driv-en High.S Chip Select Input D Serial Data Input Q Serial Data Output C Serial Clock ORG Organisation Select V CC Supply Voltage V SSGroundDevice Number of Bits Number of 8-bit Bytes Number of 16-bit Words M93C861638420481024M93C7681921024512M93C664096512256M93C562048256128M93C46102412864Instruction Description Data READ Read Data from Memory Byte or Word WRITEWrite Data to Memory Byte or WordEWEN Erase/Write Enable EWDS Erase/Write Disable ERASE Erase Byte or Word Byte or WordERAL Erase All Memory WRALWrite All Memory with same DataM93C86, M93C76, M93C66, M93C56, M93C46An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low.Figure 3. DIP, SO, TSSOP and MLPNote: 1.See PACKAGE MECHANICAL section for package di-mensions, and how to identify pin-1.2.DU = Don’t Use.The DU (Don’t Use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be con-nected to V CC or V SS. Direct connection of DU to V SS is recommended for the lowest stand-by pow-er consumption.MEMORY ORGANIZATIONThe M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to V CC) the x16 organization is selected; when Organiza-tion Select (ORG) is connected to Ground (V SS) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to V SS or V CC for minimum power consumption. Any voltage between V SS and V CC applied to Organization Select (ORG) may increase the stand-by current.POWER-ON DATA PROTECTIONTo prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming cir-cuitry, and sets the device in the Write Disable mode.–At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supplyvoltage reaches the operating value V CCspecified in Table 9. to Table 11..–When V CC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incominginstructions.For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6-W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V.5/31M93C86, M93C76, M93C66, M93C56, M93C466/31INSTRUCTIONSThe instruction set of the M93Cx6 devices con-tains seven instructions, as summarized in Table 5. to Table 7.. Each instruction consists of the fol-lowing parts, as shown in Figure 4.:s Each instruction is preceded by a rising edgeon Chip Select Input (S) with Serial Clock (C) being held Low.s A start bit, which is the first ‘1’ read on SerialData Input (D) during the rising edge of Serial Clock (C).s Two op-code bits, read on Serial Data Input(D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).sThe address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 7.).The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0Hz (static input signals) or as fast as the max-imum ratings specified in Table 20. to Table 23..Table 5. Instruction Set for the M93C46Note: 1.X = Don ’t Care bit.Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address 1DataRequiredClock CyclesAddress 1DataRequired Clock CyclesREAD Read Data from Memory 110A6-A0Q7-Q0A5-A0Q15-Q0WRITE Write Data to Memory101A6-A0D7-D018A5-A0D15-D025EWEN Erase/Write Enable 10011X XXXX 1011 XXXX 9EWDS Erase/Write Disable 10000X XXXX 1000 XXXX 9ERASE Erase Byte or Word 111A6-A010A5-A09ERAL Erase All Memory 10010X XXXX 1010 XXXX 9WRALWrite All Memory with same Data10001X XXXXD7-D01801 XXXXD15-D0257/31M93C86, M93C76, M93C66, M93C56, M93C46Table 6. Instruction Set for the M93C56 and M93C66Note: 1.X = Don ’t Care bit.2.Address bit A8 is not decoded by the M93C56.3.Address bit A7 is not decoded by the M93C56.Table 7. Instruction Set for the M93C76 and M93C86Note: 1.X = Don ’t Care bit.2.Address bit A10 is not decoded by the M93C76.3.Address bit A9 is not decoded by the M93C76.Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address 1,2DataRequiredClock CyclesAddress 1,3DataRequired Clock CyclesREAD Read Data from Memory 110A8-A0Q7-Q0A7-A0Q15-Q0WRITE Write Data to Memory101A8-A0D7-D020A7-A0D15-D027EWEN Erase/Write Enable 100 1 1XXXXXXX 1211XX XXXX 11EWDS Erase/Write Disable 1000 0XXX XXXX 1200XX XXXX 11ERASE Erase Byte or Word 111A8-A012A7-A011ERAL Erase All Memory 100 1 0XXX XXXX 1210XX XXXX 11WRALWrite All Memory with same Data1000 1XXX XXXXD7-D02001XX XXXXD15-D027Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address1,2DataRequiredClock CyclesAddress 1,3DataRequiredClock CyclesREAD Read Data from Memory 110A10-A0Q7-Q0A9-A0Q15-Q0WRITE Write Data to Memory101A10-A0D7-D022A9-A0D15-D029EWEN Erase/Write Enable 10011X XXXX XXXX 1411 XXXX XXXX 13EWDS Erase/Write Disable 10000X XXXX XXXX 1400 XXXX XXXX 13ERASE Erase Byte or Word 111A10-A014A9-A013ERAL Erase All Memory 10010X XXXX XXXX 1410 XXXX XXXX 13WRALWrite All Memory with same Data10001X XXXX XXXXD7-D02201 XXXX XXXXD15-D029M93C86, M93C76, M93C66, M93C56, M93C468/31ReadThe Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically incre-ments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a con-tinuous stream of data can be read.Erase/Write Enable and DisableThe Erase/Write Enable (EWEN) instruction en-ables the future execution of erase or write instruc-tions, and the Erase/Write Disable (EWDS)instruction disables it. When power is first applied,the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Erase/Write En-able (EWEN) instruction has been executed, eras-ing and writing remains enabled until an Erase/Write Disable (EWDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from ac-cidental corruption, it is advisable to issue the Erase/Write Disable (EWDS) instruction after ev-ery write cycle. The Read Data from Memory (READ) instruction is not affected by the Erase/Write Enable (EWEN) or Erase/Write Disable (EWDS) instructions.M93C86, M93C76, M93C66, M93C56, M93C46EraseThe Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the Ready/READY/BUSY STA-TUS section.WriteFor the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be writ-ten. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C).After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be described later in this document.Once the Write cycle has been started, it is inter-nally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction.9/31M93C86, M93C76, M93C66, M93C56, M93C4610/31Erase AllThe Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1).The format of the instruction requires that a dum-my address be provided. The Erase cycle is con-ducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be de-scribed in the READY/BUSY STATUS section.Write AllAs with the Erase All Memory (ERAL) instruction,the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy ad-dress be provided. As with the Write Data to Mem-ory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction re-quires that an 8-bit data byte, or 16-bit data word,be provided. This value is written to all the ad-dresses of the memory device. The completion of the cycle can be detected by monitoring theNote:For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..READY/BUSY STATUSWhile the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Se-lect Input (S) is driven High. (Please note, though, that there is an initial delay, of t SLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Se-lect Input (S) is driven High, the Ready signal (Q=1) indicates that the M93Cx6 is ready to re-ceive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought Low or until a new start bit is decoded. COMMON I/O OPERATIONSerial Data Output (Q) and Serial Data Input (D) can be connected together, through a current lim-iting resistor, to form a common, single-wire data bus. Some precautions must be taken when oper-ating the memory in this way, mostly to prevent a short circuit current from flowing when the last ad-dress bit (A0) clashes with the first data bit on Se-rial Data Output (Q). Please see the application note AN394 for details. CLOCK PULSE COUNTERIn a noisy environment, the number of pulses re-ceived on Serial Clock (C) may be greater than the number delivered by the master (the microcontrol-ler). This can lead to a misalignment of the instruc-tion of one or more bits (as shown in Figure 7.) and may lead to the writing of erroneous data at an er-roneous address.To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select In-put (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified.The number of clock cycles expected for each in-struction, and for each member of the M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to Memory (WRITE) in-struction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:1 Start bit+ 2 Op-code bits+ 9 Address bits+ 8 Data bitsMAXIMUM RATINGStressing the device above the rating listed in the Absolute Maximum Ratings" table may cause per-manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im-plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu-ments.Table 8. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)Symbol ParameterMin.Max.Unit T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering See note 1°C V OUT Output range (Q = V OH or Hi-Z)–0.50V CC +0.5V V IN Input range –0.50V CC +1V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000VDC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 9. Operating Conditions (M93Cx6)Table 10. Operating Conditions (M93Cx6-W)Table 11. Operating Conditions (M93Cx6-R)Symbol ParameterMin.Max.Unit V CCSupply Voltage4.55.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 7)–40105°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CCSupply Voltage2.5 5.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 7)–40105°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating Temperature (Device Grade 6)–4085°CTable 12. AC Measurement Conditions (M93Cx6)Note: 1.Output Hi-Z is defined as the point where data out is no longer driven.Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)Note: 1.Output Hi-Z is defined as the point where data out is no longer driven.Table 14. CapacitanceNote:Sampled only, not 100% tested, at T A =25°C and a frequency of 1MHz.Symbol Parameter Min.Max.Unit C LLoad Capacitance 100pFInput Rise and Fall Times 50ns Input Pulse Voltages0.4V to 2.4V V Input Timing Reference Voltages 1.0V and 2.0V V Output Timing Reference Voltages0.8V and 2.0VVSymbol Parameter Min.Max.Unit C LLoad Capacitance 100pFInput Rise and Fall Times 50ns Input Pulse Voltages0.2V CC to 0.8V CC V Input Timing Reference Voltages 0.3V CC to 0.7V CC V Output Timing Reference Voltages0.3V CC to 0.7V CCVSymbol ParameterTest Condition MinMax Unit C OUT OutputCapacitance V OUT = 0V 5pF C INInputCapacitanceV IN = 0V5pFNote: 1.Current product: identified by Process Identification letter F or M.2.New product: identified by Process Identification letter W or G or S.Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)Note: 1.Current product: identified by Process Identification letter F or M.2.New product: identified by Process Identification letter W or G or S.I LI Input Leakage Current 0V ≤ V IN ≤ V CC±2.5 µA I LOOutput Leakage Current0V ≤ V OUT ≤ V CC , Q in Hi-Z ±2.5 µA I CCSupply CurrentV CC = 5V, S = V IH , f = 1 MHz, CurrentProduct 11.5 mA V CC = 5V, S = V IH , f = 2 MHz, NewProduct 22 mA I CC1Supply Current (Stand-by)V CC = 5V , S = V SS , C = V SS ,ORG = V SS or V CC , Current Product 150µAV CC = 5V , S = V SS , C = V SS , ORG = V SS or V CC , New Product 215 µAV IL Input Low Voltage V CC = 5V ± 10%–0.450.8 V V IH Input High Voltage V CC = 5V ± 10%2V CC + 1 V V OL Output Low Voltage V CC = 5V, I OL = 2.1mA 0.4 V V OHOutput High VoltageV CC = 5V , I OH = –400µA2.4VSymbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current 0V ≤ V IN ≤ V CC±2.5 µA I LOOutput Leakage Current0V ≤ V OUT ≤ V CC , Q in Hi-Z ±2.5µAI CCSupply CurrentV CC = 5V, S = V IH , f = 1 MHz, CurrentProduct 11.5 mA V CC = 5V, S = V IH , f = 2 MHz, NewProduct 22 mA I CC1Supply Current (Stand-by)V CC = 5V , S = V SS , C = V SS ,ORG = V SS or V CC , Current Product 150 µA V CC = 5V , S = V SS , C = V SS , ORG = V SS or V CC , New Product 215 µA V IL Input Low Voltage V CC = 5V ± 10%–0.450.8 V V IH Input High Voltage V CC = 5V ± 10%2V CC + 1 V V OL Output Low Voltage V CC = 5V, I OL = 2.1mA 0.4 V V OHOutput High VoltageV CC = 5V , I OH = –400µA2.4V。