蓝牙STM8S003K3 STM8S003F3 Rev4

stm8s和stm8l低功耗对⽐stm8s和stm8l低功耗对⽐ 在低功耗应⽤中，⼀般来说mcu是常态halt模式，然后偶尔被唤醒(外部中断或者内部定时唤醒)进⼊运⾏模式。

所以对⽐低功耗性能，⼀般来说只需要对⽐run模式和halt下的功耗即可，因为项⽬选⽤的是通过内部定时器唤醒，所以选⽤active halt mode。

以下是stm8s003和stm8l151在这两种模式下的功耗对⽐：run mode：stm8sstm8l对⽐ 在使⽤同样的16M内部RC振荡器情况下，stm8s 3.7ma,stm8l 3.54ma，两款mcu耗电量差不多。

active halt mode：stm8sstm8l对⽐ 在同样的关闭外设，且使⽤内部低速RC振荡器唤醒的情况下：stm8s 10ua，stm8l 0.54ua。

⼤约有20倍的差距，不过对于要求不是特别⾼的情况下，ua级别的差距影响不会太⼤。

实测：为了实际验证，分别将单⽚机焊接到空板⼦上编写代码进⾏测试。

stm8 编写如下代码：32ms唤醒⼀次主程序：void main(void){CLK_HSECmd ( DISABLE );CLK_SYSCLKConfig(CLK_PRESCALER_HSIDIV1);AWU_DeInit();AWU_Init(AWU_TIMEBASE_32MS);CLK_SlowActiveHaltWakeUpCmd(ENABLE); //关闭活跃停机模式下的电压调节器(MVR)CLK_FastHaltWakeUpCmd(DISABLE); //关闭快速唤醒FLASH_SetLowPowerMode(FLASH_LPMODE_POWERDOWN); //设置为停机后flash掉电GPIO_Init(GPIOA,GPIO_PIN_ALL,GPIO_MODE_OUT_PP_LOW_SLOW);GPIO_Init(GPIOB,GPIO_PIN_ALL,GPIO_MODE_OUT_PP_LOW_SLOW);GPIO_Init(GPIOC,GPIO_PIN_ALL,GPIO_MODE_OUT_PP_LOW_SLOW);GPIO_Init(GPIOD,GPIO_PIN_ALL,GPIO_MODE_OUT_PP_LOW_SLOW);GPIO_WriteLow(GPIOA,GPIO_PIN_ALL);GPIO_WriteLow(GPIOB,GPIO_PIN_ALL);GPIO_WriteLow(GPIOC,GPIO_PIN_ALL);GPIO_WriteLow(GPIOD,GPIO_PIN_ALL);AWU_Cmd(ENABLE);while(1){ halt();}}中断处理程序：INTERRUPT_HANDLER(AWU_IRQHandler, 1){/* In order to detect unexpected events during development,it is recommended to set a breakpoint on the following instruction.*/u8 awu_temp = 0;awu_temp = AWU_GetFlagStatus();}程序下载到单⽚机后，串到台式万⽤表上实测电流11ua,见下图：stm8l 编写如下代码：32ms唤醒⼀次主程序：void main(void){GPIO_Init(GPIOA, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Init(GPIOB, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Init(GPIOC, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Init(GPIOD, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Init(GPIOE, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Init(GPIOF, GPIO_Pin_All, GPIO_Mode_Out_PP_Low_Slow);GPIO_Write(GPIOA,0x00);GPIO_Write(GPIOB,0x00);GPIO_Write(GPIOC,0x00);GPIO_Write(GPIOD,0x00);GPIO_Write(GPIOE,0x00);GPIO_Write(GPIOF,0x00);RTC_DeInit(); //初始化默认状态CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE); //允许RTC时钟CLK_RTCClockConfig(CLK_RTCCLKSource_LSI, CLK_RTCCLKDiv_1); // 38K/1 RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div2); //38/2=19KRTC_SetWakeUpCounter(19*32); //19*32 32msRTC_ITConfig(RTC_IT_WUT, ENABLE); //开启中断PWR_FastWakeUpCmd(DISABLE); //关闭快速唤醒功能PWR_UltraLowPowerCmd(ENABLE);//超低功耗RTC_WakeUpCmd(ENABLE);while(1){ halt();}}中断处理程序：INTERRUPT_HANDLER(RTC_CSSLSE_IRQHandler,4){/* In order to detect unexpected events during development,it is recommended to set a breakpoint on the following instruction.*/RTC_ClearITPendingBit(RTC_IT_WUT);}将程序下载到单⽚机后，串到台式万⽤表测试电流在4ua左右，见下图：。

stm8开发环境配置及测试需要准备的软件，硬件，IAR for stm8 （EWSTM8）、stm8s标准固件库、ST-LINK、STM8s003f3核⼼板安装IAR（其中包括st-link的驱动），使⽤IAR新建⼀个⼯程，具体步骤如下：1,File->New->Workspace2,创建⼀个⼯程：Project->Create New Project...3,在弹出的对话框中选择C，-》OK4，根据提⽰保存你的⼯程5，从stm8s标准固件库中复制Libraries⽬录到你的⼯程⽬录，复制\STM8S_StdPeriph_Lib_V2.1.0\Project\STM8S_StdPeriph_Examples\GPIO到你的⼯程⽬录6，IAR的⼯程配置：在⼯程中添加两个组Libraries，MyApp。

右击你的⼯程->Add->Add Group7，将库中的*.c⽂件和主程序⽬录的*.c⽂件分别添加到Libraries, MyApp;右击相应组->add->add files8，选择单⽚机型号：右击你的⼯程Options->General Options->选择你单⽚机的型号9，配置头⽂件搜索路径：上⼀步切换到C/C++ Complier->Preprocessor->Additional include directory: ( one per line)10,选择调试器：切换到Debugger->Driver选择ST-Link->OK现在开始编译拍错1，右键main.c->Comliper会提⽰保存workspace，按提⽰操作，编译中会提⽰没有定义Fatal Error[Pe035]: #error directive: "Please select first the target STM8S/A device used in your application (in stm8s.h file)" C:\Documents and Settings\Administrator\桌⾯\EWSTM8_turial\Libraries\STM8S_StdPeriph_Driver\inc\stm8s.h 65双击该条提⽰，⾃动定位到错误位置，表⽰没有定义单⽚机型号，定义上#define STM8S003F32，再次执⾏1，这次的提⽰变为Error[Pe020]: identifier "GPIOH" is undefined C:\Documents and Settings\Administrator\桌⾯\EWSTM8_turial\GPIO\GPIO_Toggle\main.c 54双击该提⽰，定位到错误位置，向上找到 #define LED_GPIO_PORT (GPIOH)将GPIOH改为GPIOD（STM8S003F3没有GPIOH这个IO）3，再次执⾏1，OK没有错误4，整体编译⼀遍：右击⼯程->Make.在编译过程中有⼀部分⽂件会报错，不要担⼼，这些是STM8S003F3中没有的资源，将报错的⽂件删除即可另外对固件库了解后，可以只添加需要的部分，⽐如这次使⽤的是stm8s_gpio.c,那么只添加stm8s_gpio.c就可以了5，删除不需要的，再编译：OK没有错误，没有警告下载并调试，1，将STM8核⼼板通过SWIM与ST-Link连接起来，注意线序2，将ST-Link连接到电脑，（在设备管理器中usb总线中会看到ST-link的相关信息）3，给stm8核⼼板加电4，点击IAR的Download and debug，点击Go。

stm8s103头⽂件//==============================================================================//============================================================================== //==============================================================================//INTERRUPT ⼊⼝//==============================================================================#ifndef __STM8S103_H#define __STM8S103_Htypedef unsigned char uint8;typedef unsigned int uint16;#define BIT0 (0x01)#define BIT1 (0x02)#define BIT2 (0x04)#define BIT3 (0x08)#define BIT4 (0x10)#define BIT5 (0x20)#define BIT6 (0x40)#define BIT7 (0x80)#define _INT_RESET 0x00#define _INT_TRAP 0x01#define _INT_TLI 0x02#define _INT_AWU 0x03#define _INT_CLK 0x04#define _INT_PA 0x05#define _INT_PB 0x06#define _INT_PC 0x07#define _INT_PD 0x08#define _INT_PE 0x09#define _INT_CAN_TX 0x0A#define _INT_CAN_RX 0x0B#define _INT_SPI 0x0C#define _INT_TIM1 0x0D#define _INT_TIM1CC 0x0E#define _INT_TIM2 0x0F#define _INT_TIM2CC 0x10#define _INT_TIM3 0x11#define _INT_TIM3CC 0x12#define _INT_UART1_TX 0x13#define _INT_UART1_RX 0x14#define _INT_IIC 0x15#define _INT_UART2_TX 0x16#define _INT_UART2_RX 0x17#define _INT_ADC1 0x18#define _INT_TIM14 0x19#define _INT_FLASH 0x1A//==============================================================================////============================================================================== #define PA_ODR (*(volatile unsigned char*)0x5000)#define PA_IDR (*(volatile unsigned char*)0x5001)#define PA_DDR (*(volatile unsigned char*)0x5002)#define PA_CR1 (*(volatile unsigned char*)0x5003)#define PA_CR2 (*(volatile unsigned char*)0x5004)#define PB_ODR (*(volatile unsigned char*)0x5005)#define PC_ODR (*(volatile unsigned char*)0x500a)#define PC_IDR (*(volatile unsigned char*)0x500b)#define PC_DDR (*(volatile unsigned char*)0x500c)#define PC_CR1 (*(volatile unsigned char*)0x500d)#define PC_CR2 (*(volatile unsigned char*)0x500e)#define PD_ODR (*(volatile unsigned char*)0x500f)#define PD_IDR (*(volatile unsigned char*)0x5010)#define PD_DDR (*(volatile unsigned char*)0x5011)#define PD_CR1 (*(volatile unsigned char*)0x5012)#define PD_CR2 (*(volatile unsigned char*)0x5013)#define PE_ODR (*(volatile unsigned char*)0x5014)#define PE_IDR (*(volatile unsigned char*)0x5015)#define PE_DDR (*(volatile unsigned char*)0x5016)#define PE_CR1 (*(volatile unsigned char*)0x5017)#define PE_CR2 (*(volatile unsigned char*)0x5018)#define PF_ODR (*(volatile unsigned char*)0x5019)#define PF_IDR (*(volatile unsigned char*)0x501a)#define PF_DDR (*(volatile unsigned char*)0x501b)#define PF_CR1 (*(volatile unsigned char*)0x501c)#define PF_CR2 (*(volatile unsigned char*)0x501d)#define PG_ODR (*(volatile unsigned char*)0x501e)#define PG_IDR (*(volatile unsigned char*)0x501f)#define PG_DDR (*(volatile unsigned char*)0x5020)#define PG_CR1 (*(volatile unsigned char*)0x5021)#define PG_CR2 (*(volatile unsigned char*)0x5022)#define PH_ODR (*(volatile unsigned char*)0x5023)#define PH_IDR (*(volatile unsigned char*)0x5024)#define PH_DDR (*(volatile unsigned char*)0x5025)#define PH_CR1 (*(volatile unsigned char*)0x5026)#define PH_CR2 (*(volatile unsigned char*)0x5027)#define PI_ODR (*(volatile unsigned char*)0x5028)#define PI_IDR (*(volatile unsigned char*)0x5029)#define PI_DDR (*(volatile unsigned char*)0x502a)#define PI_CR1 (*(volatile unsigned char*)0x502b)#define PI_CR2 (*(volatile unsigned char*)0x502c)#define FLASH_CR1 (*(volatile unsigned char*)0x505A) #define FLASH_CR2 (*(volatile unsigned char*)0x505B) #define FLASH_NCR2 (*(volatile unsigned char*)0x505C) #define FLASH_FPR (*(volatile unsigned char*)0x505D) #define FLASH_NFPR (*(volatile unsigned char*)0x505E) #define FLASH_IAPSR (*(volatile unsigned char*)0x505F) #define FLASH_PUKR (*(volatile unsigned char*)0x5062) #define FLASH_DUKR (*(volatile unsigned char*)0x5064) #define EXTI_CR1 (*(volatile unsigned char*)0x50A0)#define EXTI_CR2 (*(volatile unsigned char*)0x50A1)#define RST_SR (*(volatile unsigned char*)0x50B3)#define CLK_ICKR (*(volatile unsigned char*)0x50C0)#define CLK_ECKR (*(volatile unsigned char*)0x50C1) #define CLK_CMSR (*(volatile unsigned char*)0x50C3) #define CLK_SWR (*(volatile unsigned char*)0x50C4) #define CLK_SWCR (*(volatile unsigned char*)0x50C5)#define WWDG_CR (*(volatile unsigned char*)0x50D1) #define WWDG_WR (*(volatile unsigned char*)0x50D2)#define IWDG_KR (*(volatile unsigned char*)0x50E0) #define IWDG_PR (*(volatile unsigned char*)0x50E1) #define IWDG_RLR (*(volatile unsigned char*)0x50E2)#define AWU_CSR1 (*(volatile unsigned char*)0x50F0) #define AWU_ARP (*(volatile unsigned char*)0x50F1) #define AWU_TBR (*(volatile unsigned char*)0x50F2) #define BEEP_CSR (*(volatile unsigned char*)0x50F3)#define SPI_CR1 (*(volatile unsigned char*)0x5200)#define SPI_CR2 (*(volatile unsigned char*)0x5201)#define SPI_ICR (*(volatile unsigned char*)0x5202)#define SPI_SR (*(volatile unsigned char*)0x5203)#define SPI_DR (*(volatile unsigned char*)0x5204)#define SPI_CRCPR (*(volatile unsigned char*)0x5205) #define SPI_RXCRCR (*(volatile unsigned char*)0x5206) #define SPI_TXCRCR (*(volatile unsigned char*)0x5207) #define I2C_CR1 (*(volatile unsigned char*)0x5210)#define I2C_CR2 (*(volatile unsigned char*)0x5211)#define I2C_FREQR (*(volatile unsigned char*)0x5212) #define I2C_OARL (*(volatile unsigned char*)0x5213)#define I2C_OARH (*(volatile unsigned char*)0x5214)#define I2C_DR (*(volatile unsigned char*)0x5216)#define I2C_SR1 (*(volatile unsigned char*)0x5217)#define I2C_SR2 (*(volatile unsigned char*)0x5218)#define I2C_SR3 (*(volatile unsigned char*)0x5219)#define I2C_ITR (*(volatile unsigned char*)0x521A)#define I2C_CCRL (*(volatile unsigned char*)0x521B)#define I2C_CCRH (*(volatile unsigned char*)0x521C)#define I2C_TRISER (*(volatile unsigned char*)0x521D) #define I2C_PECR (*(volatile unsigned char*)0x521E)#define UART1_SR (*(volatile unsigned char*)0x5230)#define UART1_DR (*(volatile unsigned char*)0x5231) #define UART1_BRR1 (*(volatile unsigned char*)0x5232) #define UART1_BRR2 (*(volatile unsigned char*)0x5233) #define UART1_CR1 (*(volatile unsigned char*)0x5234) #define UART1_CR2 (*(volatile unsigned char*)0x5235) #define UART1_CR3 (*(volatile unsigned char*)0x5236) #define UART1_CR4 (*(volatile unsigned char*)0x5237) #define UART1_CR5 (*(volatile unsigned char*)0x5238) #define UART1_GTR (*(volatile unsigned char*)0x5239) #define UART1_PSCR (*(volatile unsigned char*)0x523a) #define TIM1_CR1 (*(volatile unsigned char*)0x5250)#define TIM1_CR2 (*(volatile unsigned char*)0x5251)#define TIM1_SMCR (*(volatile unsigned char*)0x5252) #define TIM1_ETR (*(volatile unsigned char*)0x5253)#define TIM1_IER (*(volatile unsigned char*)0x5254)#define TIM1_SR1 (*(volatile unsigned char*)0x5255)#define TIM1_SR2 (*(volatile unsigned char*)0x5256)#define TIM1_EGR (*(volatile unsigned char*)0x5257)#define TIM1_CCMR1 (*(volatile unsigned char*)0x5258) #define TIM1_CCMR2 (*(volatile unsigned char*)0x5259)#define TIM1_ARRH (*(volatile unsigned char*)0x5262) #define TIM1_ARRL (*(volatile unsigned char*)0x5263) #define TIM1_RCR (*(volatile unsigned char*)0x5264)#define TIM1_CCR1H (*(volatile unsigned char*)0x5265) #define TIM1_CCR1L (*(volatile unsigned char*)0x5266) #define TIM1_CCR2H (*(volatile unsigned char*)0x5267) #define TIM1_CCR2L (*(volatile unsigned char*)0x5268) #define TIM1_CCR3H (*(volatile unsigned char*)0x5269) #define TIM1_CCR3L (*(volatile unsigned char*)0x526A) #define TIM1_CCR4H (*(volatile unsigned char*)0x526B) #define TIM1_CCR4L (*(volatile unsigned char*)0x526C) #define TIM1_BKR (*(volatile unsigned char*)0x526D)#define TIM1_DTR (*(volatile unsigned char*)0x526E)#define TIM1_OISR (*(volatile unsigned char*)0x526F) #define TIM2_CR1 (*(volatile unsigned char*)0x5300)#define TIM2_IER (*(volatile unsigned char*)0x5303)#define TIM2_SR1 (*(volatile unsigned char*)0x5304)#define TIM2_SR2 (*(volatile unsigned char*)0x5305)#define TIM2_EGR (*(volatile unsigned char*)0x5306)#define TIM2_CCMR1 (*(volatile unsigned char*)0x5307) #define TIM2_CCMR2 (*(volatile unsigned char*)0x5308) #define TIM2_CCMR3 (*(volatile unsigned char*)0x5309) #define TIM2_CCER1 (*(volatile unsigned char*)0x530A) #define TIM2_CCER2 (*(volatile unsigned char*)0x530B) #define TIM2_CNTRH (*(volatile unsigned char*)0x530C) #define TIM2_CNTRL (*(volatile unsigned char*)0x530D) #define TIM2_PSCR (*(volatile unsigned char*)0x530E) #define TIM2_ARRH (*(volatile unsigned char*)0x530F) #define TIM2_ARRL (*(volatile unsigned char*)0x5310) #define TIM2_CCR1H (*(volatile unsigned char*)0x5311) #define TIM2_CCR1L (*(volatile unsigned char*)0x5312) #define TIM2_CCR2H (*(volatile unsigned char*)0x5313) #define TIM2_CCR2L (*(volatile unsigned char*)0x5314) #define TIM2_CCR3H (*(volatile unsigned char*)0x5315) #define TIM2_CCR3L (*(volatile unsigned char*)0x5316) #define TIM4_CR1 (*(volatile unsigned char*)0x5340)#define TIM4_IER (*(volatile unsigned char*)0x5343)#define TIM4_SR (*(volatile unsigned char*)0x5344) #define TIM4_EGR (*(volatile unsigned char*)0x5345)#define TIM4_CNTR (*(volatile unsigned char*)0x5346) #define TIM4_PSCR (*(volatile unsigned char*)0x5347) #define TIM4_ARR (*(volatile unsigned char*)0x5348)#define ADC_DB0R (*(volatile unsigned char*)0x53E0) #define ADC_DB1R (*(volatile unsigned char*)0x53E1) #define ADC_DB2R (*(volatile unsigned char*)0x53E2) #define ADC_DB3R (*(volatile unsigned char*)0x53E3) #define ADC_DB4R (*(volatile unsigned char*)0x53E4) #define ADC_DB5R (*(volatile unsigned char*)0x53E5) #define ADC_DB6R (*(volatile unsigned char*)0x53E6) #define ADC_DB7R (*(volatile unsigned char*)0x53E7) #define ADC_DB8R (*(volatile unsigned char*)0x53E8) #define ADC_DB9R (*(volatile unsigned char*)0x53E9) #define ADC_DB10R (*(volatile unsigned char*)0x53EA) #define ADC_DB11R (*(volatile unsigned char*)0x53EB) #define ADC_DB12R (*(volatile unsigned char*)0x53EC) #define ADC_DB13R (*(volatile unsigned char*)0x53ED) #define ADC_DB14R (*(volatile unsigned char*)0x53EE)#define ADC_CSR (*(volatile unsigned char*)0x5400)#define ADC_CR1 (*(volatile unsigned char*)0x5401)#define ADC_CR2 (*(volatile unsigned char*)0x5402)#define ADC_CR3 (*(volatile unsigned char*)0x5403)#define ADC_DRH (*(volatile unsigned char*)0x5404)#define ADC_DRL (*(volatile unsigned char*)0x5405)#define ADC_TDRH (*(volatile unsigned char*)0x5406)#define ADC_TDRL (*(volatile unsigned char*)0x5407)#define ADC_HTRH (*(volatile unsigned char*)0x5408)#define ADC_HTRL (*(volatile unsigned char*)0x5409)#define ADC_LTRH (*(volatile unsigned char*)0x540A)#define ADC_LTRL (*(volatile unsigned char*)0x540B)#define ADC_AWSRH (*(volatile unsigned char*)0x540C)#define ADC_AWSRL (*(volatile unsigned char*)0x540D)#define ADC_AWCRH (*(volatile unsigned char*)0x540E)#define ADC_AWCRL (*(volatile unsigned char*)0x540F)#define ADD_ID_S 0x4865 //ID号起始地址#define ADD_ID_E 0X4870 //ID号结束地址#define ADD_FLASH_S 0X8000 //flash起始地址#define ADD_FLASH_E 0X9fff //flash结束地址#define CFG_GCR (*(volatile unsigned char*)0x7F60)//==============================================================================#define SBIT(var,bit) (var|=(1<<(bit))) //位设置#define CBIT(var,bit) (var&=(~(1<<(bit)))) //位清零#define RBIT(var,bit) (var^=(1<<(bit))) //位取反#define GBIT(var,bit) (var&(1<<bit)) //取位数据#define _IO_OH(P,B) (SBIT(P##_ODR,B)) //将端⼝P 的B位置1#define _IO_OL(P,B) (CBIT(P##_ODR,B)) //将端⼝P 的B位置0#define _IO_OR(P,B) (RBIT(P##_ODR,B)) //将端⼝P 的B位取反#define _IO_DO(P,B) (GBIT(P##_ODR,B)) //取端⼝P的B位输出值#define _IO_MO(P,B) (SBIT(P##_DDR,B)) //端⼝P的B位设置为输出⼝#define _IO_MI(P,B) (CBIT(P##_DDR,B)) //端⼝P的B位设置为输⼊⼝#define _IO_DI(P,B) (GBIT(P##_IDR,B)) //取端⼝P的B位输⼊值#define _IO_IF(P,B) (CBIT(P##_CR1,B)) //输⼊⼝悬空#define _IO_IR(P,B) (SBIT(P##_CR1,B)) //输⼊⼝上拉电阻#define _IO_OC(P,B) (CBIT(P##_CR1,B)) //输出⼝开漏#define _IO_OP(P,B) (SBIT(P##_CR1,B)) //输出⼝推挽输出#define _IO_IE(P,B) (SBIT(P##_CR2,B)) //输⼊⼝中断允许#define _IO_ID(P,B) (CBIT(P##_CR2,B)) //输⼊⼝中断禁⽌#define _IO_CH(P,B) (SBIT(P##_CR2,B)) //输出⼝⾼速输出#define _IO_CL(P,B) (CBIT(P##_CR2,B)) //输出⼝低速输出//============================================================================== //==============================================================================#define E_IWDG IWDG_KR=0XCC //看门狗允许#define R_IWDG(x) IWDG_KR=0X55;IWDG_RLR=x;IWDG_KR=0XAA //看门狗装载值#define D_IWDG(x) IWDG_KR=0X55;IWDG_PR=x;IWDG_KR=0XAA //看门狗时钟分频值//==============================================================================#define END_AD GBIT(ADC_CSR,7) //AD转换结束标志位#define CH0_AD ADC_CSR&=0Xf0 //AD0通道#define CH1_AD ADC_CSR&=0Xf0;ADC_CSR|=0x01 //AD1通道#define CH2_AD ADC_CSR&=0Xf0;ADC_CSR|=0x02 //AD2通道#define CH3_AD ADC_CSR&=0Xf0;ADC_CSR|=0x03 //AD3通道#define CH4_AD ADC_CSR&=0Xf0;ADC_CSR|=0x04 //AD4通道#define CH5_AD ADC_CSR&=0Xf0;ADC_CSR|=0x05 //AD5通道#define CH6_AD ADC_CSR&=0Xf0;ADC_CSR|=0x06 //AD6通道#define CH7_AD ADC_CSR&=0Xf0;ADC_CSR|=0x07 //AD7通道#define CH8_AD ADC_CSR&=0Xf0;ADC_CSR|=0x08 //AD8通道#define CH9_AD ADC_CSR&=0Xf0;ADC_CSR|=0x09 //AD9通道#define CH10_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0a //AD10通道#define CH11_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0b //AD11通道#define CH12_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0c //AD12通道#define CH13_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0d //AD13通道#define CH14_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0e //AD14通道#define CH15_AD ADC_CSR&=0Xf0;ADC_CSR|=0x0f //AD15通道#define ON_AD SBIT(ADC_CR1,0) //打开AD电源#define OFF_AD CBIT(ADC_CR1,0) //关闭AD#define STR_AD SBIT(ADC_CR1,0) //开始AD转换//============================================================================== #define DENB_WREEPROM GBIT(FLASH_IAPSR,3) //允许写EE标志位数据#define DIS_WREEPROM CBIT(FLASH_IAPSR,3) //EE写保护#define DEND_WREEPROM GBIT(FLASH_IAPSR,2) //写EE完成标志位数据//============================================================================== #define TIM1_IEN SBIT(TIM1_IER,0) //定时器1中断开#define TIM1_IDIS CBIT(TIM1_IER,0) //定时器1中断关#define TIM1_INT GBIT(TIM1_IER,0) //定时器1中断状态//============================================================================== #define BEEP_ENB BEEP_CSR|=0x20#define BEEP_DIS BEEP_CSR&=(~0x20)#define G_BEEP (BEEP_CSR&0X20)//============================================================================== #define SPI_ENB SPI_CR1|=0x40#define SPI_DIS SPI_CR1&=(~0x40)#endif。

ST单片机STM8S开发入门教程最近ST在国内大力推广他的8位高性价比单片机STM8S系列，感觉性能上还是非常不错的，网上稍微看了点资料，打算有机会还是学习一下，先入门为以后做好技术积累。

好了，长话短说。

手上拿到一套ST最近做活动赠送的三合一学习套件，上面包括STM32F小板、ST LINK小板、STM8S小板，做工很精致，相信很多朋友也收到了。

既然当初去申请了，人家也送了，总得把用起来吧，放着吃灰尘是很可惜的^_^ 。

好，步入正题，刚开始在论坛上逛了一圈，感觉STM8S的资料实在太少，都是官方的应用资料，没有什么入门介绍，连需要安装什么软件都搞不清楚。

偶的电脑光驱坏了，所以也读不出光盘里有什么东西，所以只能到处瞎摸，还是ourdev论坛好，嘿嘿，仔细看了几个帖子，总算明白大概是什么样的开发环境了。

用C语言开发STM8S，需要安装两个软件：1、STVD IDE开发环境；2、COSMIC for STM8 C编译器。

STVD可以到官网下载，下载地址：COSMIC 需要申请LICENSE，比较繁琐，刚好坛子有人传了一个免安装无限制版本的，偶就赶紧下载了，大家可以去下载，仅做为个人学习使用。

下载地址：软件下载后，只需安装STVD。

从上面地址下载的COSMIC不用安装，只要解压到硬盘即可。

后面建立工程的时候设置好路径即可。

下面一步一步开始啦～一、安装好STVD后，桌面上建立了两个快捷图标，ST Visual Develop就是STVD了。

ST Visual Programmer是编程软件，可以配合ST LINK对STM8S进行编程烧录。

二、双击运行ST Visual Develop，启动STVD开发环境。

执行Workspace，在New Workspace 窗口里选择Create workspace and projects，点击“确定”建立工作组和工程三、在Workspace 里输入Workspace名称，由于最终我们要测试一个现成的LED程序，所以偶写了led，随你喜欢了，呵呵。

头文件：Uart.h#ifndef _UART_H_#define _UART_H_#include"DataType.h"void Uart1_Init(u16 SYS_Clk, u32 baud);void Uart1_SendData(u8 data);void Uart1_IOConfig(void);extern u8 RecData;extern u8 flag;#endif源文件：Uart.c#include"iostm8s.h"#include"Uart.h"u8 RecData;u8 i=0;u8 flag;void Uart1_Init(u16 SYS_Clk, u32 baud){u16 UART_Temp=0;Uart1_IOConfig();USART1_CR2 = 0;// 禁止UART发送和接收USART1_CR1 = 0x00; //8bitUSART1_CR3 = 0x00; //1 stop bit// USART1_BRR2 = 0x0D;// USART1_BRR1 = 0x00; //9600 baud rate/************************************************** 设置波特率，必须注意以下几点：(1) 必须先写BRR2(2) BRR1存放的是分频系数的第11位到第4位，(3) BRR2存放的是分频系数的第15位到第12位，和第3位到第0位例如对于波特率位9600时，分频系数=2000000/9600=208对应的十六进制数为00D0，BBR1=0D,BBR2=00*************************************************/ UART_Temp = SYS_Clk*1000000/baud;USART1_BRR2 = (u8)((UART_Temp&0x000F)|((UART_Temp&0xF000)>>8));USART1_BRR1 = (u8)((UART_Temp&0x0FF0)>>4);USART1_CR2 = 0x2C; // b3 = 1,允许发送// b2 = 1,允许接收// b5 = 1,允许产生接收中断}@far @interrupt void USART1_RX_IRQHandler (void){u8 RxBuffer;RxBuffer = USART1_DR; //Store the received byte in RxBuffer//Uart1_SendData(Rec_whole[w]);RecData=RxBuffer&0x0ff;return;}void Uart1_SendData(u8 data){while((USART1_SR & 0x80) == 0x00); // 若发送寄存器不空，则等待USART1_DR = data; // 将要发送的字符送到数据寄存器}void Uart1_IOConfig(void){PD_DDR |= (1<<5);//输出模式 TXDPD_CR1 |= (1<<5);//推挽输出PD_DDR &=~(1<<6);//输入模式 RXDPD_CR1 &=~(1<<6);//浮空输入}。

程序总流程关系统总中断AD中断函数（64US）↓↓初始化端口换向检测和处理↓↓初始化时钟 4个通道的电流读取并且清标志位↓↓初始化UART1 加载PWM占空比↓↓初始化ADC 退出中断↓初始化TIMERE1↓打开系统总中断↓延时100MS↓读取转把电压↓读取角度切换端口，切换角度↓判断转把状态↓读取峰值，均值电流的基准，并判断是否超出↓MOS管检测↓从EEROM中读取锁电机方向标志位，和电流和欠压修改值↓While(1)主循环IO初始化PA1 :TB 锁电机内部上拉，外部要加105的下拉电阻PA2：TA 助力，标准的输入配置PA3：TXD或PA3 输出口PB0：输入，峰值电流通道PB1：输入，均值电流通道PB2：输入，电池电压通道PB3：输入，转把电压检测通道PB4：输入，标准的输入端口DC和PB4PB5：输入，标准的输入端口CR 巡航PB6：输入或者输出，外部无上拉电阻，有滤波电容PB7：输入或者输出，外部无上拉电阻，有滤波电容PC1：C下PC2：A下PC3：A上PC4：输入或者输出，外部无上拉电阻，有滤波电容，凌祥没有使用到此引脚PC5：刹车，内部上拉PC6：C上PC7：B上PE5 : B下PD0：刹车中断输入PD1：输出端口，和烧程序的SWIMPD2：输入端口霍尔SAPD3：输入端口霍尔SBPD4：输入端口霍尔SCPD5：输入端口SL，内部上拉PD6：输入端口ABS 内部上拉，外部加105下拉电阻PD7：输出,LED故障指示1 时钟STM8S903//RC输出，不分频。

16Mhz HSIDIV[1:0]：CLK_CKDIVR =0x00;//打开低速内部振荡器,高速内部RCCLK_ICKR =(1<<3)+(1<<0);ADC1：时钟8MHZ,单次扫描模式2：外部触发，右对齐模式3：扫描4个通道，这个地方有疑问4：64US中断一次，但是比刹车中断的优先级低，刹车可以打断AD转换中断TIMER1TIM1_ARR寄存器由预装载缓冲器缓冲，PWM的周期中央对齐模式2。

STM8S使用常用问题汇总==================================================================按外设模块===================================================================== =============================== GPIO/AFIO ========================== ================================== Beep ============================== ===1、STM8S提供一个Beep引脚。

通过简单的配置即可输出1K、2K、4K三种频率信号驱动外部蜂鸣器。

由于默认情况下Beep输出引脚PD4为TIM2_CC1功能，为此我们需要打开“Option Bytes”的AFR7选项。

打开STVP，选择你使用的MCU型号，找到"Option Bytes"标签。

将AFR 7改为"Port D4 Alternate Function ＝Beep"。

菜单栏选择"Program" －> "Current tab"，成功后，即可正常使用B eep输出功能。

================================================================================================= Power/RESET ======================= ==1、STM8S为双电源MCU，外设工作电压为3V～5.5V，内核工作电压为1.8V。

因MCU内部已集成1.8V 低功耗电压(LPVR)调节器，MCU工作仅需提供一个供电电源。

在电源电路设计时，需要注意芯片VCAP引脚上要提供滤波电容，该电容用于对内部1.8V供电滤波，容值不小于470nF为宜，瓷片和Ta电容均可，尽量选择较低ESR(等效串联电阻值)的型号。

UM0560User manualSTM8 bootloader 1 IntroductionThis document describes the features and operation of the STM8 integrated bootloaderprogram. This code embedded in the system memory of the device (ROM memory allowsmemories, including Flash program, data EEPROM, and RAM, to be written into the deviceusing the standard serial interfaces LINUART/UART/USART, SPI, and CAN.The bootloader code is similar for all STM8 versions. However, even though a peripheralmay be present in a product, the product may not support it (for example the SPI is notsupported in 128 Kbyte devices. In addition, different STM8 device types support differentperipherals (see Table5: Serial interfaces associated with STM8 devices for detailedinformation.For further information on the STM8 family features, pinout, electrical characteristics,mechanical data and ordering information, please refer to the STM8 datasheets.March 2011Doc ID 14798 Rev 41/70Contents UM0560Contents1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Bootloader introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1Bootloader activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Peripheral settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1USART/UARTs settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.1LINUART/UARTs in “reply” mode settings . . . . . . . . . . . . . . . . . . . . . . . 11 3.2SPI settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3CAN settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Bootloader command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1Get command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1.1Get command via USART/LINUART/UART1/ UART2/UART3 . . . . . . . . 15 4.1.2Get command via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.3Get command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2Read memory command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2.1Read memory command via USART/LINUART/UART1/UART2/UART3 214.2.2Read memory command via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.2.3Read memory command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.3Erase memory command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.3.1Erase memory command via USART/LINUART/UART1/UART2/UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.3.2Erase memory command via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314.3.3Erase memory command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.4Write memory command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.4.1Write memory command via USART/LINUART/UART1/UART2/UART3 364.4.2Write memory command via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.4.3Write memory command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.5Speed command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.5.1Speed command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.6Go command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.6.1Go command via USART/LINUART/UART1/UART2/UART3 . . . . . . . . . 454.6.2Go command via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472/70Doc ID 14798 Rev 4UM0560Contents4.6.3Go command via CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.7Sector codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.8Software model (STM8A/L/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.8.1RAM erase/write routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586Programming time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Appendix A How to upload ROP protected device . . . . . . . . . . . . . . . . . . . . . . . 60A.1Rules for upgrading ROP protected devices. . . . . . . . . . . . . . . . . . . . . . . 60 Appendix B Bootloader entry points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Appendix C SPI peripheral timing options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62C.1SPI with busy state checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62C.2Modified erase/write RAM routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Appendix D PC software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Appendix E Bootloader UART limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64E.1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64E.1.1UART automatic baudrate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . 64E.1.2Description of UART limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64E.2Workaround for UART limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Appendix F Limitations and improvements versus bootloader versions. . . . . 66 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Doc ID 14798 Rev 43/70List of tables UM0560 List of tablesTable 1.STM8 subfamilies featuring abootloader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. STM8 subfamilies without bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table3.Bootloader versions for which bootloader activation flowchart isvalid. . . . . . . . . . . . . . . . . 7 Table 4.Initialchecking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5.Serial interfaces associated with STM8devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6.Bootloadercommands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7.Bootloader codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 8.Examples ofdelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table9.STM8 sector codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 10.Errortable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table ART/LINUART/UART1/UART2/UART3 programmingtimes. . . . . . . . . . . . . . . . . . . . . 59 Table 12.SPI programmingtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 13.CAN programming time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 14.Bootloader entrypoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table15.Description of limitation, improvements and addedfeatures . . . . . . . . . . . . . . . . . . . . . . . 66 Table 16.Document revisionhistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/70Doc ID 14798 Rev 4UM0560List of figures List of figuresFigure 1.Bootloader activation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.CANframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3.Get command via USART/LINUART/UART1/UART2/UART3 - hostside . . . . . . . . . . . . . 15 Figure 4.Get command viaUSART/LINUART/UART1/UART2/UART3 - device side. . . . . . . . . . . . 16 Figure5.Get command via SPI - host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 6.Get command via SPI - deviceside . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7.Get command via CAN - host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8.Get command via CAN - device side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9.Read memory command via USART/LINUART/UART1/UART2/UART3 - host side. . . . . 21 Figure 10.Read memory command viaUSART/LINUART/UART1/UART2/UART3 - device side . . . 22 Figure 11.Read memory command via SPI - host side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12.Read memory command via SPI - deviceside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13.Read memory command via CAN - host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14.Read memory command via CAN - device side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.Erase memory command via USART/LINUART/UART1/UART2/UART3 - host side. . . . . 28 Figure 16.Erase memory command viaUSART/LINUART/UART1/UART2/UART3 - device side. . . 30 Figure 17.Erase memory command via SPI - host side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18.Erase memory command via SPI - deviceside . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19.Erase memory command via CAN - host side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 20.Erase memory command via CAN - device side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 21.Write memory command via USART/LINUART/UART1/UART2/UART3 - hostside . . . . . 36 Figure 22.Write memory command viaUSART/LINUART/UART1/UART2/UART3 - device side . . . 37 Figure 23.Write memory command via SPI - host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 24.Write memory command via SPI - deviceside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 25.Write memory command via CAN - host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 26.Write memory command via CAN - device side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 27.Speed command via CAN - hostside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 28.Speed command via CAN - device side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 29.Go command via USART/LINUART/UART1/UART2/UART3 - host side. . . . . . . . . . . . . .45 Figure 30.Go command via USART/LINUART/UART1/UART2/UART3 - device side . . . . . . . . . . . . 46 Figure 31.Go command via SPI - hostside . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 32.Go command via SPI - device side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 33.Go command via CAN - hostside . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 34.Go command via CAN - device side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure35.Delay elimination in modified RAMroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 36."Flash loader demonstrator" software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Doc ID 14798 Rev 45/706/70Doc ID 14798 Rev 42 Bootloader introductionThe main task of the bootloader is to download the application program into the internalmemories through the integrated peripherals (UARTs, SPI, or CAN without using the SWIM protocol and dedicated hardware. Data are provided by any device (host which is capable of sending information through one of the above-mentioned serial interfaces.The bootloader permits downloading of application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.The bootloader code is stored in the internal boot ROM memory. After a reset, thebootloader code checks whether the program memory is virgin or whether a specific option byte is set allowing code modifications.If these conditions are not fulfilled, the bootloader resumes and the user application is started.In case of a successful check the bootloader is executed.When the bootloader procedure starts, the main tasks are:●Polling all supported serial interfaces to check which peripheral is used●Programming code, data, option bytes and/or vector tables at the address(es received from the host.Each STM8 device embeds a specific bootloader code which is common to a whole group of STM8 devices. The correspondence between STM8 groups and STM8 part numbers is given in Table 1. Group names are used all over this user manual.Table 2 gives the list of STM8 devices without embedded bootloader (no ROM bootloader is implemented inside the microcontroller. When using these devices, youhave to write your own bootloader code and save it in the UBC program area (refer to STM8S and STM8A families reference manual for information on the UBC area.Table 1.STM8 subfamilies featuring a bootloaderSTM8 group STM8 part numbersSTM8A/S-128KSTM8AF52xx, STM8AF6269/8x/Ax, STM8AF51xx, STM8AF6169/7x/8x/9x/Ax,STM8S20xxx STM8A/S-32KSTM8AF622x/4x, STM8AF6266/68, STM8AF612x/4x, STM8AF6166/68,STM8S105xxSTM8L-64k STM8L15xx8, STM8L15xR6, STM8L16xx8STM8L-32KSTM8L15xC4, STM8L15xK4, STM8L15xG4,STM8L15xC6, STM8L15xK6, STM8L15xG6(x = 1 or 2STM8L-8KSTM8L15xC2, STM8L15xK2, STM8L15xG2, STM8L15xC3, STM8L15xK3, STM8L15xG3(x = 1 or 2Doc ID 14798 Rev 47/702.1 Bootloader activationThe STM8 hardware reset vector is located at the beginning of the boot ROM(0x006000,while the other interrupt vectors are in the Flash program memory starting at address 0x008004.The device executes the boot ROM (jumps inside the boot ROM area and after checking certain address locations (see Table 4: Initial checking on page 10, it starts to execute the bootloader or the user code defined by the reset vector (0x008000.The bootloader activation flowchart is described in Figure 1: Bootloader activation flowchart . In previous bootloader versions, a return to the “wait for SYNCHR” state (see dashed line in Figure 1 was performed when the “Flash virgin” test was positive. In newer versions, it has been replaced by a software (SW reset to prevent the customer firmware from remaining in a infinite loop (e.g. due to EMC disturbance. This bootloader modification is referred to as "EMC lockup protection" in T able 15. Table 3 lists the bootloader versions for which the dashed line was replaced by a SW reset.The bootloader version number of a given device is obtained by the “Get command” (see Section 4.1: Get command . The bootloader version is represented by a two-digitbinary-coded decimal (BCD number (with a decimal point between the two digits which is coded into one byte in the “Get command” result. For example, 0x21 version byte is bootloader version 2.1.Table 2.STM8 subfamilies without bootloaderSTM8 group STM8 part numbersSTM8A/S-8K STM8Sx03xx STM8L-8KSTM8L101xxTable 3.Bootloader versions for which bootloader activation flowchart is validSTM8 group Bootloader versionSTM8A/S-128K v2.2STM8A/S-32K v1.3STM8L-64K v1.0STM8L-32K v1.2STM8L-8Kv1.01.See Flow chart description on page9 for explanation of points 1 to 8.2.See Table4: Initial checking.3.Dotted routines are loaded in RAM by the host. They are removed by the go command before jumping to the Flash programmemory to execute an application.8/70Doc ID 14798 Rev 4Flow chart description1.Disable all interrupt sources.2. The host can start the bootloader process according to checks shown in Table4 (inkeeping with the content of the first Flash program memory location (0x008000 and “bootloader enable” option bytes. The host checks the following bootloader startconditions:Condition 1: the host checks if the device memory is empty by inspecting the content of address 0x00 8000 (reset vector. If the content is not equal to 0x82 or 0xAC, thedevice is recognized as being empty and the bootloader remains active and waits for host commands without timeouts.Condition 2: the host checks if the bootloader option bytes (two bytes are set to enable the bootloader or not. The bootloader is enabled with a value of 0x55AA and disabled by all other values (see the device datasheets for the bootloader option byte locations.If the option bytes are enabled, the bootloader remains active and waits for hostcommands with a 1-second timeout. If the host does not send a command within this timeout, the bootloader jumps directly to the application user vector (jump to address0x008000.Condition 3: If the option bytes disable the bootloader (by a value different from0x55AA, the bootloader jumps directly to the application user vector (jump to address 0x00 8000.The above checking process is summarized in T able4.3. When readout protection (ROP is active, the Flash program memory is readoutprotected. In this case, the bootloader stops and the user application starts. If ROP is inactive, the bootloader continues to be executed (see Appendix A: How to upload ROP protected device.4. The CAN peripheral can only be used if an external clock (8 MHz, 16 MHz, or 24 MHzis present. It is initialized at 125 kbps. The UARTs and SPI peripherals do not require an external clock.5. Set the high speed internal RC oscillator (HSI to 16 MHz and initialize the UARTsreceiver pins in input pull-up mode in the GPIO registers. Initialize the SPI in slave mode. Then, wait 4 ms for I/O pin voltage level stabilization. It is recommended that the host waits 10 ms from the STM8 reset before sending the SYNCHR byte/message.This is the time needed for bootloader initialization.Doc ID 14798 Rev 49/7010/70Doc ID 14798 Rev 46.Interface polling: The bootloader polls all peripherals waiting for a synchronizationbyte/message (SYNCHR = 0x7F within a timeout of 1 s. If a timeout occurs, either the Flash program memory is virgin in which case it waits for a synchronizationbyte/message in an infinite loop through a software reset, or the Flash programmemory is not virgin and the bootloader re stores the registers’ reset status and jumps to the memory address given by the reset vector (located at 0x008000. For thebootloader versions listed in Table 3, a software reset is generated after a timeout has elapsed, in case the Flash program memory is empty (this is because it is safer to stay in an infinite loop if there is a hardware chip error.Note:When synchronization fails (the bootloader receives a byte/message different to‘SYNCHR’ = 0x7F two different situations can be distinguished according to the peripheral:With the UART peripherals, a device reset or power-down is necessary beforesynchronization can be tried again. Refer to Appendix E: Bootloader UART limitation With the CAN or SPI peripheral, the user can continue to poll the interfaces until a synchronization or a timeout occurs.7.If the synchronization message is received by the UARTs, the bootloader automatically detects the baud rate, initializes the UART and goes to step 8 below. If thesynchronization message is received by the CAN or SPI, the bootloader goes directly to step 8 below.Note: Once one of the available interfaces receives the synchronization message, all others are disabled.8.Waiting for commands: Commands are checked in an infinite loop and executed. To exit from the bootloader, the host has to send a ‘GO’ command. When this is done, the bootloader removes the EM and WM routines from the RAM memory and jumps to the address selected by the host.Note:To be able to write/erase data in Flash and EEPROM the host must write into RAMexecutable routines for writing and erasing. Those routines (*.s19 files are provided with the bootloader. Host must upload those routines at address 0xA0. See section 4.8.1: RAM erase/write routines for more information.Note:After interface initialization, the ROP bit is checked to avoid non-authorized reading of the Flash program memory and data EEPROM.Table 4.Initial checkingChecksProgram memory byte location [0x008000]Bootloader check option bytes[BL_OPT](11.See device datasheet for the [BL_OPT] location in the option byte area memory map.Actual Flash program memory status-> Flash action1st [0x00 8000] <>(0x82 or 0xAC[BL_OPT] = 0x00XXXX Flash program memory virgin.-> jump to bootloader 2nd[0x00 8000] <>(0x82 or 0xAC[BL_OPT] = 0x0055AA Flash program memory already written, bootloader enabled by option bytes.-> jump to bootloader 3rd[0x00 8000] <>(0x82 or 0xAC[BL_OPT] <> 0x0055AAFlash program memory already written,bootloader disabled by option bytes.-> jump to Flash program memory resetUM0560Peripheral settingsDoc ID 14798 Rev 411/703 Peripheral settingsThis section describes the hardware settings of the STM8 communication peripherals:●UARTs/LINUART ●SPI ●CANNote:During bootloading only one peripheral (first addressed is enabled. All others are disabled.3.1 USART/UARTs settingsThis peripheral supports asynchronous serial communication.The USART/UARTs settings are:●Data frame: 1 start bit, 8 data bit, 1 parity bit set to even, 1 stop bit●Baud rate: The baud rate is automatically detected by the bootloader. When the usersends the synchronization byte, 0x7F , the bootloader automatically detects the baud rate and sets the USART/UARTs to the same baud rate. Maximum baud rate = 1 Mbps (115200 baud for STM8L-64K; minimum baud rate = 4800 bps.To perform the automatic speed detection, the RxD line must be stable in the application board (internal pull-up is enabled on the RxD line by the bootloader.3.1.1 LINUART/UARTs in “reply” mode settingsSettings are:●Data frame: 1 start bit, 8 data bit, no parity bit, 1 stop bit●Baud rate: The baud rate is automatically detected by the bootloader. When the user sends the synchronization byte 0x7F , the bootloader automatically detects the baud rate and sets the UARTs to the same baud rate. Maximum baud rate = 550 kbps (115200 baud for STM8L-64K; minimum baud rate = 4800 bps.To perform automatic speed detection, the RxD line must be stable in the application board (internal pull-up is enabled on the RxD line by the bootloader.Table 5.Serial interfaces associated with STM8 devices (11.The above table reflects only current bootloader versions and device states.STM8 groups Serial interfaceSTM8A-128K USART , LINUART (in “reply” mode, CAN STM8A-32K LINUART, SPISTM8S-128K UART1, UAR T3 (in “reply” mode, CAN STM8S-32K UART2 (in “reply” mode, SPI STM8L-8K UART, SPI STM8L-32K UARTSTM8L-64KUART1, UART2, UART3 (in “reply” mode,SPI1, SPI2Peripheral settings UM056012/70Doc ID 14798 Rev 4Reply modeThe host must reply to all the bytes sent from the bootloader. If TxD and RxD lines share the same physical medium (for example, 1-wire communication, then host replies are not necessary since RxD and TxD pins coincide.3.2 SPI settingsThe SPI settings are:●8 data bit, MSB first●Bit rate: S et by the host which acts as a master●Peripheral set in slave mode with software management of NSS●Data polarity : CPOL = 0 (SCK to 0 when idle, CPHA = 0 (the first clock transition is thefirst data capture edge.Note:1Before sending a ‘token’ byte, th e host has to wait for a delay of a specified period of time. If this period is not quantified, it is equal to 6 µs.2The SPI peripheral is accessible via SPI_SCK, SPI_MOSI and SPI_MISO pins.UM0560Peripheral settingsDoc ID 14798 Rev 413/703.3 CAN settingsTo address additional devices on the same bus, the CAN protocol provides a standardidentifier field (11-bit and an optional extended identifier field (18-bit in the frame. Figure 2 shows the CAN frame that uses the standard identifier only.The CAN settings are as follows:●Standard identifier (not extended●Bit rateBy default, it is 125 kbps. The runtime can be changed via the speed command to achieve a maximum bitrate of 1 Mbps.The transmit settings (from the STM8 to the host are:●Tx mailbox0: On●Tx mailbox1 and Tx mailbox2: Off ●Tx identifier: 0x02●Outgoing messages contain 1 data byteThe receive settings (from the host to the STM8 are:●The synchronization byte, 0x7F , is in the RX identifier and not in the data field●The RX identifier depends on the command (0x00, 0x03, 0x11, 0x21, 0x31, 0x43●Error checking: If the error field (bit [6:4] in the CESR register is different from 000b, the message is discarded and a NACK is sent to the host.●In FIFO overrun condition, the message is discarde d and a NACK is sent to the host.●Incoming messages can contain from 1 to 8 data bytes.Note:The CAN peripheral is accessible via CAN_TX and CAN_RX pins.Bootloader command set UM056014/70Doc ID 14798 Rev 44 Bootloader command setThe commands supported by the bootloader are listed in Table 6 below.Table 7.Bootloader codesWhen the bootloader receives a command via the UARTs, CAN or SPI peripherals, the general protocol is as follows:1.The bootloader sends an ACK byte (0x79 to the host and waits for an address and for a checksum byte, both of which are checked when received.2.When the address is valid and the checksum is correct, the bootloader transmits an ACK byte (0x79, otherwise it transmits a NACK byte (0x1F and aborts the command. The bootloader waits for the number of bytes to be transmitted (N bytes and for its complemented byte (checksum. –If the checksum is correct, it then carries out the command, starting from the received address.–If the checksum is incorrect, it sends a NACK (0x1F byte before aborting the command.Table 6.Bootloader commandsCommandCommand codeCommand descriptionGet 0x00Gets the version and the allowed commands supported bythe current version of the bootloaderRead memory 0x11Reads up to 256 bytes of memory starting from an address specified by the hostErase memory0x43Erases from one to all of the Flash program memory/data EEPROM sectorsWrite memory0x31Writes up to 128 bytes to RAM or the Flash programmemory/data EEPROM starting from an address specified by the hostSpeed 0x03Allows the baud rate for CAN runtime to be changed Go0x21。

This is information on a product in full production.August 2018DS7147 Rev 10Value line, 16-MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²CDatasheet - production dataFeaturesCore•16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline •Extended instruction setMemories•Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles •RAM: 1 Kbyte•Data memory: 128 bytes true data EEPROM;endurance up to 100 k write/erase cyclesClock, reset and supply management• 2.95 V to 5.5 V operating voltage•Flexible clock control, 4 master clock sources –Low-power crystal resonator oscillator –External clock input–Internal, user-trimmable 16 MHz RC –Internal low-power 128 kHz RC •Clock security system with clock monitor •Power management–Low-power modes (wait, active-halt, halt)–Switch-off peripheral clocks individually –Permanently active, low-consumption power-on and power-down resetInterrupt management•Nested interrupt controller with 32 interrupts •Up to 27 external interrupts on 6 vectorsTimers•Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization •16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)•8-bit basic timer with 8-bit prescaler •Auto wakeup timer•Window and independent watchdog timersCommunications interfaces•UART with clock output for synchronousoperation, SmartCard, IrDA, LIN master mode •SPI interface up to 8 Mbit/s •I 2C interface up to 400 Kbit/sAnalog to digital converter (ADC)•10-bit ADC, ± 1 LSB ADC with up to 5multiplexed channels, scan mode and analog watchdogI/Os•Up to 28 I/Os on a 32-pin package including 21high-sink outputs •Highly robust I/O design, immune against current injectionDevelopment support•Embedded single-wire interface module(SWIM) for fast on-chip programming and non-intrusive debuggingDescription STM8S003F3 STM8S003K3DS7147 Rev 102 DescriptionThe STM8S003F3/K3 value line 8-bit microcontrollers offer 8 Kbytes of Flash programmemory, plus integrated true data EEPROM. They are referred to as low-density devices in the STM8S microcontroller family reference manual (RM0016).The STM8S003F3/K3 value line devices provide the following benefits: performance, robustness and reduced system cost.Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-arttechnology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset.Full documentation is offered as well as a wide choice of development tools.Table 1. STM8S003F3/K3 value line featuresFeaturesSTM8S003K3STM8S003F3Pin count3220Max. number of GPIOs (I/O)2816External interrupt pins 2716Timer CAPCOM channels 77Timer complementary outputs 32A/D converter channels 45High-sink I/Os2112Low-density Flash program memory (byte)8 K 8 K RAM (byte)1 K 1 K True data EEPROM (byte)128(1)1.Without read-while-write capability.128(1)Peripheral setMulti purpose timer (TIM1), SPI, I2C, UART, Window WDG, independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)DS7147 Rev 10STM8S003F3 STM8S003K3Block diagram3 Block diagramFigure 1. STM8S003F3/K3 value line block diagramXTAL 1-16 MHzRC int. 16 MHzRC int. 128 kHzSTM8 coreDebug/SWIMUART1I2CSPIAWU timerReset blockResetPORBORClock controllerDetectorClock to peripherals and core400Kbit/s8Mbit/sup to 5A d d r e s s a n d d a t a b u sWindow WDG8 Kbyte 128 byte 1 Kbyte RAMADC1ResetSingle wiredebug interfaceprogram Flashdata EEPROM16-bit general purpose16-bit advanced controltimer (TIM1)timer (TIM2)8-bit basic timer(TIM4)Beeper1/2/4 kHz beepIndependent WDG4 CAPCOM channels Up to 3 CAPCOM channelsUp to + 3 complementaryoutputsLIN master channelsSPI emul.STM8S003F3 STM8S003K3Product overviewDS7147 Rev 10Product overview STM8S003F3 STM8S003K3DS7147 Rev 104.12 TIM4 - 8-bit basic timer•8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128•Clock source: CPU clock•Interrupt source: 1 x overflow/update4.13 Analog-to-digital converter (ADC1)STM8S003F3/K3 value line products contain a 10-bit successive approximation A/Dconverter (ADC1) with up to 5 external multiplexed input channels and the following main features: •Input voltage range: 0 to V DDA •Conversion time: 14 clock cycles•Single and continuous, buffered continuous conversion modes •Buffer size (10 x 10 bits)•Scan mode for single and continuous conversion of a sequence of channels •Analog watchdog capability with programmable upper and lower thresholds •Analog watchdog interrupt •External trigger input •Trigger from TIM1 TRGO •End of conversion (EOC) interruptNote:Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.4.14 Communication interfacesThe following communication interfaces are implemented:•UART1: full feature UART, synchronous mode, SPI master mode, SmartCard mode,IrDA mode, LIN2.1 master capability •SPI: full and half-duplex, 8 Mbit/s •I²C: up to 400 Kbit/sTable 3. TIM timer featuresTimerCounter size (bits)PrescalerCounting mode CAPCOM channels Complem. outputs Ext. trigger Timersynchr-onization/ chainingTIM1 16Any integer from 1 to 65536Up/down 43Yes NoTIM2 16Any power of 2 from 1 to 32768Up 30No TIM48Any power of 2 from 1 to 128UpNo。

···16-bit generalOC or PWM)with3CAPCO···RAM:memory:128bytes of true data EEPROM;·endurance up to100000write/erase cycles ·Window watchdog and independent watchdog ··I C interface up to400Kbit/s···Flexiblepower crystal resonator oscillator -··Highly robust I/O design,immune against current ·-Low power modes STM8S003K3STM8S003F3Value line,16MHz STM8S8-bit MCU,8Kbytes Flash,128bytes data EEPROM,10-bit ADC,3timers,UART,SPI,I²CInterrupt managementNested interrupt controller with32interrupts·Up to27external interrupts on6vectors LQFP327x7TSSOP20UFQFPN203x3FeaturesCore16MHz advanced STM8core with Harvardarchitecture and3-stage pipeline·Extended instruction setMemoriesProgram memory:8Kbytes Flash;data retention20years at55°C after100cyclesClock,reset and supply management2.95to5.5V operating voltageclock control,4master clock sources:·Power management:(wait,active-halt,halt)-Switch-off peripheral clocks individually·Permanently active,reset consumption power-onTimersAdvanced control timer:16-bit,4CAPCOMchannels,3complementary outputs,dead-timeinsertion and flexible synchronization,·8-bit basic timer with8-bit prescaler·Auto wake-up timerCommunications interfacesUART with clock output for synchronousoperation,Smartcard,IrDA,LIN master mode·SPI interface up to8Mbit/s2Analog to digital converter(ADC)10-bit,±1LSB ADC with up to5multiplexedchannels,scan mode and analog watchdogI/OsUp to28I/Os on a32-pin package including21high sink outputsDevelopment supportEmbedded single wire interface module(SWIM)for fast on-chip programming and non intrusivedebuggingJune2012DocID018576Rev31/100Contents STM8S003K3STM8S003F3 Contents1Introduction (7)2Description (8)3Block diagram (9)4Product overview (10)4.1Central processing unit STM8 (10)4.2Single wire interface module(SWIM)and debug module(DM) (10)4.3Interrupt controller (11)4.4Flash program memory and data EEPROM (11)4.5Clock controller (12)4.6Power management (13)4.7Watchdog timers (13)4.8Auto wakeup counter (14)4.9Beeper (14)4.10TIM1-16-bit advanced control timer (14)4.11TIM2-16-bit general purpose timer (15)4.12TIM4-8-bit basic timer (15)4.13Analog-to-digital converter(ADC1) (15)4.14Communication interfaces (16)4.14.1UART1 (16)4.14.2SPI (17)4.14.3I²C (17)5Pinout and pin description (18)5.1STM8S003K3LQFP32pinout and pin description (18)5.2STM8S003F3TSSOP20/UFQFPN20pinout and pin description (21)5.2.1STM8S003F3TSSOP20pinout and pin description (21)5.2.2STM8S003F3UFQFPN20pinout (22)5.2.3STM8S003F3TSSOP20/UFQFPN20pin description (22)5.3Alternate function remapping (24)6Memory and register map (25)6.1Memory map (25)6.2Register map (26)6.2.1I/O port hardware register map (26)6.2.2General hardware register map (27)6.2.3CPU/SWIM/debug module/interrupt controller registers (36)7Interrupt vector mapping (39)8Option bytes (41)8.1Alternate function remapping bits (43)2/100DocID018576Rev39.3.9 I C interface characteristics (80)STM8S003K3 STM8S003F3Contents9 Electrical characteristics .....................................................................................469.1 Parameter conditions ..................................................................................................46 9.1.1 Minimum and maximum values .......................................................... 46 9.1.2 Typical values ...................................................................................... 46 9.1.3 Typical curves ..................................................................................... 46 9.1.4 Loading capacitor ................................................................................ 46 9.1.5 Pin input voltage ..................................................................................46 9.2 Absolute maximum ratings ......................................................................................... 47 9.3 Operating conditions ...................................................................................................49 9.3.1 VCAP external capacitor ..................................................................... 50 9.3.2 Supply current characteristics ............................................................. 51 9.3.3 External clock sources and timing characteristics .............................. 60 9.3.4 Internal clock sources and timing characteristics ................................ 62 9.3.5 Memory characteristics .. (64)9.3.6 I/O port pin characteristics .................................................................. 66 9.3.7 Reset pin characteristics ..................................................................... 74 9.3.8 SPI serial peripheral interface ............................................................. 77 29.3.10 10-bit ADC characteristics .................................................................819.3.11 EMC characteristics (85)10 Package information ..........................................................................................8910.1 32-pin LQFP package mechanical data ................................................................... 89 10.2 20-pin TSSOP package mechanical data ................................................................. 90 10.3 20-lead UFQFPN package mechanical data ............................................................9211 Thermal characteristics ......................................................................................9411.1 Reference document ................................................................................................ 94 11.2 Selecting the product temperature range .................................................................9412 Ordering information .......................................................................................... 96 13 STM8 development tools ...................................................................................9713.1 Emulation and in-circuit debugging tools .................................................................. 97 13.2 Software tools ...........................................................................................................97 13.2.1 STM8 toolset ..................................................................................... 98 13.2.2 C and assembly toolchains ...............................................................98 13.3 Programming tools ...................................................................................................9814 Revision history ..................................................................................................99DocID018576 Rev 33/100Table 43. I C characteristics (80)List of tablesSTM8S003K3 STM8S003F3List of tablesT able 1. STM8S003xx value line features ............................................................................................... 8 T able 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ................................. 13 T able 3. TIM timer features ................................................................................................................... 15 T able 4. Legend/abbreviations for pinout tables.................................................................................. 18 T able 5. LQFP32 pin description ........................................................................................................... 19 T able 6. STM8S003F3 pin description .................................................................................................. 22 T able 7. I/O port hardware register map ............................................................................................... 26 T able 8. General hardware register map.............................................................................................. 27 T able 9. CPU/SWIM/debug module/interrupt controller registers........................................................ 36 T able 10. Interrupt mapping .................................................................................................................. 39 T able 11. Option bytes.......................................................................................................................... 99 T able 12. Option byte description .......................................................................................................... 41 T able 13. STM8S003K3 alternate function remapping bits for 32-pin devices ..................................... 43 T able 14. STM8S003F3 alternate function remapping bits for 20-pin devices ..................................... 44 T able 15. Voltage characteristics .......................................................................................................... 47 T able 16. Current characteristics .......................................................................................................... 47 T able 17. Thermal characteristics ......................................................................................................... 48 T able 18. General operating conditions ................................................................................................ 49 T able 19. Operating conditions at power-up/power-down ..................................................................... 50 T able 20. T otal current consumption with code execution in run mode at V DD = 5 V ............................ 51 T able 21. T otal current consumption with code execution in run mode at V DD = 3.3 V ......................... 52 T able 22. T otal current consumption in wait mode at V DD = 5 V ........................................................... 53 T able 23. T otal current consumption in wait mode at V DD = 3.3 V ........................................................ 53 T able 24. T otal current consumption in active halt mode at V DD = 5 V ................................................. 54 T able 25. T otal current consumption in active halt mode at V DD = 3.3 V .............................................. 54 T able 26. T otal current consumption in halt mode at V DD = 5 V ............................................................ 55 T able 27. T otal current consumption in halt mode at V DD = 3.3 V ......................................................... 55 T able 28. Wakeup times ........................................................................................................................ 56 T able 29. T otal current consumption and timing in forced reset state ................................................... 57 T able 30. Peripheral current consumption ............................................................................................ 57 T able 31. HSE user external clock characteristics ................................................................................ 60 T able 32. HSE oscillator characteristics ................................................................................................ 61 T able 33. HSI oscillator characteristics ................................................................................................. 62 T able 34. LSI oscillator characteristics .................................................................................................. 64 T able 35. RAM and hardware registers ................................................................................................. 64 T able 36. Flash program memory and data EEPROM .......................................................................... 65 T able 37. I/O static characteristics ........................................................................................................ 66 T able 38. Output driving current (standard ports) ................................................................................. 68 T able 39. Output driving current (true open drain ports) ....................................................................... 68 T able 40. Output driving current (high sink ports) ................................................................................. 69 T able 41. NRST pin characteristics ....................................................................................................... 74 T able 42. SPI characteristics .................................................................................................................78 2 T able 44. ADC characteristics ............................................................................................................... 82 T able 45. ADC accuracy with R AIN < 10 kΩ , V DD = 5 V........................................................................ 82 T able 46. ADC accuracy with R AIN < 10 kΩ R AIN , V DD = 3.3 V............................................................. 83 T able 47. EMS data ...............................................................................................................................864/100DocID018576 Rev 3STM8S003K3STM8S003F3List of tablesT able48.EMI data (86)T able49.ESD absolute maximum ratings (87)T able50.Electrical sensitivities (88)T able51.32-pin low profile quad flat package mechanical data (89)T able52.20-pin,4.40mm body,0.65mm pitch mechanical data (91)T able53.20-lead ultra thin fine pitch quad flat no-lead package(3x3)mechanical data (92)T able54.Thermal characteristics (94)T able55.Document revision history (99)DocID018576Rev35/100Figure 41. Typical application with I C bus and timing diagram (84)List of figuresSTM8S003K3 STM8S003F3List of figuresFigure 1. Block diagram .......................................................................................................................... 9 Figure 2. Flash memory organization ................................................................................................... 12 Figure 3. STM8S003K3 LQFP32 pinout ............................................................................................... 18 Figure 4. STM8S003F3 TSSOP20 pinout ............................................................................................. 21 Figure 5. STM8S003F3 UFQFPN20-pin pinout .................................................................................... 22 Figure 6. Memory map .......................................................................................................................... 25 Figure 7. Pin loading conditions ............................................................................................................ 46 Figure 8. Pin input voltage .................................................................................................................... 47 Figure 9. f CPUmax versus V DD ............................................................................................................... 50 Figure 10. External capacitor C EXT ...................................................................................................... 50 Figure 11. Typ I DD(RUN) vs. V DD HSE user external clock, f CPU = 16 MHz ............................................ 58 Figure 12. Typ I DD(RUN) vs. f CPU HSE user external clock, V DD = 5 V ................................................... 58 Figure 13. Typ I DD(RUN) vs. V DD HSI RC osc, f CPU = 16 MHz ................................................................ 59 Figure 14. Typ I DD(WFI) vs. V DD HSE user external clock, f CPU = 16 MHz ............................................. 59 Figure 15. Typ I DD(WFI) vs. f CPU HSE user external clock, V DD = 5 V .................................................... 60 Figure 16. Typ I DD(WFI) vs. V DD HSI RC osc, f CPU = 16 MHz ................................................................ 60 Figure 17. HSE external clock source ................................................................................................... 61 Figure 18. HSE oscillator circuit diagram .............................................................................................. 62 Figure 19. Typical HSI frequency variation vs V DD @ 4 temperatures ................................................. 63 Figure 20. Typical LSI frequency variation vs V DD @ 4 temperatures .................................................. 64 Figure 21. Typical V IL and V IH vs V DD @ 4 temperatures ..................................................................... 67 Figure 22. Typical pull-up resistance vs V DD @ 4 temperatures ........................................................... 67 Figure 23. Typical pull-up current vs V DD @ 4 temperatures ................................................................ 68 Figure 24. Typ. V OL @ V DD = 5 V (standard ports) ............................................................................... 70 Figure 25. Typ. V OL @ V DD = 3.3 V (standard ports) ............................................................................ 70 Figure 26. Typ. V OL @ V DD = 5 V (true open drain ports) ..................................................................... 71 Figure 27. Typ. V OL @ V DD = 3.3 V (true open drain ports) .................................................................. 71 Figure 28. Typ. V OL @ V DD = 5 V (high sink ports) ............................................................................... 72 Figure 29. Typ. V OL @ V DD = 3.3 V (high sink ports) ............................................................................ 72 Figure 30. Typ. V DD - V OH @ V DD = 5 V (standard ports) ...................................................................... 73 Figure 31. Typ. V DD - V OH @ V DD = 3.3 V (standard ports) .................................................................. 73 Figure 32. Typ. V DD - V OH @ V DD = 5 V (high sink ports) ...................................................................... 74 Figure 33. Typ. V DD - V OH @ V DD = 3.3 V (high sink ports) ................................................................... 74 Figure 34. Typical NRST V IL and V IH vs V DD @ 4 temperatures .......................................................... 76 Figure 35. Typical NRST pull-up resistance vs V DD @ 4 temperatures ................................................ 76 Figure 36. Typical NRST pull-up current vs V DD @ 4 temperatures ..................................................... 77 Figure 37. Recommended reset pin protection ..................................................................................... 77 Figure 38. SPI timing diagram - slave mode and CPHA = 0 ................................................................. 79 Figure 39. SPI timing diagram - slave mode and CPHA = 1 ................................................................. 79 Figure 40. SPI timing diagram - master mode (1) ..................................................................................80 2 Figure 42. ADC accuracy characteristics .............................................................................................. 84 Figure 43. Typical application with ADC ............................................................................................... 85 Figure 44. 32-pin low profile quad flat package (7 x 7) ......................................................................... 89 Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................. 90 Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ................................... 92 Figure 47. STM8S003x value line ordering information scheme ..........................................................966/100DocID018576 Rev 3· · For informationto the STM8S Flash programming manual (PM0051).internal Flash memory· For information on the protocol and debug module user manual (UM0470). to the STM8· For information on the STM8 core, please refer to the STM8 CPU programming manualSTM8S003K3 STM8S003F3Introduction1IntroductionThis datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).on programming, erasing and protection of the please referdebug and SWIM (single wire interface module) refer SWIM communication(PM0044).DocID018576 Rev 37/100Multipurpose timer (TIM1), SPI, I C, UARTDescription2STM8S003K3 STM8S003F3DescriptionThe STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.Full documentation is offered as well as a wide choice of development tools.Table 1: STM8S003xx value line featuresDevice Pin countMaximum number of GPIOs (I/Os) Ext. interrupt pins Timer CAPCOM channels Timer complementary outputs A/D converter channels High sink I/OsSTM8S003K3 32 28 27 7 3 4 21STM8S003F3 20 16 16 7 2 5 12 Low density Flash program memory (bytes) 8K 8K RAM (bytes)True data EEPROM (bytes) 1K 128 (1)1K 128 (1)2Peripheral setwindow WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)(1) Without read-while-write capability.8/100DocID018576 Rev 3A d d r e s s a n d d a t a b u sSTM8S003K3 STM8S003F3Block diagram3Block diagramFigure 1: Block diagramReset blockClock controllerXTAL 1-16 MHzResetSingle wire debug interf.400 Kbit/s8 Mbit/sResetPORBORSTM8 coreDebug/SWIMI2CSPIDetectorClock to peripherals and coreRC int. 16 MHzRC int. 128 kHzWindow WDGIndependent WDG8-Kbyte program Flash 128-bytedata EEPROM1-KbyteRAMUp to4 CAPCOM channels +3LIN master SPI emul.UART116-bit advanced control timer (TIM1)16-bit general purposetimer (TIM2)complementaryoutputsUp to3 CAPCOMchannels8-bit basic timerUp to 5 channels1/2/4 kHzbeepADC1BeeperDocID018576 Rev 3(TIM4)AWU timer9/100· · Xand read-modify-write type data manipulations addressing modes with or without offset · · Indexed indirect addressing mode for look-up tables located anywhere in the address ·Product overviewSTM8S003K3 STM8S003F344.14.210/100Product overviewThe following section intends to give an overview of the basic features of the device functional modules and peripherals.For more detailed information please refer to the corresponding family reference manual (RM0016).Central processing unit STM8The 8-bit STM8 core is designed for code efficiency and performance.It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.Architecture and registers Harvard architecture· 3-stage pipeline · 32-bit wide program memory bus - single cycle fetching for most instructionsand Y 16-bit index registers - enabling indexed · 8-bit accumulator · 24-bit program counter - 16-Mbyte linear memory space · 16-bit stack pointer - access to a 64 K-level stack · 8-bit condition code register - 7 condition flags for the result of the last instructionAddressing20 addressing modesspace · Stack pointer relative addressing mode for local variables and parameter passingInstruction set80 instructions with 2-byte average instruction size· Standard data movement and logic/arithmetic functions · 8-bit by 8-bit multiplication · 16-bit by 8-bit and 16-bit by 16-bit division · Bit manipulation · Data transfer between stack and accumulator (push/pop) with direct stack access · Data transfer using the X and Y registers or direct memory-to-memory transfersSingle wire interface module (SWIM) and debug module (DM)The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.DocID018576 Rev 3· · 128 bytes ofbyte area EEPROM· ·STM8S003K3 STM8S003F3Product overviewSWIMSingle wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug moduleThe non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.R/W to RAM and peripheral registers in real-time· R/W access to all resources by stalling the CPU · Breakpoints on all program-memory instructions (software breakpoints) · Two advanced breakpoints, 23 predefined configurations4.34.4Interrupt controller· Nested interrupts with three software priority levels · 32 interrupt vectors with hardware priority · Up to 27 external interrupts on 6 vectors including TLI · Trap and reset interruptsFlash program memory and data EEPROM· 8 Kbytes of Flash program single voltage Flash memorytrue data User optionWrite protection (WP)Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, the data EEPROM, and the option bytes.T o perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of the main program memory and data EEPROM, or to reprogram the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: 8 Kbytes minus UBC· User-specific boot code (UBC): Configurable up to 8 KbytesThe UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the bootDocID018576 Rev 311/100。

概要stm8s003f3p6值线8位微控制器具有8KB闪存程序存储器和集成的实数据EEPROM。

stm8s微控制器系列参考手册（rm0016）涉及该系列中的低密度器件。

它们具有以下优点：性能，稳定性和降低的系统成本集成真实数据EEPROM支持以确保设备性能和坚固性采用最先进的技术，多达00000个写入/擦除周期，先进的内核和外围设备16MHz时钟频率，强大的I / O，独立的看门狗时钟源和时钟安全系统由于内部时钟系统的高度集成，降低了系统成本振荡器，看门狗和掉电复位提供完整的文档和广泛的开发工具特性它采用16 MHz先进的stm8核心架构和三级流水线扩展指令集程序存储器：8kbflash；100个数据保留周期后的55c20年●RAM：1KB数据存储器：128字节真数据EEPROM；耐久性高达100000个写入/擦除周期工作电压2.95至5.5V灵活的时钟控制，4个主要时钟源：-低功耗晶体谐振器-外部时钟输入-内部，用户可调16MHz RC-内部低功率128khz RC带时钟监控器的时钟安全系统能源管理：-低功耗模式（等待，活动暂停，暂停）-分别关闭外设时钟永久，低功耗启动和掉电复位●具有32个中断的嵌套中断控制器●在6个向量上最多27个外部中断高级控制计时器：16位，4个Capcom通道，3个互补输出，停滞时间插入和灵活同步●具有3个Capcom通道（IC，OC或PWM）的16位通用定时器●具有8位预分频器的8位基本定时器自动唤醒定时器●窗口看门狗和独立看门狗定时器具有时钟输出的UART用于同步操作，智能卡，IrDA，Lin主模式SPI接口高达8 Mbit / SI2C接口高达400 kbit / S●10位，±1 LSB ADC，多达5个多路复用通道，扫描模式和模拟看门狗采用32引脚封装的高灌点输出（高达21 I / O）用于快速片上编程和非侵入式调试。

航顺HK32F030M 系列◆最大卖点：0.1USD◆内核时钟：ARM-M0 内核32 位最高32M 时钟频率◆供电电压：单电源2.0~3.6V◆片内内存：2KB SRAM、16KKB ROM、512B EEPROM◆主要外设：1 路USART、1 路SPI、1 路I2C、1 个ADC 模块、1 个蜂鸣器模块，无DMA、无RTC◆封装形式: TSSOP20◆替代型号：与国外003 系列硬件兼容，注意国外产品电源范围为2.95~5.5V，注意下载调试口不一样，国外003 为单线调试模式，030M 采用SWD 双线调试模式◆软件环境：软件不能兼容，使用航顺自己得函数库、器件库，支持ST-link\J-link 下载器，支持Keil\IAR 编译软件设计时候参考STM32F030 系列函数库◆离线烧录器：航顺指定厂家烧录器STM8S003 系列◆内核时钟：ARM-M0 内核8 位最高16M 时钟频率航顺的主频快一倍◆供电电压：单电源2.95~5.5V 注意航顺的电源2.0~3.6V（新工艺）◆片内内存：1KB SRAM、8KB ROM、128B EEPROM 航顺的内部容量大一倍◆主要外设：1 路USART、1 路SPI、1 路I2C、1 个10 位ADC 模块，航顺的ADC 位12 位◆软件环境：主要是采用IAR 编译软件，8 位系统，函数库和航顺的030M 完全不同，指令效率不如航顺030M ，总结：航顺的HK32F030M 功能完全可以替代STM32S003, 而且主频比ST32S003 快PWM 可以直接驱动电机，硬件上基本兼容STM8S003 （除了调试口需要调整）, 软件上函数库和S003 完全不一样，需要重新移植，移植也很简单和ST 030 系列的函数库接近（头文件不太一样）函数体基本一样。

航顺HK32F030M 价格比STM8S003 便宜20%（按具体数量申请价格）样品申请：深圳市芯楠科技有限公司。

STM8S使用常用问题汇总==================================================================按外设模块===================================================================== =============================== GPIO/AFIO ========================== ================================== Beep ============================== ===1、STM8S提供一个Beep引脚。

通过简单的配置即可输出1K、2K、4K三种频率信号驱动外部蜂鸣器。

由于默认情况下Beep输出引脚PD4为TIM2_CC1功能，为此我们需要打开“Option Bytes”的AFR7选项。

打开STVP，选择你使用的MCU型号，找到"Option Bytes"标签。

将AFR 7改为"Port D4 Alternate Function ＝Beep"。

菜单栏选择"Program" －> "Current tab"，成功后，即可正常使用B eep输出功能。

================================================================================================= Power/RESET ======================= ==1、STM8S为双电源MCU，外设工作电压为3V～5.5V，内核工作电压为1.8V。

因MCU内部已集成1.8V 低功耗电压(LPVR)调节器，MCU工作仅需提供一个供电电源。

在电源电路设计时，需要注意芯片VCAP引脚上要提供滤波电容，该电容用于对内部1.8V供电滤波，容值不小于470nF为宜，瓷片和Ta电容均可，尽量选择较低ESR(等效串联电阻值)的型号。