FT24C32&64_资料完整版

F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page1Two-Wire Serial EEPROM4K, 8K and 16K (8-bit wide)FEATURES❑Low voltage and low power operations:FT24C04A/08A/16A: V CC = 1.8V to 5.5V❑ Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). ❑ 16 bytes page write mode.❑ Partial page write operation allowed.❑ Internally organized: 512 x 8 (4K), 1024 x 8 (8K), 2048 x 8 (16K). ❑ Standard 2-wire bi-directional serial interface. ❑ Schmitt trigger, filtered inputs for noise protection. ❑ Self-timed Write Cycle (5ms maximum).❑ 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility. ❑ Automatic erase before write operation.❑ Write protect pin for hardware data protection.❑ High reliability: typically 1, 000,000 cycles endurance. ❑ 100 years data retention.❑ Industrial temperature range (-40o C to 85o C).❑Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT-23/TSOT-23 Pb-free packages.DESCRIPTIONThe FT24C04A/08A/16A series are 4,096/8,192/16,384 bits of serial Electrical Erasable andProgrammable Read Only Memory, commonly known as EEPROM. They are organized as 512/1,024/2,048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range (1.8V to 5.5V) devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin FunctionA2, A1, A0 Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-ConnectF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page2All these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0G 8L DIP 8L SOP8L TSSOP W P VCCG ND FT24C04A/08A/16A 5L SOT-23SCL 8L DFN8L M SOP 5L TSO T-23ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40℃ to 85℃ Storage temperature:-50℃ to 125℃Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to thedevice. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality .F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page3PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device.(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL . If left unconnected, they are internally recognized as V IL . FT24C04A has A0 pin as no-connect. FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-connect.(C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can bewired-OR with other open-drain output devices.(D) WRITE PROTECT (WP)The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to V IL . Conversely all programming functions are disabled if WP pin is connected to V IH or V CC . Read operations is not affected by the WP pin’s input level.Table AF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page4Device Chip Select/DeviceAddress Pins UsedNo-Connect Pins Max number of similardevices on the samebusFT24C04A A2, A1 A0 4FT24C08A A2, A1, A0 2 FT24C16A(None)A2, A1, A01MEMORY ORGANIZATIONThe FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.DEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only whenSerial clock SCL is at V IL . Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITIONWith SCL V IH , a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page5(C) STOP CONDITIONWith SCL V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACKF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page6DEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th , 6th and 7th ) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th , 6th and 7th ) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.FT24C04A uses A2 (5th ) and A1 (6th ) device address bits. Only four FT24C04A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used.FT24C08A uses only A2 (5th ) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC , the byte programming will finish and the EEPROM device will return to the STANDBY mode.(B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit aftersending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC , the devices will return to the STANDBY mode.F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page7The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word will be loaded to the 2nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. (C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle.READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th ) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bitand a valid device address word with read/write bit (8th ) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th ) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send the address word. Again the EEPROM willacknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address readinstruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address.laitnedifnoCDMF© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page8F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page9Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICS1.8 V2.5-5.0 V Symbol ParameterMin Max MinMax Unit f SCLClock frequency, SCL 400 1000 kHz t LOW Clock pulse width low1.20.7µst HIGH Clock pulse width high0.4 0.3 µst I Noise suppression time (1) 180 120 ns t AAClock low to data out valid 0.30.90.20.7µs t BUF Time the bus must be free before a new transmission can start (1)1.3 0.5µs t HD.STA START hold time0.6 0.25 µs t SU.STA START set-up time 0.6 0.25 µs t HD.DAT Data in hold time 0 0 µs t SU.DAT Data in set-up time100100nst R Input rise time (1)0.3 0.3 µst F Input fall time (1) 300 100 nst SU.STO STOP set-up time 0.6 0.25 µs t DH Date out hold time 50 50 ns WRWrite cycle time55msEndurance(1)25o C, Page Mode, 3.3V1,000,000Write CyclesNotes: 1. This Parameter is expected by characterization but are not fully screened by test.2. AC Measurement conditions: R L (Connects to Vcc): 1.3K ΩInput Pulse Voltages: 0.3Vcc to 0.7VccInput and output timing reference Voltages: 0.5VccF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page10DC CHARACTERISTICSSymbol Parameter Test ConditionsMin Typical Max Units V CC1 24C A supply V CC1.8 5.5 V I CC Supply read currentV CC @ 5.0V SCL = 400 kHz0.5 1.0 mA I CCSupply write current V CC @ 5.0V SCL = 400 kHz2.03.0 mA I SB1 Supply current V CC @ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supply current V CC @ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supply currentV CC @ 5.0V, V IN = V CC or V SS 0.06 1.0 µA I ILInput leakagecurrentV IN = V CC or V SS 3.0 µA I LOOutput leakagecurrentV IN = V CC or V SS3.0µAV IL Input low level -0.6 V CC x 0.3 V V IHInput high levelV CC x 0.7V CC +0.5 VV OL1 Output low level V CC @ 1.8V, I OL = 0.15 mA0.2 V V OL2 Output low level V CC @ 3.0V, I OL = 2.1 mA0.4VF MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page11ORDERING INFORMATION:Density PackageTemperatureRangeVcc HSF Packaging Ordering CodeRoHSTube FT24C04A-UDR-BDIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C04A-UDG-B Tube FT24C04A-USR-B RoHSTape and Reel FT24C04A-USR-TTube FT24C04A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-USG-TTube FT24C04A-UMR-B RoHS Tape and Reel FT24C04A-UMR-TTube FT24C04A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-UMG-TTube FT24C04A-UTR-B RoHSTape and Reel FT24C04A-UTR-TTube FT24C04A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-UTG-T RoHS Tape and Reel FT24C04A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-ULG-T RoHS Tape and Reel FT24C04A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UPG-T RoHS Tape and Reel FT24C04A-UNR-T 4kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UNG-TRoHS Tube FT24C08A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C08A-UDG-B Tube FT24C08A-USR-B RoHSTape and Reel FT24C08A-USR-TTube FT24C08A-USG-B 8kbitsSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C08A-USG-TD: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8Packaging B: TubeT: Tape and Reel HSF R: RoHS G: GreenU:-40F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page12Density Package TemperatureRangeVcc HSF Packaging Ordering CodeTube FT24C08A-UMR-BRoHSTape and Reel FT24C08A-UMR-TTube FT24C08A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UMG-TTube FT24C08A-UTR-B RoHSTape and Reel FT24C08A-UTR-TTube FT24C08A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UTG-T RoHSTape and Reel FT24C08A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-ULG-T RoHS Tape and Reel FT24C08A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UPG-T RoHS Tape and Reel FT24C08A-UNR-T 8kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UNG-TRoHS Tube FT24C16A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C16A-UDG-B Tube FT24C16A-USR-B RoHSTape and Reel FT24C16A-USR-TTube FT24C16A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-USG-TTube FT24C16A-UMR-B RoHSTape and Reel FT24C16A-UMR-TTube FT24C16A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UMG-TTube FT24C16A-UTR-B RoHS Tape and Reel FT24C16A-UTR-TTube FT24C16A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UTG-T RoHSTape and Reel FT24C16A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-ULG-T RoHS Tape and Reel FT24C16A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-UPG-T RoHS Tape and Reel FT24C16A-UNR-T 16kbitsDFN8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UNG-TF MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page13DIP8 PACKAGE OUTLINEDIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170 A1 0.510 0.020 A2 3.200 3.600 0.126 0.142B 0.380 0.570 0.015 0.022B1 1.524（BSC ） 0.060（BSC ）C 0.204 0.360 0.008 0.014D 9.000 9.400 0.354 0.370E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 e 2.540 (BSC) 0.100（BSC ） L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page14SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC)0.050 (BSC)L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8°F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page15MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 0.820 1.100 0.320 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 e 0.65 (BSC) 0.026 (BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6°F MDCo nf i de nt i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page16TSSOP8 PACKAGE OUTLINEDIMENSIONSDimensions In MillimetersDimensions In Inches SymbolMinMax Min Max D 2.900 3.100 0.114 0.122 E4.3004.5000.1690.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006e 0.65 (BSC) 0.026 (BSC) L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1°7° 1° 7°F MDCo n f i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page17SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e 0.95 (BSC) 0.037 (BSC) e1 1.800 2.000 0.071 0.079 L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 6°F MDCo nf i de nt i a l© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page18TSOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersDimensions In InchesSymbolMin Max Min MaxA 0.700 0.900 0.028 0.035A1 0.000 0.100 0.000 0.004 A2 0.700 0.800 0.028 0.031 b 0.350 0.500 0.014 0.020 c 0.080 0.200 0.003 0.008 D 2.820 3.020 0.111 0.119 E 1.600 1.700 0.063 0.067 E1 2.650 2.950 0.104 0.116 e 0.95 (BSC) 0.037 (BSC) e1 1.90 (BSC) 0.075 (BSC) L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8°F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page19DFN8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersSymbolMinNomMaxA 0.70 0.75 0.80A1 - 0.02 0.05 b 0.18 0.25 0.03 c 0.18 0.20 0.25 D 1.902.00 2.10D2 1.50REF e 0.50BSC Nd 1.50BSC E 2.90 3.00 3.10 E2 1.60REFL 0.30 0.40 0.50 h 0.20 0.25 0.30F MDCo nf i de n t i al© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page20Fremont Micro Devices (SZ) Limited* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication orotherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners.。

© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without noticeDoc. No. 25083-00 12/989-1CAT24C321/322/641/6422AdvancedDoc. No. 25083-00 12/98ABSOLUTE MAXIMUM RATINGS*Temperature Under Bias....................–55°C to +125°C Storage Temperature........................ –65°C to +150°C Voltage on Any Pin withRespect to Ground (1) ..............–2.0V to +V CC + 2.0V V CC with Respect to Ground..................–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)1.0W.................................1.0W Lead Soldering Temperature (10 secs)...............300°C Output Short Circuit Current (2) ..........................100mACOMMENTStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica-tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor-mance and reliability.RELIABILITY CHARACTERISTICSSymbol Parameter Min.Max. Units Reference Test MethodN END (3)Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 T DR (3)Data Retention 100 Years MIL-STD-883, Test Method 1008 V ZAP (3)ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 I LTH (3)(4)Latch-up 100 mAJEDEC Standard 17D.C. OPERATING CHARACTERISTICSV CC = +2.7V to +6.0V, unless otherwise specified.Symbol Parameter Min. Typ. Max. Units Test Conditions I CC Power Supply Current 3mA f SCL = 100 KHzIsbStandby Current40 µAVcc=3.3V50 µA Vcc=5I LI Input Leakage Current 2 µA V IN =G ND or V CC I LO Output Leakage Current10µA V IN =G ND or V CCV IL Input Low Voltage –1 V CC x 0.3 V V IH Input High Voltage V CC x 0.7 V CC + 0.5 VV OLOutput Low Voltage (SDA)0.4 V I OL = 3 mA ,V CC =3.0VLimitsCAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol Test Max.Units Conditions C I/O (3) Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (SCL)6pFV IN = 0VNote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)This parameter is tested initially and after a design or process change that affects the parameter.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.CAT24C321/322/641/6423AdvancedDoc. No. 25083-00 12/98A.C. CHARACTERISTICSV CC =2.7V to 6.0V unless otherwise specified.Output Load is 1 TTL Gate and 100pFRead & Write Cycle Limits SymbolParameterV CC =2.7V - 6V V CC =4.5V - 5.5V Min.Max.Min.Max.Units F SCL Clock Frequency100400kHz T I (1)Noise Suppression Time200200ns Constant at SCL, SDA Inputs t AA SCL Low to SDA Data Out 3.51µs and ACK Outt BUF (1)Time the Bus Must be Free Before 4.7 1.2µs a New Transmission Can Start t HD:STA Start Condition Hold Time 40.6µs t LOW Clock Low Period 4.7 1.2µs t HIGH Clock High Period40.6µs t SU:STA Start Condition Setup Time4.70.6µs (for a Repeated Start Condition)t HD:DAT Data In Hold Time 00ns t SU:DAT Data In Setup Time 5050ns t R (1)SDA and SCL Rise Time 10.3µs t F (1)SDA and SCL Fall Time 300300ns t SU:STO Stop Condition Setup Time 40.6µs t DHData Out Hold Time100100nsPower-Up Timing (1)(2)Symbol ParameterMax.Units t PUR Power-up to Read Operation 1ms t PUWPower-up to Write Operation1msNote:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.Write Cycle Limits Symbol Parameter Min.Typ.Max Units t WRWrite Cycle Time10msThe write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.CAT24C321/322/641/6424AdvancedDoc. No. 25083-00 12/98RESET CIRCUIT CHARACTERISTICSCAT24C321/322/641/6425AdvancedDoc. No. 25083-00 12/98PIN DESCRIPTIONSWP : WRITE PROTECTIf the pin is tied to V CC the entire memory array becomes Write Protected (READ only). When the pin is tied to V SS or left floating normal read/write operations are allowed to the device.SCL : SERIAL CLOCKThe serial clock input clocks all data transferred into or out of the device.RESET/RESET : RESET I/OThese are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition for approximately 200ms. RESET pin must be connected through a pull-down and RESET pin must be connected through a pull-up device.SDA: SERIAL DATA/ADDRESSThe bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. In the 24C321/641, the SDA line is also used as the Watchdog Timer Monitor.Reset Controller DescriptionThe CAT24CXXX provides a precision RESET control-ler that ensures correct system operation during brown-out and power-up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until V CC reaches the V TH threshold and will continue driving the outputs for approximately 200ms (t PURST ) after reaching V TH. After the t PURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when V CC falls below V TH. The RESET outputs will be valid so long as V CC is >1.0V (V RVALID ).The RESET pins are I/Os; therefore, the CAT24CXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 24CXXX will initiate a reset timeout after detecting a high and the RESET input in the 24CXXX will initiate a reset timeout after detecting a low.Watchdog TimerThe Watchdog Timer provides an independent protec-tion for microcontrollers. During a system failure, the CAT24C321/641 will respond with a reset signal after a time-out interval of 1.6 seconds for lack of activity.24CXX1 is designed with the Watchdog Timer feature on the SDA input. For the 24C321/641, if the microcontroller does not toggle the SDA input pin within 1.6 seconds the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watch-dog Timer is cleared by any transition on SDA.As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. 24C322/642does not feature the Watchdog Timer function.DEVICE OPERATIONV CCV RESETCAT24C321/322/641/6426AdvancedDoc. No. 25083-00 12/98Hardware Data ProtectionThe 24CXXX is designed with the following hardware data protection features to provide a high degree of data integrity.(1) The 24CXXX features a WP pin. When WP pin is tied high the entire memory array becomes write protected (read only).(2) The V CC sense provides write protection when V CC falls below the reset threshold value (V TH ). The V CC lock out inhibits writes to the serial EEPROM whenever V CC falls below (power down) V TH or until V CC reaches the reset threshold (power up) V TH .Reset Threshold VoltageFrom the factory the 24CXXX is offered in five different variations of reset threshold voltages. They are 4.50-4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-2.70V. To provide added flexibility to design engineers using this product, the 24CXXX is designed with an additional feature of programming the reset threshold voltage. This allows the user to change the existing reset threshold voltage to one of the other four reset threshold voltages. Once the reset threshold voltage is selected it will not change even after cycling the power,unless the user uses the programmer to change the reset threshold voltage. However, the programming function is available only through third party programmer manufacturers. Please call Catalyst for a list of program-mer manufacturers who support this function.STOPCONDITIONSTARTCONDITIONADDRESSSCLSDAFigure 3. Write Cycle TimingSTART BITSDASTOP BITSCLFigure 4. Start/Stop TimingSCLSDA INSDA OUTFigure 2. Bus TimingCAT24C321/322/641/6427AdvancedDoc. No. 25083-00 12/98ACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVERFigure 5. Acknowledge TimingFigure 6. Slave Address BitsFUNCTIONAL DESCRIPTIONThe CAT24CXXX supports the I 2C Bus data transmis-sion protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re-ceiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24CXXX operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or re-ceiver, but the Master device controls which mode is activated.I 2C BUS PROTOCOLThe features of the I 2C bus protocol are defined as follows:(1) Data transfer may be initiated only when the bus is not busy.(2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.START ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24CXXX monitors the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe Master begins a transmission by sending a START condition. The Master sends the address of the particu-lar slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010.The next three bits are don't care. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write opera-tion is selected.After the Master sends a START condition and the slave address byte, the CAT24CXXX monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24CXXX then performs a Read or Write operation depending on the state of the R/W bit.1010X R/WX XCAT24C321/322/641/6428AdvancedDoc. No. 25083-00 12/98Figure 7. Byte Write TimingFigure 8. Page Write TimingACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24CXXX responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.When the CAT24CXXX begins a READ mode it trans-mits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this ac-knowledge, the CAT24CXXX will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After t he Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the CAT24CXXX. After receiving another acknowledge from the Slave, the Master device trans-mits the data to be written into the addressed memory location. The CAT24CXXX acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe 24CXXX writes up to 32 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31 additional bytes. After each byte has been transmitted, CAT24CXXX will respond with an acknowledge, and internally increment the lower order address bits by one. The high order bits remain un-changed.If the Master transmits more than 32 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwrit-ten.When all 32 bytes are received, and the STOP condi tion has been sent by the Master, the internal program-ming cycle begins. At this point, all received data is written to the CAT24CXXX in a single write cycle.* = Don't care bit for 24C321/322X= Don't care bitA 15–A 8SLAVE ADDRESSSA C KAC KDATAA C KS T O P P BUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS A C K*X X XSLAVE C KC KC KBUS ACTIVITY:MASTERSDA LINES T A BYTE ADDRESS C KS T C K C KC KCAT24C321/322/641/6429AdvancedDoc. No. 25083-00 12/98Figure 9. Immediate Address Read TimingAcknowledge PollingDisabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation,CAT24CXXX initiates the internal write cycle. ACK poll-ing can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24CXXX is still busy with the write operation, no ACK will be returned. If CAT24CXXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.WRITE PROTECTIONThe Write Protection feature allows the user to protect against inadvertent programming of the memory array.If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT24CXXX will accept both slave and byte addresses, but the memory location accessed is protected from program-ming by the device's failure to send an acknowledge after the first byte of data is received.READ OPERATIONSThe READ operation for the CAT24CXXX is initiated in the same manner as the write operation with one excep-tion, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.SCL SDA 8TH BIT STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KBUS ACTIVITY:MASTERSDA LINES T A R T N O A C KDATAS T O P PCAT24C321/322/641/64210AdvancedDoc. No. 25083-00 12/98Figure 10. Selective Read TimingFigure 11. Sequential Read TimingImmediate/Current Address ReadThe CAT24CXXX’s address counter contains the ad-dress of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would ac-cess data from address N+1. If N=E (where E=4095 for 24C321/322 and E=8191 for 24C641/642), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24CXXX receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an ac-knowledge, but will generate a STOP condition.Selective/Random ReadSelective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condi-tion, slave address and byte addresses of the location it wishes to read. After CAT24CXXX acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one.The CAT24CXXX then responds with its acknowledge and sends the 8-bit byte requested. The master deviceSequential ReadThe Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24CXXX sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24CXXX will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from CAT24CXXX is output-ted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24CXXX address bits so that the entire memory array can be read during one operation. If more than E (where E= 4095 for 24C321/322, E=511 and E=8191 for 24C641/642) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes.does not send an acknowledge but will generate a STOP condition.BUS ACTIVITY:MASTERSDA LINEDATA n+xDATA nC KC KDATA n+1C KS T O O A C KDATA n+2C KSLAVE ADDRESS* = Don't care bit for 24C321/322X= Don't care bitA 15–A 8SLAVE ADDRESSSA C KA C KA C KBUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS SLAVEADDRESSSA C KN O A C KS T A R T DATAPS T O P X X X *CAT24C321/322/641/64211Advanced Doc. No. 25083-00 12/98Ordering InformationNote:(1) The device used in the above example is a CAT24C322JI-30TE13 (32K I 2C Memory, SOIC, Industrial Temperature, 3.0-3.15V ResetThreshold Voltage, Tape and Reel)CAT24C321/322/641/64212AdvancedDoc. No. 25083-00 12/98。

2011-04-2916:56:58 分类：LINUXAT24C32是2-WireSerialEEPROM，容量为32Kbits（4096*8）。

利用该芯片可以模拟I2C总线，如果采用IO口来进行模拟，可以采用二线制（SCL、SDA），也可以采用三线制（WP、SCL、SDA）。

在编写驱动程序时，要分为两个层次。

第一、针对IIC总线的驱动部分。

第二、针对AT24C32的驱动部分。

DynamicC里面的IO模拟IIC函数库采用的是二线制，针对的芯片是24C02。

如果要用，就需要进行相应的改进。

下面把使用该芯片时注意的地方总结如下：1、各个引脚的含义A0-A2：地址线，用来选择slave器件。

WP：WriteProtect写保护，高电平拒绝写入，低电平可以写入，即低电平有效。

SCL：SerialClock串行时钟，用来指示什么时候数据线上是有效数据。

SDA：SerialData串行数据，用于数据传送2、关于WP脚二线制没有WP，也就是把WP置为低电平，始终写有效。

这样的问题是，在上电或调电的时候，可能会发生异常情况，对EEPROM内数据有所改动。

所以，如果有重要的数据，还是要采用WP引脚比较安全。

对AT24C32来说，WP置高，则只有四分之一受保护，即0x0C00－0x0FFF。

也就是说保护区为1KBytes。

对于低地址的四分之三，则不保护。

所以，如果数据较多时，可以有选择地存储。

不重要的数据则放在低四分之三区域，重要的数据则放在高四分之一区域。

看ICDatasheet，一定要仔细。

初次写测试程序时，发现WP不起作用，常有效。

用万用表测试，确实是高电平。

经过仔细阅读WP引脚说明，发现只有高四分之一区域可以写保护。

改变地址后，测试成功。

整个驱动函数也就修改成功了。

WP：Thewriteprotectinput,whentiedtoGND,,allwriteoperationstotheupperquand rant(8Kbits),WPisinternallypulleddowntoGND.3、关于读写流程AT24C32的数据地址必须要先发高字节地址，再发低字节地址。

Lenovo ThinkAgile CP Series Cloud PlatformProduct Guide (withdrawn product)Lenovo ThinkAgile CP Series is an all-in-one, composable cloud with an integrated application marketplace and end-to-end automation, delivering a turn-key cloud experience in your own data center. ThinkAgile CP Series uses modular compute, storage, and networking components paired with the cloud virtualization software to create pools of IT resources, independently scaling and allocating capacity, and automatically configuring resources to fulfill application requirements.Due to its software-defined modular architecture, the ThinkAgile CP Series platform can be scaled easily by adding more compute and storage resources independently of each other as your needs grow. Suggested workloads for the ThinkAgile CP Series include web services, virtual desktop infrastructure (VDI), enterprise applications, OLTP and OLAP databases, data analytics, application development, cost-optimized virtualization, containers, and other back-office applications.The following figure shows the ThinkAgile CP Series hardware components.Figure 1. Lenovo ThinkAgile CP Series hardware componentsDid you know?Lenovo professional deployment services are included in ThinkAgile CP Series to get customers up and running quickly. Also included is the ThinkAgile Advantage lifecycle management with a single point of support for the entire ThinkAgile CP platform with the nodes, networking, and software components, for quicker problem determination and minimized downtime.Lenovo offers additional professional services that can be purchased for the ThinkAgile CP Series deployments, including hardware installation, software deployment, workload migration, cloud assessment and design, and ongoing managed services to help achieve optimal operations and performance. ThinkAgile CP is designed to minimize downtime with all of the components engineered to work together, and with tested, standardized and automated code updates.Click here to check for updatesFigure 2. ThinkAgile CP Interconnect port-side viewThe following figure shows the non-port-side view of the ThinkAgile CP Interconnect. Figure 3. ThinkAgile CP Interconnect non-port-side viewThe following figure shows the rear view of the ThinkAgile CP Compute Block.Figure 5. ThinkAgile CP Compute Block rear viewFigure 6. ThinkAgile CP Storage Block front viewThe following figure shows the rear view of the ThinkAgile CP Storage Block.Figure 7. ThinkAgile CP Storage Block rear viewThe following figure shows the port-side view of the RackSwitch G7052.Figure 8. RackSwitch G7052 port-side viewThe following figure shows the non-port-side view of the RackSwitch G7052.Figure 9. RackSwitch G7052 non-port-side viewThe following figure shows the port-side view of the NE0152T RackSwitch.Figure 10. NE0152T RackSwitch port-side viewThe following figure shows the non-port-side view of the NE0152T RackSwitch.Figure 11. NE0152T RackSwitch non-port-side viewSystem specificationsThe following table lists the system specifications of the ThinkAgile CP Series. Table 1. ThinkAgile CP Series system specificationsAttribute SpecificationCP4000CP6000Warranty and support Three-, four-, or five-year customer-replaceable unit and onsite limited hardware warranty with ThinkAgile Advantage Support and selectable service levels: 9x5 next business day (NBD) parts delivered (base warranty), 9x5 NBD onsite response (Foundation Service), 24x7 coverage with 4-hour onsite response or 24-hour committed repair (select areas), (Essential Service), or 2-hour onsite response or 6-hour committed repair (select areas) (Advanced Service). Also available are YourDrive YourData, Premier Support, and Enterprise Software Support.Software Guardian Edition Software for ThinkAgile CP.Figure 12. ThinkAgile CP network connectivity topologyNote: When only one Interconnect is deployed with the CP4000 model, all ports on the Compute Block and Storage Block are connected to the same Interconnect network device.The following table lists the ThinkAgile CP Interconnect model.Table 2. Interconnect for CP SeriesDescription Machine Type/ModelThinkAgile CP Interconnect (CP-I-10)7Y67CTO1WW ThinkAgile CP Interconnect Expansion (CP-I-10E)7Y67CTO2WWConfiguration notes:Table 5. Transceivers and cables for customer network uplinksDescription FeaturecodeMaximum quantityper Interconnect10 GbE SFP+ DAC cables1.5m Passive DAC SFP+ Cable A51N2 2m Passive DAC SFP+ Cable A51P2 3m Passive DAC SFP+ Cable A1PJ2 5m Passive DAC SFP+ Cable A1PK2 7m Passive DAC SFP+ Cable A3RH2 10 GbE SFP+ active optical cablesLenovo 3m SFP+ to SFP+ Active Optical Cable ATYY2 Lenovo 5m SFP+ to SFP+ Active Optical Cable ATYZ2 Lenovo 7m SFP+ to SFP+ Active Optical Cable ATZ02 Lenovo 15m SFP+ to SFP+ Active Optical Cable ATZ12 Lenovo 20m SFP+ to SFP+ Active Optical Cable ATZ22 40 GbE QSFP+ transceivers and optical cablesLenovo 40GBASE-SR4 QSFP+ Transceiver A1DR2 Lenovo 10m QSFP+ MPO-MPO OM3 MMF Cable AT2U2 Lenovo 30m QSFP+ MPO-MPO OM3 MMF Cable AT2V2 40 GbE QSFP+ active optical cablesLenovo 3m QSFP+ to QSFP+ Active Optical Cable ATZ32 Lenovo 5m QSFP+ to QSFP+ Active Optical Cable ATZ42 Lenovo 7m QSFP+ to QSFP+ Active Optical Cable ATZ52 Lenovo 15m QSFP+ to QSFP+ Active Optical Cable ATZ62 Lenovo 20m QSFP+ to QSFP+ Active Optical Cable ATZ72 40 GbE QSFP+ to 4x10 GbE SFP+ active optical breakout cablesLenovo 1m QSFP+ to 4xSFP+ Active Optical Cable ATZ82 Lenovo 3m QSFP+ to 4xSFP+ Active Optical Cable ATZ92 Lenovo 5m QSFP+ to 4xSFP+ Active Optical Cable ATZA2 40 GbE QSFP+ direct-attach copper cablesLenovo 1m Passive QSFP+ DAC Cable A1DP2 Lenovo 3m Passive QSFP+ DAC Cable A1DQ2 Lenovo 5m Passive QSFP+ DAC Cable A2X82 Lenovo 7m Passive QSFP+ DAC Cable A2X92 40 GbE QSFP+ to 4x 10 GbE SFP+ breakout cablesLenovo 1m Passive QSFP+ to SFP+ Breakout DAC Cable A1DL2 Lenovo 3m Passive QSFP+ to SFP+ Breakout DAC Cable A1DM2 Lenovo 5m Passive QSFP+ to SFP+ Breakout DAC Cable A1DN2Intel Xeon Silver 4214 12C 85W 2.2GHz Processor B4HR Intel Xeon Silver 4214Y 12/10/8C 85W 2.2GHz Processor B4NW Intel Xeon Silver 4215 8C 85W 2.5GHz Processor B4HQ Intel Xeon Silver 4216 16C 100W 2.1GHz Processor B4HP Intel Xeon Gold processorsIntel Xeon Gold 5215 10C 85W 2.5GHz Processor B4HN Intel Xeon Gold 5215M 10C 85W 2.5GHz Processor B4P1 Intel Xeon Gold 5215L 10C 85W 2.5GHz Processor B4P9 Intel Xeon Gold 5217 8C 115W 3.0GHz Processor B4HM Intel Xeon Gold 5218 16C 125W 2.3GHz Processor B4HL Intel Xeon Gold 5218B 16C 125W 2.3GHz Processor B6BS Intel Xeon Gold 5218T 16C 105W 2.1GHz Processor B4P3 Intel Xeon Gold 5220 18C 125W 2.2GHz Processor B4HK Intel Xeon Gold 5220S 18C 125W 2.7GHz Processor B6CW Intel Xeon Gold 5220T 18C 105W 1.9GHz Processor B6CQ Intel Xeon Gold 6222V 20C 115W 1.8GHz Processor B6CV Intel Xeon Gold 6226 12C 125W 2.7GHz Processor B6CL Intel Xeon Gold 6230 20C 125W 2.1GHz Processor B4HJ Intel Xeon Gold 6230N 20C 125W 2.3GHz Processor B5RY Intel Xeon Gold 6230T 20C 125W 2.1GHz Processor B6CP Intel Xeon Gold 6234 8C 130W 3.3GHz Processor B6CK Intel Xeon Gold 6238 22C 140W 2.1GHz Processor B6CJ Intel Xeon Gold 6238M 22C 140W 2.1GHz Processor B6CM Intel Xeon Gold 6238L 22C 140W 2.1GHz Processor B6CR Intel Xeon Gold 6238T 22C 125W 1.9GHz Processor B4P2 Intel Xeon Gold 6240 18C 150W 2.6GHz Processor B4HH Intel Xeon Gold 6240M 18C 150W 2.6GHz Processor B6CN Intel Xeon Gold 6240L 18C 150W 2.6GHz Processor B6CS Intel Xeon Gold 6240Y 18/14/8C 150W 2.6GHz Processor B4NV Intel Xeon Gold 6242 16C 150W 2.8GHz Processor B4HG Intel Xeon Gold 6244 8C 150W 3.6GHz Processor B4HF Intel Xeon Gold 6246 12C 165W 3.3GHz Processor B6PD Intel Xeon Gold 6248 20C 150W 2.5GHz Processor B4HE Intel Xeon Gold 6252 24C 150W 2.1GHz Processor B4HC Intel Xeon Gold 6252N 24C 150W 2.3GHz Processor B6CT Intel Xeon Gold 6254 18C 200W 3.1GHz Processor B4HD Intel Xeon Gold 6262V 24C 135W 1.9GHz Processor B6CU Intel Xeon Platinum processorsIntel Xeon Platinum 8253 16C 125W 2.2GHz Processor B5RZ Intel Xeon Platinum 8260 24C 165W 2.4GHz Processor B4HB Intel Xeon Platinum 8260M 24C 165W 2.4GHz Processor B4NZManagement switchThe management network switch is a 1 GbE RJ-45 switch that connects SMM management ports on the Compute Blocks and management ports on the Storage Blocks. The management switch also provides one management uplink to the first Interconnect. The management switch can be purchased from Lenovo or provided by the customer.The following table lists the management switches that are available from Lenovo.Table 13. Management switchesDescription Machine Type-ModelFeaturecode QuantityRackSwitch G7052 (Rear to Front) for ThinkAgile CP7159-HCS B2ZC1 ThinkSystem NE0152T RackSwitch (Rear to Front) for ThinkAgile CP7Y81CTO4WW BAEU1The following tables list cables that are available for selection for the management switch.Table 14. 1 GbE UTP cables for management links to Compute Blocks and Storage BlocksDescription FeaturecodeMaximum quantityper switchQuantity perCompute BlockQuantity perStorage Block0.75m Blue Cat5e Cable AVFT16121.0m Blue Cat5e Cable AVFU1612 1.25m Blue Cat5e Cable AVFV1612 1.5m Blue Cat5e Cable38021612 3m Blue Cat5e Cable38031612 10m Blue Cat5e Cable38041612 25m Blue Cat5e Cable38051612Table 15. 10 GbE SFP+ cables for management uplink to InterconnectDescription FeaturecodeQuantityper switch10 GbE SFP+ DAC cables1.5m Passive DAC SFP+ Cable A51N1 2m Passive DAC SFP+ Cable A51P1 3m Passive DAC SFP+ Cable A1PJ1 5m Passive DAC SFP+ Cable A1PK1 7m Passive DAC SFP+ Cable A3RH1 10 GbE SFP+ active optical cablesLenovo 3m SFP+ to SFP+ Active Optical Cable ATYY1 Lenovo 5m SFP+ to SFP+ Active Optical Cable ATYZ1 Lenovo 7m SFP+ to SFP+ Active Optical Cable ATZ01 Lenovo 15m SFP+ to SFP+ Active Optical Cable ATZ11 Lenovo 20m SFP+ to SFP+ Active Optical Cable ATZ21Power cablesPower cablesThe following table lists the power cable options that can be selected for the ThinkAgile CP Series components. Two power cables are required per each Compute Block, Storage Block, Interconnect, and NE0152T management switch. One power cable is required for the G7052 management switch.Table 16. Power cablesDescription Feature codeRack power cables1.0m, 10A/125-250V, C13 to IEC 320-C14 Rack Power Cable A4VP1.5m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable62012.0m, 13A/125V-10A/250V, C13 to IEC 320-C14 Rack Power Cable6570 2.8m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable6311 2.8m, 13A/125V-10A/250V, C13 to IEC 320-C14 Rack Power Cable6400 2.8m, 10A/100-250V, C13 to IEC 320-C20 Rack Power Cable6204 4.3m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable6263 4.3m, 13A/125V-10A/250V, C13 to IEC 320-C14 Rack Power Cable6583 Line cordsAustralia/New Zealand 2.8m, 10A/250V, C13 to AS/NZS 3112 Line Cord6211 Australia/New Zealand 4.3m, 10A/250V, C13 to AS/NZS 3112 Line Cord6574 Denmark 2.8m, 10A/250V, C13 to DK2-5a Line Cord6213 Denmark 4.3m, 10A/250V, C13 to DK2-5a Line Cord6575 Europe 2.8m, 10A/250V, C13 to CEE7-VII Line Cord6212 Europe 4.3m, 10A/250V, C13 to CEE7-VII Line Cord6572 India 2.8m, 10A/250V, C13 to IS 6538 Line Cord6269 India 4.3m, 10A/250V, C13 to IS 6538 Line Cord6567 Israel 2.8m, 10A/250V, C13 to SI 32 Line Cord6218 Israel 4.3m, 10A/250V, C13 to SI 32 Line Cord6579 Italy 2.8m, 10A/250V, C13 to CEI 23-16 Line Cord6217 Italy 4.3m, 10A/250V, C13 to CEI 23-16 Line Cord6493 South Africa 2.8m, 10A/250V, C13 to SABS 164 Line Cord6214 South Africa 4.3m, 10A/250V, C13 to SABS 164 Line Cord6576 Switzerland 2.8m, 10A/250V, C13 to SEV 1011-S24507 Line Cord6216 Switzerland 4.3m, 10A/250V, C13 to SEV 1011-S24507 Line Cord6578 United Kingdom 2.8m, 10A/250V, C13 to BS 1363/A Line Cord6215 United Kingdom 4.3m, 10A/250V, C13 to BS 1363/A Line Cord6577 United States 2.8m, 10A/250V, C13 to NEMA 6-15P Line Cord A1RF United States 4.3m, 10A/250V, C13 to NEMA 6-15P Line Cord6373Rack cabinetsThe following table lists the rack cabinets that are offered by Lenovo that can be used with the ThinkAgile CP Series.Table 20. Rack cabinetsDescription Part number25U S2 Standard Rack (1000 mm deep; 2 sidewall compartments)93072RX 25U Static S2 Standard Rack (1000 mm deep; 2 sidewall compartments)93072PX 42U S2 Standard Rack (1000 mm deep; 6 sidewall compartments)93074RX 42U 1100mm Enterprise V2 Dynamic Rack (6 sidewall compartments)93634PX 42U 1100mm Enterprise V2 Dynamic Expansion Rack (6 sidewall compartments)93634EX 42U 1200mm Deep Dynamic Rack (6 sidewall compartments)93604PX 42U 1200mm Deep Static Rack (6 sidewall compartments)93614PX 42U Enterprise Rack (1105 mm deep; 4 sidewall compartments)93084PX 42U Enterprise Expansion Rack (1105 mm deep; 4 sidewall compartments)93084EXFor more information, see the list of Product Guides in the Rack Cabinets category:/servers/options/racks#rt=product-guidePower distribution unitsThe following table lists the power distribution units (PDUs) that are offered by Lenovo that can be used with the ThinkAgile CP Series.Table 21. Power distribution unitsDescription Part number0U Basic PDUs0U 36 C13/6 C19 24A/200-240V 1 Phase PDU with NEMA L6-30P line cord00YJ776 0U 36 C13/6 C19 32A/200-240V 1 Phase PDU with IEC60309 332P6 line cord00YJ777 0U 21 C13/12 C19 32A/200-240V/346-415V 3 Phase PDU with IEC60309 532P6 cord00YJ778 0U 21 C13/12 C19 48A/200-240V 3 Phase PDU with IEC60309 460P9 line cord00YJ779 Switched and Monitored PDUs0U 20 C13/4 C19 Switched and Monitored 24A/200-240V/1Ph PDU w/ NEMA L6-30P cord00YJ781 0U 20 C13/4 C19 Switched and Monitored 32A/200-240V/1Ph PDU w/ IEC60309 332P6 cord00YJ780 0U 18 C13/6 C19 Switched and Monitored 32A/200-240/346-415V/3Ph PDU w/ IEC60309 532P6 cord00YJ782 0U 12 C13/12 C19 Switched and Monitored 48A/200-240V/3Ph PDU w/ IEC60309 460P9 cord00YJ783 1U 9 C19/3 C13 Switched and Monitored DPI PDU (without line cord)46M4002 1U 9 C19/3 C13 Switched and Monitored 60A 3Ph PDU with IEC 309 3P+Gnd cord46M4003 1U 12 C13 Switched and Monitored DPI PDU (without line cord)46M4004 1U 12 C13 Switched and Monitored 60A 3 Phase PDU with IEC 309 3P+Gnd line cord46M4005 Ultra Density Enterprise PDUs (9x IEC 320 C13 + 3x IEC 320 C19 outlets)Ultra Density Enterprise C19/C13 PDU Module (without line cord)71762NXUltra Density Enterprise C19/C13 PDU 60A/208V/3ph with IEC 309 3P+Gnd line cord 71763NU C13 Enterprise PDUs (12x IEC 320 C13 outlets)DPI C13 Enterprise PDU+ (without line cord)39M2816DPI Single Phase C13 Enterprise PDU (without line cord)39Y8941C19 Enterprise PDUs (6x IEC 320 C19 outlets)DPI Single Phase C19 Enterprise PDU (without line cord)39Y8948DPI 60A 3 Phase C19 Enterprise PDU with IEC 309 3P+G (208 V) fixed line cord 39Y8923Front-end PDUs (3x IEC 320 C19 outlets)DPI 30amp/250V Front-end PDU with NEMA L6-30P line cord 39Y8939DPI 32amp/250V Front-end PDU with IEC 309 2P+Gnd line cord 39Y8934DPI 60amp/250V Front-end PDU with IEC 309 2P+Gnd line cord 39Y8940DPI 63amp/250V Front-end PDU with IEC 309 2P+Gnd line cord 39Y8935Universal PDUs (7x IEC 320 C13 outlets)DPI Universal 7 C13 PDU (with 2 m IEC 320-C19 to C20 rack power cord)00YE443Line cords for PDUs that ship without a line cord DPI 30a Line Cord (NEMA L6-30P)40K9614DPI 32a Line Cord (IEC 309 P+N+G)40K9612DPI 32a Line Cord (IEC 309 3P+N+G)40K9611DPI 60a Cord (IEC 309 2P+G)40K9615DPI 63a Cord (IEC 309 P+N+G)40K9613DPI Australian/NZ 3112 Line Cord (32A)40K9617DPI Korean 8305 Line Cord (30A)40K9618DescriptionPart number For more information, see the list of Product Guides in the Power Distribution Units category:/servers/options/pdu#rt=product-guideUninterruptible power supply unitsUninterruptible power supply unitsThe following table lists the uninterruptible power supply (UPS) units that are offered by Lenovo that can be used with the ThinkAgile CP Series.Table 22. Uninterruptible power supply unitsDescription Part numberRT1.5kVA 2U Rack or Tower UPS (200-240VAC) (8x IEC 320 C13 10A outlets)55941KX RT2.2kVA 2U Rack or Tower UPS (200-240VAC) (8x IEC 320 C13 10A, 1x C19 16A outlets)55942KX RT3kVA 2U Rack or Tower UPS (200-240VAC) (8x IEC 320 C13 10A, 1x C19 16A outlets)55943KX RT5kVA 3U Rack or Tower UPS (200-240VAC) (8x IEC 320 C13 10A, 2x C19 16A outlets)55945KX RT6kVA 3U Rack or Tower UPS (200-240VAC) (8x IEC 320 C13 10A, 2x C19 16A outlets)55946KX RT8kVA 6U Rack or Tower UPS (200-240VAC) (4x IEC 320-C19 16A outlets)55948KX RT11kVA 6U Rack or Tower UPS (200-240VAC) (4x IEC 320-C19 16A outlets)55949KX RT8kVA 6U 3:1 Phase Rack or Tower UPS (380-415VAC) (4x IEC 320-C19 16A outlets)55948PX RT11kVA 6U 3:1 Phase Rack or Tower UPS (380-415VAC) (4x IEC 320-C19 16A outlets)55949PXFor more information, see the list of Product Guides in the Uninterruptible Power Supply Units category: /servers/options/ups#rt=product-guideLenovo Financial ServicesLenovo Financial Services reinforces Lenovo’s commitment to deliver pioneering products and services that are recognized for their quality, excellence, and trustworthiness. Lenovo Financial Services offers financing solutions and services that complement your technology solution anywhere in the world.We are dedicated to delivering a positive finance experience for customers like you who want to maximize your purchase power by obtaining the technology you need today, protect against technology obsolescence, and preserve your capital for other uses.We work with businesses, non-profit organizations, governments and educational institutions to finance their entire technology solution. We focus on making it easy to do business with us. Our highly experienced team of finance professionals operates in a work culture that emphasizes the importance of providing outstanding customer service. Our systems, processes and flexible policies support our goal of providing customers with a positive experience.We finance your entire solution. Unlike others, we allow you to bundle everything you need from hardware and software to service contracts, installation costs, training fees, and sales tax. If you decide weeks or months later to add to your solution, we can consolidate everything into a single invoice.Our Premier Client services provide large accounts with special handling services to ensure these complex transactions are serviced properly. As a premier client, you have a dedicated finance specialist who manages your account through its life, from first invoice through asset return or purchase. This specialist develops an in-depth understanding of your invoice and payment requirements. For you, this dedication provides a high-quality, easy, and positive financing experience.For your region-specific offers please ask your Lenovo sales representative or your technology provider about the use of Lenovo Financial Services. For more information, see the following Lenovo website:Related publications and linksTrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®Lenovo ServicesRackSwitchThinkAgile®ThinkSystem®TruDDR4XClarity®The following terms are trademarks of other companies:Intel® and Xeon® are trademarks of Intel Corporation or its subsidiaries.Linux® is the trademark of Linus Torvalds in the U.S. and other countries.Microsoft® is a trademark of Microsoft Corporation in the United States, other countries, or both.Other company, product, or service names may be trademarks or service marks of others.Lenovo ThinkAgile CP Series Cloud Platform (withdrawn product)31。

All-in-One 0.72° Stepper MotorBuilt-in Controller Type PKA SeriesThis all-in-one 0.72° stepper motor features a built-incontroller (stored data) type, microstepping driver andhigh performance motor integrated into one compactpackage.There is no wiring needed between the controller,driver and motor, providing easy motion control of thehigh performance 0.72° stepper motor.There are three control methods that can be selected,I/O, Modbus (RTU)/RS-485 or Factory Automation (FA)Network.The controller and driver are integrated onto the 0.72º highperformance stepper motor. Since there is a built-in controllerthere is no need for a pulse generator. The system is simplified andrequires less wiring.By combining the high performance motor with a built-inmicrostepping driver and stored data controller, superior noise andvibration reduction can be easily achieved.Comparison of Vibration Characteristics2.01.61.20.80.4Speed [r/min]VibrationComponentVoltageVp-p[V]All-in-One Simplifies Motion ControlAdvantages of the All-in-One High Performance 0.72° Stepper MotorBuilt-in Controller (Stored Data) TypeDriver and ControllerMotorA positioning function is built-in, ensuring that the traveling amount, speed and other operating data is retained in the motor. It is also equipped with a variety of other operation functions in addition to the positioning operation, such as continuous operation and a return-to-home operation. This contributes to a reduced load on the programmable controller and a simplified program.All-in-One 0.72º Stepper MotorReduces the Burden on the Master ControllerPositioning Operation●The motor's operating speed and traveling amount are set in the operating data and operations are performed in accordance with the selected operating data.Linked Operation◇If the operating data is set to "linked", continuous positioning with the following data number is possible with one START signal.If data No. 01 is selected and the START input, the data No. 01 operation is executed. After that, it is stopped for only the set dwell time ✽ and then the operations from data No. 02 to No. 03 are executed. Operating data with a different rotation direction can also be linked.✽ Dwell time is the wait time until the nextpositioning operation starts.If data No. 01 is selected and the START input, linked driving from data No. 01 to No. 03 is performed without the motor stopping.Sequential Operation◇If the operating data is set to "sequential positioning", positioning of the next data number is performed in sequence every time a SSTART signal is input.I/OProgrammable ControllerThe positioning module (pulse generator) function is built-in to the driver, allowing theoperation to use I/O by directly connecting to a switch box or PLC. Because apositioning module is not necessary on the PLC side, space is saved and the system is simplified.Modbus (RTU)/RS-485Programmable ControllerComputerorOperating data and parameters can be set and operation commands can be input using RS-485 communication. Up to 31 drivers can be connected to each serial communication module. Also, there is a function that enables the simultaneous start of multiple axes. The protocol supports Modbus (RTU), enabling connection with devices such as touch screen (HMI) and PCs.Factory Automation (FA) NetworkUse of a network converter (sold separately)✽2 enables support with CC-Link, MECHATROLINK or EtherCAT communication. Operating data and parameters can be set and operationcommands can be input using various communication methods.Network Converter NETC01-CC (Sold separately)NETC01-M2 (Sold separately)NETC01-M3 (Sold separately)NETC01-ECT (Sold separately)Programmable Controller 2 A network converter converts✽various network protocols to the RS-485 communication protocol used in Oriental Motor products.Speed Control Operation●The motor operates continuously while a FWD signal or RVS signal is input. Because it operates at the speed of the operating data set beforehand, multistep speed-change operation is possible by changing the data number.FWD inputRVS input M0∼M5 inputMotor operationON OFF ON OFF ON OFF+Direction −DirectionReturn-To-Home Operation●Equipped with a sequence for return-to-home operation thatreduces the burden of the host (master controller) and the hassle of combining programs or sequences. A separate sensor is required.Touch Screen or Computer③FA Network② RS-485① I/O ② Modbus (RTU)② Modbus (RTU)CC-LinkMECHATROLINK-MECHATROLINK-EtherCATSystem Configuration■Example of System Configuration●The system configuration shown above is an example. Other combinations are also available.●Product Line■ 1 ✽Not supplied.2 ✽This is required for driving I/O control.3 ✽Compatible software can be downloaded from the Oriental Motor website.4 For details, please contact the nearest Oriental Motor sales office.✽N etwork ConverterSpecifications ■Speed – Torque Characteristics■PKA544KDPKA566KD0(0)10(100)5(50)15(150)Pulse Speed [kHz]Resolution: 500(Resolution: 5000)Speed [r/min]Current: 0.75 A/Phase Step Angle: 0.72˚/stepExternal Load Inertia: JL=0 kg·m (0 oz-in )T o r q u e [N ·m ]12C u r r e n t [A ]510152025T o r q u e [o z -i n]0(0)5(50)2.5(25)7.5(75)Speed [r/min]Pulse Speed [kHz]Resolution: 500(Resolution: 5000)Current: 1.4 A/Phase Step Angle: 0.72˚/step External Load Inertia: JL=0 kg·m (0 oz-in )T o r q u e [N ·m ] 024C u r r en t [A ]08012016040T o r q u e [o z -i n ]NoteDepending on the driving conditions, a considerable amount of heat may be generated by the motor. Be sure to keep the motor case temperature at 75˚C (167˚F) max.●Control Circuit Specifications■No. of Positioning Data Sets 64Operation FunctionsPositioning operation, return-to-home operation, continuous operation, JOG operation, test operationControl Circuit RS-485 Communication Specification■ProtocolModbus protocol (Modbus RTU mode)Electrical CharacteristicsEIA-485 complianceTwisted-pair wire (TIA/EIA-568B CAT5e or greater recommended) is used up to a total extension length of 50 m (164 ft.).Sending and Receiving Method Half-duplex communication Baud Rate 9600 bps/19200 bps/38400 bps/57600 bps/115200 bps Physical Layer Start-stop synchronization method (data: 8-bit, stop bit: 1-bit/2-bit, parity: none/odd/even)Connection Type Up to 31 units can be connected to one programmable controller (master controller).General Specifications■1 This value is for full step under no load. (The value changes with the size of the load.)✽2 Radial Play: Displacement in shaft position in the radial direction, when a 5 N (1.12 lb.) load is applied in the vertical direction to the tip of the motor's✽shaft.3 Axial Play: Displacement in shaft position in the axial direction, when a 10 N (2.2 lb.) load is applied to the motor shaft in the axial direction.✽4 T. I. R. (Total Indicator Reading): The total dial gauge reading when the measurement section is rotated one revolution centered on the reference axis✽center.Permissible Overhung Load and Permissible Thrust Load■Dimensions■Unit mm (in.)Motor●Frame Size 60 mm (2.36 in.)Connection Cable (Included)●Connection and Operation■Names and Function of Parts●Axis Setting Switch (SW2)Signal Monitor DisplayBaud Rate Setting Switch (SW3)Power Supply & I/O SignalConnector (CN1)RS-485 Communication Connector (CN2, 3)Control Module Connector (CN4)Signal Monitor Display LED Indicator◇Function Switch (SW1)Settings for RS-485 Communication Protocol◇Axis Setting Switch (SW2)Baud Rate Setting Switch (SW3)RS-485 Baud Rate Setting◇Power Supply & I/O Signal Connector (CN1)Sets the function to be assigned according to the parameter setting. The initial values are shown above. For details, refer to the User's Manual.✽The following input signals can be assigned to input terminals IN0∼3.1: FWD 9: MS124: ALM-RST 37: R545: R1353: M52: RVS 10: MS225: P-PRESET 38: R646: R1460: +LS 3: HOME 11: MS327: HMI 39: R747: R1561: −LS 4: START 12: MS432: R040: R848: M062: HOMES 5: SSTART 13: MS533: R141: R949: M163: SLIT6: +JOG 16: FREE 34: R242: R1050: M27: −JOG17: AWO35: R343: R1151: M31: FWD_R 10: MS2_R 34: R243: R1152: M4_R 68: MOVE 2: RVS_R 11: MS3_R 35: R344: R1253: M5_R 70: HOME-P 3: HOME_R 12: MS4_R 36: R445: R1360: +LS_R 72: TIM 4: START_R 13: MS5_R 37: R546: R1461: −LS_R 73: AREA15: SSTART_R 16: FREE_R 38: R647: R1562: HOMES_R 74: AREA26: +JOG_R 17: AWO_R 39: R748: M0_R 63: SLIT_R 75: AREA37: −JOG_R 18: STOP_R 40: R849: M1_R 65: ALM 80: S-BSY8: MS0_R32: R041: R950: M2_R66: WNGConnection Diagram●Connection to Programmable Controller◇Example of Connection with Current Sink Output Circuit (NPN specification)●Example of Connection with Current Source Output Circuit (PNP specification)●NotesUse 24 VDC for the input signals.●U se 24 VDC 10 mA max. for the output signals. When the current value exceeds 10 mA, connect the external resistor R to keep the current 10 mA max. ●If noise generated by the power supply cable causes a problem with the specific wiring or layout, shield the cable or use ferrite cores.●Control Module CableThis is a cable that connects an OPX-2A or data setting software communication cable to the PKA Series.Product Line■Dimensions■unit mm (in.)Accessories (Sold separately)These accessories are necessary to change operating data such as parameter settings and data settings in the PKA Series.Data Setting Software Communication CableThis communication cable is required for connecting to the computer on which the data setting software is installed.Product Line■orControl ModulePerform operations such as setting the driver's internal parameters and setting or changing the data. It can also be used for operations such as speed and I/O monitoring and teaching.Product Line■Specifications■IndicationLEDCable Length5 m (16.4 ft.)Operating Ambient Temperature0∼40˚C (+32∼+104˚F) (non-freezing)<Enlarged view>Dimensions■Unit mm (in.)Control Module●Mass: 0.25 kg (0.55 lb.)B453Panel Cut-Out for ●Controller Module[Installation Plate Thickness 1∼3 mm (0.04∼0.12 in.)]3.6220920 +0.8+0.031680 +0.7( (2.677 +0.0280))RS-485 Communication CableThis is an RS-485 communication cable.Product Line■Dimensions■unit mm (in.)CC020-RS4ACC020-RS4BOperating Environment■Operating System (OS)●Microsoft Windows 2000 Professional Service Pack 4●Be sure to install Rollup 1 provided by Microsoft Corporation. Check whether Rollup 1 has been installed in "Add or Remove Programs".For the following operating systems, both the 32-bit (x86) edition and 64-bit (x64) edition are supported.Microsoft Windows XP Home Edition Service Pack 3●Microsoft Windows XP Professional Service Pack 2●Microsoft Windows XP Professional Service Pack 3●✽1Microsoft Windows Vista Home Basic Service Pack 2●Microsoft Windows Vista Home Premium Service Pack 2●Microsoft Windows Vista Business Service Pack 2●Microsoft Windows Vista Ultimate Service Pack 2●Microsoft Windows Vista Enterprise Service Pack 2●Microsoft Windows 7 Starter Service Pack 1●Microsoft Windows 7 Home Premium Service Pack 1●Microsoft Windows 7 Professional Service Pack 1●Microsoft Windows 7 Ultimate Service Pack 1●Microsoft Windows 7 Enterprise Service Pack 1● 1 32-bit (x86) version only✽CC020-RS4ACC020-RS4BConnection Example●PC●Recommended CPU ✽2Intel Core processor 2 GHz min.(Must be compatible with OS)DisplayVideo adapter and monitor with resolution of XGA (1024 × 768) min.Recommended Memory ✽232-bit version (x86): 1 GB min.64-bit version (x64): 2 GB min.Hard Disk ✽3Free disk space of 30 MB B Port USB 1.1 1 PortDisk DeviceCD-ROM Drive (Used for installation)2 The operating conditions of the OS must be satisfied.✽3 Microsoft .NET Framework 2.0 Service Pack 2 is required for ✽MEXE02. If it is notinstalled, it will be installed automatically. An additional max. of 500 MB of free space may be required.NotesThe required memory and hard disk space may vary depending on the system environment. ●Windows and Windows Vista are registered trademarks of the Microsoft Corporation in the ●United States and other countries.Data Setting Software■MEXE02The data setting software can be downloaded from the Oriental Motor website. For details, please go to the Oriental Motor website or contact the nearest Oriental Motor sales office.A network converter converts from the hostcommunication protocols to Oriental Motor's own RS-485 communication protocol. Use the network converter to control products supporting Oriental Motor's RS-485 compatible products in the host communication environment.Features■Reduced Wiring and Space Saving is Possible●Only the one included cable is needed for the wiring when connecting to an RS-485-compatible product.Setting Method for Various Parameters●A control module OPX-2A (sold separately) or data setting software MEXE02 is required for setting a network converter.A control module OPX-2A and data setting software MEXE02 can also be used to monitor the time it takes to communicate with each axis.Multi-axis Connection is Possible●RS-485-compatible products can be connected on multiple -Link-compatible: 12 axes max.●MECHATROLINK-●-compatible: 16 axes max.MECHATROLINK-●-compatible: 16 axes max.EtherCAT-compatible: 16 axes max.●Product Line■The following items are included in each product.Network converter, RS-485 communication cable, power supply connector, operatingmanual, CC-Link communication connector (NETC01-CC only)Related Products (Sold separately)Network ConverterNETC01-CCNETC01-M2NETC01-M3NETC01-ECTCopyright ©2013 ORIENTAL MOTOR U.S.A. CORP .Printed in USA 13S #419Specifications are subject to change without notice. This catalog was published in May, 2013.ORIENTAL MOTOR U.S.A. CORP .Western Sales andCustomer Service Center Tel: (310) 715-3301 Fax: (310) 225-2594Los AngelesTel: (310) 715-3301San JoseTel: (408) 392-9735Midwest Sales andCustomer Service Center Tel: (847) 871-5900 Fax: (847) 472-2623ChicagoTel: (847) 871-5900DallasTel: (214) 432-3386TorontoTel: (905) 502-5333Eastern Sales andCustomer Service Center Tel: (781) 848-2426 Fax: (781) 848-2617BostonTel: (781) 848-2426CharlotteTel: (704) 766-1335New YorkTel: (973) 359-1100Technical SupportTel: (800) 468-3982 / 8:30 A.M. to 5:00 P .M., P .S.T. (M–F)7:30 A.M. to 5:00 P .M., C.S.T. (M–F)E-mail:*****************************Obtain Specifications, Online Training and Purchase Products at:。

滚动轴承一、选择题11-1．滚动轴承代号由前置代号、基本代号和后置代号组成，其中基本代号表示_______。

A．轴承的类型、结构和尺寸 B. 轴承组件C．轴承内部结构变化和轴承公差等级 D. 轴承游隙和配置11-2．滚动轴承的类型代号由________表示。

A．数字B．数字或字母C. 字母D. 数字加字母11-3．________只能承受径向载荷。

A．深沟球轴承 B. 调心球轴承C. 圆锥滚子轴承D. 圆柱滚子轴承11-4．________ 只能承受轴向载荷。

A．圆锥滚子轴承 B. 推力球轴承C. 滚针轴承D. 调心滚子轴承11-5．________ 不能用来同时承受径向载荷和轴向载荷。

A. 深沟球轴承B. 角接触球轴承C. 圆柱滚子轴承11-6．角接触轴承承受轴向载荷的能力，随接触角α的增大而________。

A．增大 B.减小C．不变D．不定11-7．有a）7230C和b）7230AC两种滚动轴承，在相等的径向载荷作用下，它们的派生轴向力Sa和Sb相比较，应是________。

A．Sa ＞Sb B．Sa = SbC．Sa ＜Sb D．大小不能确定11-8．若转轴在载荷作用下弯曲变形较大或轴承座孔不能保证良好的同轴度，宜选用类型代号为________的轴承。

A．1或2 B．3或7C．N或NU D．6或NA11-9．一根用来传递转矩的长轴，采用三个固定在水泥基础上支点支承，各支点应选用的轴承类型为________。

A. 深沟球轴承B. 调心球轴承C. 圆柱滚子轴承D. 调心滚子轴承11-10．跨距较大并承受较大径向载荷的起重机卷筒轴轴承应选用________ 。

A. 深沟球轴承C. 调心滚子轴承D. 圆柱滚子轴承11-11．________ 轴承通常应成对使用。

A．深沟球轴承 B. 圆锥滚子轴承C. 推力球轴承D. 圆柱滚子轴承11-12．在正常转动条件下工作，滚动轴承的主要失效形式为________。

FM24CXX产品基本介绍以及应用领域概述（共2页）首先，简单介绍一下什么是EEPROM：EEPROM(Electrically Erasable Programmable Read一Only Memory)即电子擦除式只读存储器，它是一种非挥发性存储器，与擦除式只读存储器(EPROM)类似，电源消失后，储存的数据依然存在，要消除储存在其中的内容，不是用紫外线照射方式，而是以电子信号直接消除即可。

正是由于EEPROM具有以上特点，该器件可广泛应用于对数据存储安全性及可靠性要求高的应用场合，如门禁考勤系统，测量和医疗仪表，非接触式智能卡，税控收款机，预付费电度表或复费率电度表、水表、煤气表以及家电遥控器等应用场合。

该类型存储器在可靠数据存储领域会获得越来越广泛的应用。

但是，EEPROM有固定的使用寿命，这是指某一位由1写为O或由O写为1的次数。

不同厂家的产品，相同厂家不同型号、系列的产品，它们的寿命也不尽相同，100万次为常见主流产品。

24CXX系列在EEPROM产品中的位置：最常见的EEPROM有2线制串行EEPROM，3线制串行EEPROM，也有并行EEPROM。

在2线制串行EEPROM中又有适应不同总线的产品系列，其中24CXX是适用用于IIC总线的两线制串行EEPROM。

I2C(Inter－Integrated Circuit)总线是一种由PHILIPS公司开发的两线式串行总线，用于连接微控制器及其外围设备。

I2C总线产生于在80年代，最初为音频和视频设备开发，如今的应用领域涉及几乎所有有小容量字节存储需求的电子产品方案。

譬如每年在深圳就有IIC器件全球峰会，可见IIC器件的大量应用是将来通用类电子产品方案设计的首选。

I2C总线最主要的优点是其简单性和有效性。

由于接口直接在组件之上，因此I2C总线占用的空间非常小，减少了电路板的空间和芯片管脚的数量，降低了互联成本。

总线的长度可高达25英尺，并且能够以10Kbps的最大传输速率支持40个组件。

FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMInterface24IICFM Fairchild Non-VolatileMemoryFM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMFM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMBackground Information (IIC Bus) Extended IIC specification is an extension of Standard IIC speci-fication to allow addressing of EEPROMs with more than 16Kbits of memory on an IIC bus. The difference between the two specifications is that Extended IIC specification defines two bytes of “Array Address” information while Standard IIC specification defines only one. All other aspects are identical between the two specifications. Using two bytes of Array Address and 3 address signals (A2, A1 and A0), it is now possible to address up to 4 Mbits (28 * 28 * 23 * 8 = 4 Mbits) of memory on an IIC bus.Note that due to format difference, it is not possible to have peripherals which follow Standard IIC specification (e.g. 16K bit EEPROM) and peripherals which follow Extended IIC specifica-tion (e.g. 32K bit EEPROM) on a common IIC bus.IIC bus allows synchronous bi-directional communication be-tween a TRANSMITTER and a RECEIVER using a Clock signal (SCL) and a Data signal (SDA). Additionally there are up to three Address signals (A2, A1 and A0) which collectively serve as “chip select signal” to a device (e.g. EEPROM) on the bus.All communication on the IIC bus must be started with a valid START condition (by a MASTER), followed by transmittal (by the MASTER) of byte(s) of information (Address/Data). For every byte of information received, the addressed RECEIVER provides a valid ACKNOWLEDGE pulse to further continue the communi-cation unless the RECEIVER intends to discontinue the commu-nication. Depending on the direction of transfer (Write or Read), the RECEIVER can be a SLAVE or the MASTER. A typical IIC communication concludes with a STOP condition (by the MAS-TER).Addressing an EEPROM memory location involves sending a command string with the following information:[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W BIT]—[ARRAY ADDRESS#1]—[ARRAY ADDRESS#0] Slave AddressSlave Address is an 8-bit information consisting of a Device type field (4bits), Device/Page block selection field (3bits) and Read/ Write bit (1bit).Slave Address Format Device TypeIIC bus is designed to support a variety of devices such as RAMs, EPROMs etc., along with EEPROMS. Hence to properly identify various devices on the IIC bus, a 4-bit “Device Type” identifier string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC device on the bus internally compares this 4-bit string to its own “Device Type” string to ensure proper device selection. Device/Page Block SelectionWhen multiple devices of the same type (e.g. multiple EEPROMS) are present on the IIC bus, then the A2, A1 and A0 address information bits are used in device selection. Every IIC device on the bus internally compares this 3-bit string to its own physical configuration (A2, A1 and A0 pins) to ensure proper device selection. This comparison is in addition to the “D evice Type”comparison.In addition to selecting an EEPROM, these 3 bits are also used to select a “page block” within the selected EEPROM. Each page block is 512Kbit (64 K Bytes) in size. If an EEPROM contains more than one page bock then the selection of a page block within the EEPROM is by using A2, A1 and A0 bits.Read/Write BitLast bit of the Slave Address indicates if the intended access is Read or Write. If the bit is "1," then the access is Read, whereas if the bit is "0," then the access is Write.AcknowledgeAcknowledge is an active LOW pulse on the SDA line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. The receiver provides an ACK pulse for every 8-bits of data received. This handshake mechanism is done as follows: After transmitting 8-bits of data, the transmitter re-leases the SDA line and waits for the ACK pulse. The addressed receiver, if present, drives the ACK pulse on the SDA line during the 9th clock and releases the SDA line back (to the transmitter). Refer Figure 3.Array Address#1This is an 8-bit information containing the most significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device.Array Address#0This is an 8-bit information containing the least significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device.Device Type Identifier Device/Page BlockSelection1010A2A1A0R/W(LSB)FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMPin DescriptionsSerial Clock (SCL)The SCL input is used to clock all data into and out of the device. Serial Data (SDA)SDA is a bi-directional pin used to transfer data into and out of the device. It is an open drain output and may be wire–ORed with any number of open drain or open collector outputs.Write Protect (WP)If tied to V CC, PROGRAM operations onto the upper half (upper 16Kbits) of the memory will not be executed. READ operations are possible. If tied to V SS, normal operation is enabled, READ/ WRITE over the entire memory is possible.This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged.This pin has an internal pull-down circuit. However, on systems where write protection is not required it is recommended that this pin is tied to V SS.Device Selection Inputs A2, A1 and A0 (as appropriate)These inputs collectively serve as “chip select” signal to an EEPROM when multiple EEPROMs are present on the same IIC bus. Hence these inputs should be connected to V CC or V SS in a unique manner to allow proper selection of an EEPROM amongst multiple EEPROMs. During a typical addressing sequence, every EEPROM on the IIC bus compares the configuration of these inputs to the respective 3 bit “D evice/Page block selection”information (part of slave address) to determine a valid selection. For e.g. if the 3 bit “Device/Page block selection” is 1-0-1, then the EEPROM whose “Device Selection inputs” (A2, A1 and A0) are connected to V CC-V SS-V CC respectively, is selected.Device OperationThe FM24C32U supports a bi-directional bus oriented protocol.The protocol defines any device that sends data onto the bus asa transmitter and the receiving device as the receiver. The devicecontrolling the transfer is the master and the device that iscontrolled is the slave. The master will always initiate datatransfers and provide the clock for both transmit and receive operations. Therefore, the FM24C32U will be considered a slavein all applications.Clock and Data ConventionsData states on the SDA line can change only during SCL LOW.SDA state changes during SCL HIGH are reserved for indicatingstart and stop conditions. Refer Figure 1.Start ConditionAll commands are preceded by the start condition, which is aHIGH to LOW transition of SD A when SCL is HIGH. The FM24C32U continuously monitors the SDA and SCL lines for the start condi-tion and will not respond to any command until this condition hasbeen met. Refer Figure 2.Stop ConditionAll communications are terminated by a stop condition, which is aLOW to HIGH transition of SDA when SCL is HIGH. The stopcondition is also used by the FM24C32U to place the device in thestandby power mode. Refer Figure 2.FM24C32U Array AddressingDuring Read/Write operations, addressing the EEPROM memoryarray involves in providing 2 address bytes, “Word Address 1” and“Word Address 0." However on FM24C32U only the 4 leastsignificant bits (LSB) of “Word Address 1” byte are used indecoding the access location. The remaining 4 bits are not usedand are recommended to be set to “0”. All 8 bits of the “WordAddress 0” byte are used in decoding the access location.FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMFM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMFM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROMFM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM。

Two-Wire Serial EEPROM4K, 8K and 16K (8-bit wide)FEATURES❑Low voltage and low power operations:FT24C04A/08A/16A: V CC = 1.8V to 5.5V❑Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).❑16 bytes page write mode.❑Partial page write operation allowed.❑Internally organized: 512 x 8 (4K), 1024 x 8 (8K), 2048 x 8 (16K).❑Standard 2-wire bi-directional serial interface.❑Schmitt trigger, filtered inputs for noise protection.❑Self-timed Write Cycle (5ms maximum).❑ 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.❑Automatic erase before write operation.❑Write protect pin for hardware data protection.❑High reliability: typically 1, 000,000 cycles endurance.❑100 years data retention.❑Industrial temperature range (-40o C to 85o C).❑Standard 8-lead DIP/SOP/MSOP/TSSOP/DFN and 5-lead SOT-23/TSOT-23 Pb-free packages. DESCRIPTIONThe FT24C04A/08A/16A series are 4,096/8,192/16,384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 512/1,024/2,048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-23/TSOT-23packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range(1.8V to 5.5V)devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin FunctionA2, A1, A0 Device Address InputsSDA Serial Data Input / Open Drain OutputSCL Serial Clock InputWP Write ProtectNo-ConnectNC© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page1© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page2All these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0G 8L DIP 8L SOP8L TSSOP W P VCCG ND FT24C04A/08A/16A 5L SOT-23SCL 8L DFN8L M SOP 5L TSO T-23ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40℃ to 85℃ Storage temperature:-50℃ to 125℃Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality .PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of thisclock is to clock data out of the EEPROM device.(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL. If left unconnected, they are internally recognized as V IL. FT24C04A has A0 pin as no-connect. FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-connect.(C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices.(D) WRITE PROTECT (WP)The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.Programming operations are allowed if WP pin is left un-connected or input to V IL. Conversely all programming functions are disabled if WP pin is connected to V IH or V CC. Read operations is not affected by the WP pin’s input level.Table A© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page3Device Chip Select/DeviceAddress Pins UsedNo-Connect PinsMax number of similardevices on the samebusFT24C04A A2,A1 A0 4 FT24C08A A2, A1,A0 2 FT24C16A (None) A2, A1, A0 1MEMORY ORGANIZATIONThe FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.DEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at V IL. Any SDA signal transition may interpret as either a START or STOP condition as described below.(B) START CONDITIONWith SCL V IH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page4© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page5(C) STOP CONDITIONWith SCL V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACKDEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.FT24C04A uses A2 (5th) and A1 (6th) device address bits. Only four FT24C04A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b). Chip select address pin A0 is not used.FT24C08A uses only A2 (5th) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a properEEPROM device address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC, the byte programming will finish and the EEPROM device will return to the STANDBY mode.(B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmedalong the same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle.This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC, the devices will return to the STANDBY mode.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page6The least significant 4 bits of the word address (column address) increments internally by one afterreceiving each data word. The rest of the word address bits (row address) do not change internally, butpointing to a specific memory row or page to be programmed. The first page write data word can be ofany column address. Up to 16 data words can be loaded into a page. If more then 16 data words areloaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word willbe loaded to the 2nd data word column address and so on. In other word, data word address (columnaddress) will “roll” over the previously loaded data.(C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internalprogramming. By issuing a valid read or write address command, the EEPROM will not acknowledge atthe 9th clock cycle if the device is still in the self-timed programming mode. However, if the programmingcompletes and the chip has returned to the STANDBY mode, the device will return a validACKNOWLEDGE signal at the 9th clock cycle.READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”.The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if thepower supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. TheEEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data wordwill then be serially clocked out. The internal address word counter will then automatically increase byone. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18thclock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the readoperation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bitand a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with anACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.Meanwhile the internally address word counter will then automatically increase by one. Unlike currentaddress read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signalingthe EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, theEEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter.If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clockcycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as longas the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When theinternal address counter reaches its maximum valid address, it rolls over to the beginning of the memoryarray address. Similar to current address read, the micro-controller can terminate the sequential read bynot acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with atarget read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a STARTbit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will thenacknowledge. The micro-controller will then send the address word. Again the EEPROM willacknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page7instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page8© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page9Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICS1.8 V2.5-5.0 V Symbol ParameterMin Max Min Max Unit f SCL Clock frequency, SCL 400 1000 kHz t LOW Clock pulse width low 1.20.7µst HIGH Clock pulse width high0.4 0.3 µst I Noise suppression time (1) 180 120 ns t AA Clock low to data out valid 0.3 0.9 0.2 0.7 µs t BUF Time the bus must be free before a new transmission can start (1)1.3 0.5 µs t HD.STA START hold time 0.6 0.25 µs t SU.STA START set-up time 0.6 0.25 µs t HD.DAT Data in hold time 0 0 µs t SU.DAT Data in set-up time 100100nst R Input rise time (1)0.3 0.3 µs t F Input fall time (1) 300 100 nst SU.STO STOP set-up time 0.6 0.25 µs t DH Date out hold time 50 50 ns WRWrite cycle time55msEndurance(1)25o C, Page Mode, 3.3V1,000,000Write CyclesNotes: 1. This Parameter is expected by characterization but are not fully screened by test.2. AC Measurement conditions: R L (Connects to Vcc): 1.3K ΩInput Pulse Voltages: 0.3Vcc to 0.7VccInput and output timing reference Voltages: 0.5VccDC CHARACTERISTICSSymbol Parameter TestConditions MinTypicalMaxUnitsV CC124C A supplyV CC1.8 5.5 VI CC Supply read current V CC@ 5.0V SCL = 400 kHz 0.5 1.0 mA I CC Supply write current V CC@ 5.0V SCL = 400 kHz 2.0 3.0 mA I SB1 Supplycurrent V CC@ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supplycurrent V CC@ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supplycurrent V CC@ 5.0V, V IN = V CC or V SS0.06 1.0 µAI IL Input leakagecurrentV IN = V CC or V SS 3.0 µAI LO Output leakagecurrentV IN = V CC or V SS 3.0 µAV IL Input low level -0.6 V CC x0.3 V V IH Input high level V CC x0.7V CC+0.5 V V OL1 Outputlowlevel V CC@ 1.8V, I OL = 0.15 mA 0.2 V V OL2 Outputlowlevel V CC@ 3.0V, I OL = 2.1 mA 0.4 V© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page10© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page11ORDERING INFORMATION:Density PackageTemperatureRangeVcc HSF Packaging Ordering CodeRoHSTube FT24C04A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C04A-UDG-B Tube FT24C04A-USR-B RoHSTape and Reel FT24C04A-USR-TTube FT24C04A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C04A-USG-TTube FT24C04A-UMR-B RoHSTape and Reel FT24C04A-UMR-TTube FT24C04A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C04A-UMG-TTube FT24C04A-UTR-B RoHSTape and Reel FT24C04A-UTR-TTube FT24C04A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C04A-UTG-T RoHS Tape and Reel FT24C04A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-ULG-T RoHS Tape and Reel FT24C04A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UPG-T RoHS Tape and Reel FT24C04A-UNR-T 4kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C04A-UNG-TRoHS Tube FT24C08A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C08A-UDG-B Tube FT24C08A-USR-B RoHSTape and Reel FT24C08A-USR-TTube FT24C08A-USG-B 8kbitsSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C08A-USG-TD: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8Packaging B: TubeT: Tape and Reel HSF R: RoHS G: GreenU:-40© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page12Density Package TemperatureRangeVcc HSF Packaging Ordering CodeTube FT24C08A-UMR-BRoHSTape and Reel FT24C08A-UMR-TTube FT24C08A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UMG-TTube FT24C08A-UTR-B RoHSTape and Reel FT24C08A-UTR-TTube FT24C08A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C08A-UTG-T RoHSTape and Reel FT24C08A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-ULG-T RoHS Tape and Reel FT24C08A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UPG-T RoHS Tape and Reel FT24C08A-UNR-T 8kbitsDFN8 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C08A-UNG-TRoHS Tube FT24C16A-UDR-B DIP8 -40℃-85℃ 1.8V-5.5VGreen Tube FT24C16A-UDG-B Tube FT24C16A-USR-B RoHSTape and Reel FT24C16A-USR-TTube FT24C16A-USG-B SOP8 -40℃-85℃ 1.8V-5.5VGreen Tape and Reel FT24C16A-USG-TTube FT24C16A-UMR-B RoHSTape and Reel FT24C16A-UMR-TTube FT24C16A-UMG-B MSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UMG-TTube FT24C16A-UTR-B RoHSTape and Reel FT24C16A-UTR-TTube FT24C16A-UTG-B TSSOP8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UTG-T RoHS Tape and Reel FT24C16A-ULR-T SOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-ULG-T RoHS Tape and Reel FT24C16A-UPR-T TSOT23-5 -40℃-85℃ 1.8V-5.5V Green Tape and Reel FT24C16A-UPG-T RoHS Tape and Reel FT24C16A-UNR-T 16kbitsDFN8 -40℃-85℃ 1.8V-5.5VGreenTape and Reel FT24C16A-UNG-TDIP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 3.710 4.310 0.146 0.170A1 0.510 0.020A2 3.200 3.600 0.126 0.142B 0.380 0.570 0.015 0.0221.524（BSC） 0.060（BSC）B1C 0.204 0.360 0.008 0.014D 9.000 9.400 0.354 0.370E 6.200 6.600 0.244 0.260E1 7.320 7.920 0.288 0.312(BSC) 0.100（BSC）e 2.540L 3.000 3.600 0.118 0.142E2 8.400 9.000 0.331 0.354© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page13SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061b 0.330 0.510 0.013 0.020c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157E1 5.800 6.200 0.228 0.244(BSC)(BSC) 0.050e 1.270L 0.400 1.270 0.016 0.050θ0° 8° 0° 8°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page14MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.820 1.100 0.320 0.043A1 0.020 0.150 0.001 0.006A2 0.750 0.950 0.030 0.037b 0.250 0.380 0.010 0.015c 0.090 0.230 0.004 0.009D 2.900 3.100 0.114 0.122e 0.65 (BSC) 0.026 (BSC)E 2.900 3.100 0.114 0.122E1 4.750 5.050 0.187 0.199L 0.400 0.800 0.016 0.031θ0° 6° 0° 6°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page15TSSOP8 PACKAGE OUTLINEDIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxD 2.900 3.100 0.114 0.122E 4.300 4.500 0.169 0.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008E1 6.250 6.550 0.246 0.258A 1.100 0.043A2 0.800 1.000 0.031 0.039A1 0.020 0.150 0.001 0.006e 0.65 (BSC) 0.026 (BSC)L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1° 7° 1° 7°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page16SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004A2 1.050 1.150 0.041 0.045b 0.300 0.500 0.012 0.020c 0.100 0.200 0.004 0.008D 2.820 3.020 0.111 0.119E 1.500 1.700 0.059 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.800 2.000 0.071 0.079L 0.300 0.600 0.012 0.024θ 0° 8° 0° 6°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page17TSOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 0.700 0.900 0.028 0.035A1 0.000 0.100 0.000 0.004A2 0.700 0.800 0.028 0.031b 0.350 0.500 0.014 0.020c 0.080 0.200 0.003 0.008D 2.820 3.020 0.111 0.119E 1.600 1.700 0.063 0.067E1 2.650 2.950 0.104 0.116e 0.95 (BSC) 0.037 (BSC)e1 1.90 (BSC) 0.075 (BSC)L 0.300 0.600 0.012 0.024θ 0° 8° 0° 8°© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page18DFN8 PACKAGE OUTLINE DIMENSIONSDimensions In MillimetersSymbolMin Nom Max0.75 0.80A 0.700.02 0.05A1 -0.25 0.03b 0.180.20 0.25c 0.182.00 2.10D 1.90D2 1.50REFe 0.50BSCNd 1.50BSC3.10E 2.903.00E2 1.60REF0.40 0.50L 0.300.25 0.30h 0.20© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page19Fremont Micro Devices (SZ) Limited#5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, ShenzhenTel: (86 755) 86117811Fax: (86 755) 86117810Fremont Micro Devices (Hong Kong) Limited#16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong KongTel: (852) 27811186Fax: (852) 27811144Fremont Micro Devices (USA), Inc.42982 Osgood Road Fremont, CA 94539Tel: (1-510) 668-1321Fax: (1-510) 226-9918Web Site: /* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners.© 2012 Fremont Micro Devices Inc. DS24C04_08_16-A0--page20。

C8051F060-GQR SILICON TQFP100 ATMEGA8L-8AU AT TQFP32 ATMEGA8A-AU AT TQFP32 ATMEGA8L-8AU AT TQFP32 ATMEGA8L-8AU AT TQFP32 ATMEGA8A-AU AT TQFP32 ATMEGA8A-AU AT TQFP32 ASM1042ASMEDIA QFN64 ASM1042ASMEDIA QFN64 MP2305DS-LF-Z.MPS代理MP2305DS-LF-Z MPS代理MP2303DN-LF-Z MPS代理MP2303ADN-LF-Z.MPS代理MP2303ADN-LF-Z MPS代理MP2357DJ-LF-Z MPS代理MP2309DS-LF-Z MPS代理MP2307DN-LF-Z MPS代理MP2359DJ-LF-Z MPS代理MP2359DJ-LF-Z.MPS代理FT4232HL FTDIFT2232L FTDIFT2232D FTDIFT245RL FTDIFT245BM FTDIFT245BL FTDIFT232RQ FTDIFT232RL FTDIFT232BM FTDIFT232BL FTDIMAX31865ATP+T MAXIMPESD15VL2BT NXPAP9345GM APSFP9640FAIRCHILDSI2301CJXPT2046XPT矽普特LBC857CLT1G LRCPESD12VS2UT NXPMSA00155PWR TIMCP4018T-502E/LT MCIROCHIPATMEGA325V-8MU ATMEL2BL5-0003MARVELL88W8000-BO-NNC-C000MARVELLMB87M4490PB-G-JXE1FUJITSUPPC750FX-GR0133T IBMMV64462-BAY1MARVELLGT48302A-BBA MARVELL深圳市明烽威电子有限公司GT48302A-BBA MARVELL GT48302A-B-O MARVELL MSM99Q034-002GS-BK4OKIR5C843RICOH CXP1051AQ SONY USB2223-NU-03SMSCZ84C1510AEC ZILOG MT8291E MTMST9886-LF-140MSTART-7202-FC-DB ATTC847UG-4G16JAPAN CH21UG-5CR4TOSHIBA MST6251A-205MSTAR OR4E02-1ORCA CXK77B1B40BGB-38SONY NQ82006MCHQM51ESINTELHY5PS1G1631CFP-Y5HYNIXMD56V62160J-7TAZL3AOKIMD56V62160J-7TAZL3AOKICXA2089Q SONYMV8508CNK MTEKVISIO MV3013DAB-G MTEKVISIO MV8652CAB-G MTEKVISIO LM2576-5.0TI/NSLM2576S-ADJ TI/NSLM2576S-12TI/NSLM2576S-5.0TI/NSLM2596SX-ADJ TI/NSLM2596SX-5.0TI/NSLM2596SX-12TI/NSLM2576SX-ADJ TI/NSLM2576SX-12TI/NSLM2576SX-5.0TI/NSL7805CD2T STLM2576T-5.0NSHT1621B HTLM317T STLM317MDT NSLM317EMP NSLM317AEMP NSL7805STAMS1117-1.2-5.0-3.3-1.8-2.5-1.5-ADJAMSTD1410ST7538Q STSTPS20H100CT STST7538Q ST817b SHARP PC817B SHARP PC817C SHARP NTR4503NT1G ONSEMI NE555DR TINCP1579DR2G ONAZ431AN-ATRE1BCDSTM32F103C8T6LM2576D2T-005GSTM32F103C8T6ST72C215G2B6ST72C215G2B62SC3355LTK5203EP4CE22F17C8NMCP2200-I/SS430G2553TDA8034HN/C1NXPDB2J41100L Panasonic DB2J40700L Panasonic DB2J31300L Panasonic DB2730800L Panasonic DB2730800L Panasonic DA2J10100L Panasonic DA22F2100L Panasonic AN44069A-VF Panasonic AN29160AA-VF Panasonic MJD45H11G ONMJD44H11G ONLMR10510XMF TILM311DR TILD1117S50TR STIS01541DR TIIN4148-MIC MICDY12S05-2W YAOHUA CD74HC00DR TICD4051BM TISA608DK PHITLP222G(F)TOSHIBA NJM062V JRCEPM7128STC100-7ALTBRATLP785(D4,GRH,TPTOSHIBA 6(CACPM-2302-TR1AVAGOTMP87C807UG-5DR7TOSHIBATMP92CF29AFG-7770TOSHIBATA31180FN TOS ACPM-5805-TR1AVAGO RT5002AZQW RICHTEK RT9013-18GU5RICHTEK ACPM-7870-TR1AVAGO TC74LVX4053FT TOSHIBAVT8601A(VT3127A6/TMF501B )VIAA0509S-2W MORNSUN/GANMA0509S-2W MORNSUN/GANMA0509S-1W MORNSUN/GANMA0509S-1W MORNSUN/GANMA0509S-1W MORNSUN/GANMA0509S-1W MORNSUN/GANMA0509D-2W GANMAA0509D-2W MORNSUN/GANMA0509D-2W GANMAA0509D-2W MORNSUN/GANMA0509D-1W GANMAA0509D-1W MORNSUN/GANMA0509D-1W GANMAA0509D-1W MORNSUN/GANMA0505S-2W MORNSUN/GANMA0505S-2W MORNSUN/GANMA0505S-2W MORNSUN/GANMA0505S-2W MORNSUN/GANMA0505S-1W MORNSUN/GANMA0505S-1W MORNSUN/GANMA0505S-1W MORNSUN/GANMA0505S-1W MORNSUN/GANMA0505D-2W GANMAA0505D-2W MORNSUN/GANMA0505D-2W MORNSUN/GANMA0505D-2W MORNSUN/GANMA0505D-2W MORNSUN/GANMA0505D-1W GANMAA0505D-1W MORNSUN/GANMA0505D-1W GANMASPA20N60C3INFINEON MBRF20100CTG ONSPA08N80C3INFINEON SIHP22N60S-E3VISHAYIRFP27N60KPBF VISHAYFDA20N50FAIRCHILDIPA60R299CP INFINEON IRFPS40N50LPBF IRIPA60R199CP Infineon IRFPS43N50KPBF IRSPA11N80C3INFINEON FGL40N120ANDTU FSC/原装FGA25N120ANTDTU FSC/原装TK10A60D TOS原装2SK3568TOS原装STTH3003CW ST原装STP7NK80ZFP ST原装STP4NK60ZFP ST原装STP10NK80ZFP ST原装SPA20N60C3INFINEON KA5M02659R-YDTU FAIRCHILD仙KA5M02659RTU FAIRCHILD仙KA5M02659RNB FAIRCHILD仙KA5L0380R-YDTU FAIRCHILD仙KA431Z FAIRCHILD仙KA3525FAIRCHILD仙K2010B(4N35B)COSMOK1010(KPC817C)COSMOK1010(KPC817B)COSMOJC817C匡通KA5Q0765R FGA15N120AN FAN6300AMY FSL106HR FSL126MR FSL116LRFQPF5N60C FQPF8N60C FSDM0265R FAN6754MRMY RHRD660S9A KA5H0165RTUFSDM0365RFSDH321 FSDM07652REFSL136MR FAN7602BMX TSM103WAIDTFSDM311 FQPF7N80C FSDM0565R NC7WB66K8X NC7SZ74K8X FAN6862TYFSDM0465R FQPF12N60C FQPF10N60CFAN7530MX FAN7930CMX FDPF13N50NZFDPF12N60NZFSFR2100 VIPER12AS/22AS FSEZ1317MY/NY AZ431AZBU406TUFQP(F)6N90C FDPF7N60NZ FQPF7N65C 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24C02/A, 24C04/A, 24C08/A , 24C16/A© 2007 Fremont Micro Devices Inc. DS3001H-page 1Two-Wire Serial EEPROM2K, 4K, 8K and 16K ( 8-bit wide )FEATURESLow voltage and low power operations:•FT24C02/04/08/16:V CC = 2.5V to 5.5V• FT24C02A/04A/08A/16A: V CC = 1.8V to 5.5VMaximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). 16 bytes page write mode.Partial page write operation allowed.Internally organized: 256 × 8 (2K), 512 × 8 (4K), 1024 × 8 (8K), 2048 × 8 (16K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed programming cycle (5ms maximum). Automatic erase before write operation.Write protect pin for hardware data protection.High reliability: typically 1, 000,000 cycles endurance. 100 years data retention.Industrial temperature range (-40o C to 85o C).Standard 8-pin PDIP/SOIC/TSSOP and 5-pin SOT-23 Pb-free packages.DESCRIPTIONThe FT24C02/04/08/16 series are 2048/4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 256/512/1024/2048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP and 5-lead SOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended V CC range (1.8V to 5.5V) devices enables wide spectrum of applications.PIN CONFIGURATIONPin Name Pin FunctionA2, A1, A0 Device Address InputsSDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NCNo-Connect24C02/A, 24C04/A, 24C08/A , 24C16/ADS3001H-page 2 © 2007 Fremont Micro Devices Inc.All these packaging types come in conventional or Pb-free certified.VCC W P SCL SDAA2A1A0GND8L PDIP 8L SOIC8L TSSOP VCC W P SCL SDAA2A1A08L PDIP 8L SOIC8L TSSOP VCC W P SCLA2A1A0GND8L PDIP 8L SOIC8L TSSOP VCC W P SCL SDAA2A1A0GND8L PDIP 8L SOIC 8L TSSOPW P VCCFT24C02/04/08/16SOT-23-5ABSOLUTE MAXIMUM RATINGSIndustrial operating temperature: -40o C to 85o C Storage temperature: -50o C to 125o C Input voltage on any pin relative to ground: -0.3V to V CC + 0.3V Maximum voltage: 8VESD protection on all pins: >2000V* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality .24C02/A, 24C04/A, 24C08/A , 24C16/A© 2007 Fremont Micro Devices Inc. DS3001H-page 3PIN DESCRIPTIONS(A) SERIAL CLOCK (SCL)The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device.(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either V IH or V IL . If left unconnected, they are internally recognized as V IL . Only FT24C02 uses all three signals. FT24C04 has A0 pin as no-connect. FT24C08 has both A0 and A1 pins as no-connect. For FT24C16, all device address pins (A0-A2) are no-connect. (C) SERIAL DATA LINE (SDA)SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP)The FT24C02/04/08/16 devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to V IL . Conversely all programming functions are disabled if WP pin is connected to V IH or V CC . Read operations is not affected by the WP pin’s input level.Table ADevice Chip Select/Device Address Pins UsedNo-Connect PinsMax number of similar devices on the same busFT24C02 A2, A1, A0 (None) 8 FT24C04 A2, A1 A04FT24C08 A2, A1, A0 2 FT24C16(None)A2, A1, A01MEMORY ORGANIZATIONThe FT24C02/04/08/16 devices have 16/32/64/128 pages respectively. Since each page has 16 bytes, random wordaddressing to FT24C02/04/08/16 will require 8/9/10/11 bits data word addresses respectively.DEVICE OPERATION(A) SERIAL CLOCK AND DATA TRANSITIONSThe SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at V IL . Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITIONWith SCL ≥ V IH , a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.24C02/A, 24C04/A, 24C08/A , 24C16/ADS3001H-page 4 © 2007 Fremont Micro Devices Inc.(C) STOP CONDITIONWith SCL ≥ V IH , a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGEThe 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODEThe EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.Figure 1: Timing diagram for START and STOP conditionsFigure 2: Timing diagram for output ACKNOWLEDGESCLSDASTART ConditionSTOP ConditionData Data Valid TransitionSCLData inData out START ConditionACK24C02/A, 24C04/A, 24C08/A, 24C16/ADEVICE ADDRESSINGThe 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.Referring to table A, FT24C02 uses A2 (5th), A1 (6th), and A0 (7th) as device address bits. Up to eight FT24C02 devices can be wired-OR on the same 2-wire bus. Each FT2C02 Chip select address pin needs to be hard wired and coded from 000 (b) to 111 (b). Individual FT24C02 device will be selected if the three device address bits (5th, 6th, 7th) match the chip select address code.FT24C04 uses A2 (5th) and A1 (6th) device address bits. Only four FT24C04 devices can be wired-OR on the same 2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11 (b).Chip select address pin A0 is not used.FT24C08 uses only A2 (5th) device address bit. Only two FT24C08 devices can be wired-OR on the same 2-wire bus.Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select address pins A1 and A0 are not used.FT24C16 does not use any device address bit. Only one FT24C16 device can be used on the on 2-wire bus. Chip Select address pins A2, A1, and A0 are not used.WRITE OPERATIONS(A) BYTE WRITEA byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROMdevice address and then a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC, the byte programming will finish and the EEPROM device will return to the STANDBY mode.(B) PAGE WRITEA page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along thesame page or memory row. All FT24C02/04/08/16 are organized to have 16 bytes per memory row or page.With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n × 9th clock cycle.After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of T WC, the devices will return to the STANDBY mode.© 2007 Fremont Micro Devices Inc. DS3001H-page524C02/A, 24C04/A, 24C08/A, 24C16/A The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th data word will be loaded to the 2nd data word column address and so on.In other word, data word address (column address) will “roll” over the previously loaded data.(C) ACKNOWLEDGE POLLINGACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming.By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle. READ OPERATIONSThe read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows:(A) CURRENT ADDRESS READThe EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out.The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode.(B) SEQUENTIAL READThe sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead.(C) RANDOM READRandom read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read.To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge.The micro-controller will then send the address word. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address.DS3001H-page6 © 2007 Fremont Micro Devices Inc.24C02/A, 24C04/A, 24C08/A, 24C16/A© 2007 Fremont Micro Devices Inc. DS3001H-page724C02/A, 24C04/A, 24C08/A, 24C16/ADS3001H-page 8 © 2007 Fremont Micro Devices Inc.Figure 8: SCL and SDA Bus TimingAC CHARACTERISTICSFT24C02A / 04A / 08A / 16AFT24C 02 / 04 / 08 / 16FT24C02A / 04A / 08A / 16A 02 / 04 / 08 / 161.8 V2.5 V5.5 VSymbolParameterMin Max Min Max Min Max Unit f SCLClock frequency, SCL 100 400 400 kHz t LOW Clock pulse width low 4.71.21.2µst HIGH Clock pulse width high 4.0 0.6 0.6 µs t I Noise suppression time 100 50 50 ns t AA Clock low to data out valid0.1 4.5 0.1 0.9 0.1 0.9 µs t BUF Time the bus must be free before a new transmission can start 4.7 1.2 1.2 µs t HD.STA START hold time 4.0 0.6 0.6 µs t SU.STA START set-up time 4.7 0.6 0.6 µst HD.DAT Data in hold time 0 0 0 µs t SU.DAT Data in set-up time 200 100 100 ns t R Input rise time 1 0.3 0.3 µs t F Input fall time 300 300 300 ns t SU.STO STOP set-up time 4.7 0.6 0.6 µs t DH Date out hold time 100 50 50 ns t WRWrite cycle time555ms24C02/A, 24C04/A, 24C08/A , 24C16/A© 2007 Fremont Micro Devices Inc. DS3001H-page 9DC CHARACTERISTICSSymbol Parameter Test ConditionsMin Typical Max Units V CC1 24C ××A supply V CC 1.8 5.5 V V CC1 24C ×× supply V CC2.5 5.5 V I CC Supply read current V CC @ 5.0V SCL = 100 kHz 0.5 1.0 mA I CCSupply write currentV CC @ 5.0V SCL = 100 kHz2.03.0mAI SB1 Supply current V CC @ 1.8V, V IN = V CC or V SS 1.0 µA I SB2 Supply current V CC @ 2.5V, V IN = V CC or V SS 1.0 µA I SB3 Supply current V CC @ 5.0V, V IN = V CC or V SS 0.07 1.0 µAI IL Input leakage current V IN = V CC or V SS 3.0 µA I LO Output leakage current V IN = V CC or V SS 3.0 µA V IL Input low level -0.6V CC × 0.3 V V IH Input high levelV CC ×0.7V CC + 0.5 V V OL2 Output low level V CC @ 3.0V, I OL = 2.1 mA 0.4 V V OL1 Output low levelV CC @ 1.8V, I OL = 0.15 mA0.4V24C02/A, 24C04/A, 24C08/A , 24C16/ADS3001H-page 10 © 2007 Fremont Micro Devices Inc.ORDER CODE:ORDER INFORMATIONOrder codeVccTemperatureRangePackage Option PackagingFT24C02A-CDG-B 1.8v-5.5v 0-700C DIP8 Green Package Tube FT24C02A-CDR-B 1.8v-5.5v 0-700C DIP8 RoHS Tube FT24C02A-IDG-B 1.8v-5.5v -40-850C DIP8 Green Package Tube FT24C02A-IDR-B 1.8v-5.5v -40-850C DIP8 RoHS TubeFT24C02-CDG-B 2.5v-5.5v 0-700C DIP8 Green Package TubeFT24C02-CDR-B 2.5v-5.5v 0-700C DIP8 RoHS TubeFT24C02-IDG-B 2.5v-5.5v -40-850C DIP8 Green Package TubeFT24C02-IDR-B 2.5v-5.5v -40-850C DIP8 RoHS TubeFT24C02A-CSG-B 1.8v-5.5v 0-700C SOP8 Green Package Tube FT24C02A-CSG-T 1.8v-5.5v 0-700C SOP8 Green Package T/R FT24C02A-CSR-B 1.8v-5.5v 0-700C SOP8 RoHS TubeFT24C02A-CSR-T 1.8v-5.5v 0-700C SOP8 RoHS T/RFT24C02A-ISG-B 1.8v-5.5v -40-850C SOP8 Green Package Tube FT24C02A-ISG-T 1.8v-5.5v -40-850C SOP8 Green Package T/R FT24C02A-ISR-B 1.8v-5.5v -40-850C SOP8 RoHS TubeFT24C02A-ISR-T 1.8v-5.5v -40-850C SOP8 RoHS T/RFT24C02-CSG-B 2.5v-5.5v 0-700C SOP8 Green Package Tube FT24C02-CSG-T 2.5v-5.5v 0-700C SOP8 Green Package T/R FT24C02-CSR-B 2.5v-5.5v 0-700C SOP8 RoHS TubeFT24C02-CSR-T 2.5v-5.5v 0-700C SOP8 RoHS T/RFT24C02-ISG-B 2.5v-5.5v -40-850C SOP8 Green Package TubeORDER INFORMATION（CONTINUED）Order code Vcc TemperaureRangePackage Option PackagingFT24C02-ISG-T 2.5v-5.5v -40-850C SOP8GreenPackage T/R FT24C02-ISR-B 2.5v-5.5v -40-850C SOP8RoHS Tube FT24C02-ISR-T 2.5v-5.5v -40-850C SOP8RoHS T/R FT24C02A-CTG-B 1.8v-5.5v 0-700C TSSOP8GreenPackage Tube FT24C02A-CTG-T 1.8v-5.5v 0-700C TSSOP8GreenPackage T/R FT24C02A-CTR-B 1.8v-5.5v 0-700C TSSOP8RoHS Tube FT24C02A-CTR-T 1.8v-5.5v 0-700C TSSOP8RoHS T/R FT24C02A-ITG-B 1.8v-5.5v -40-850C TSSOP8GreenPackage Tube FT24C02A-ITG-T 1.8v-5.5v -40-850C TSSOP8GreenPackage T/R FT24C02A-ITR-B 1.8v-5.5v -40-850C TSSOP8RoHS Tube FT24C02A-ITR-T 1.8v-5.5v -40-850C TSSOP8RoHS T/R FT24C02A-CLG-T 1.8v-5.5v 0-700C SOT23-5GreenPackage T/R FT24C02A-CLR-T 1.8v-5.5v 0-700C SOT23-5RoHS T/R FT24C02A-ILG-T 1.8v-5.5v -40-850C SOT23-5GreenPackage T/R FT24C02A-ILR-T 1.8v-5.5v -40-850C SOT23-5RoHS T/R FT24C02-CLG-T 2.5v-5.5v 0-700C SOT23-5GreenPackage T/R FT24C02-CLR-T 2.5v-5.5v 0-700C SOT23-5RoHS T/R FT24C02-ILG-T 2.5v-5.5v -40-850C SOT23-5GreenPackage T/R FT24C02-ILR-T 2.5v-5.5v -40-850C SOT23-5RoHS T/R© 2007 Fremont Micro Devices Inc. DS3001H-page11ORDER INFORMATION（CONTINUED）Order code Vcc TemperatureRangePackage Option PackagingFT24C04A-CDG-B 1.8v-5.5v 0-700C DIP8GreenPackage Tube FT24C04A-CDR-B 1.8v-5.5v 0-700C DIP8RoHS Tube FT24C04A-IDG-B 1.8v-5.5v -40-850C DIP8GreenPackage Tube FT24C04A-IDR-B 1.8v-5.5v -40-850C DIP8RoHS Tube FT24C04A-CSG-B 1.8v-5.5v 0-700C SOP8GreenPackage Tube FT24C04A-CSG-T 1.8v-5.5v 0-700C SOP8GreenPackage T/R FT24C04A-CSR-B 1.8v-5.5v 0-700C SOP8RoHS Tube FT24C04A-CSR-T 1.8v-5.5v 0-700C SOP8RoHS T/R FT24C04A-ISG-B 1.8v-5.5v -40-850C SOP8GreenPackage Tube FT24C04A-ISG-T 1.8v-5.5v -40-850C SOP8GreenPackage T/R FT24C04A-ISR-B 1.8v-5.5v -40-850C SOP8RoHS Tube FT24C04A-ISR-T 1.8v-5.5v -40-850C SOP8RoHS T/R FT24C04-CSG-B 2.5v-5.5v 0-700C SOP8GreenPackage Tube FT24C04-CSG-T 2.5v-5.5v 0-700C SOP8GreenPackage T/R FT24C04-CSR-B 2.5v-5.5v 0-700C SOP8RoHS Tube FT24C04-CSR-T 2.5v-5.5v 0-700C SOP8RoHS T/R FT24C04-ISG-B 2.5v-5.5v -40-850C SOP8GreenPackage Tube FT24C04-ISG-T 2.5v-5.5v -40-850C SOP8GreenPackage T/R FT24C04-ISR-B 2.5v-5.5v-40-850C SOP8RoHS Tube FT24C04-ISR-T 2.5v-5.5v-40-850C SOP8RoHS T/R FT24C04A-CTG-B 1.8v-5.5v 0-700C TSSOP8GreenPackage Tube FT24C04A-CTG-T 1.8v-5.5v 0-700C TSSOP8GreenPackage T/R FT24C04A-CTR-B 1.8v-5.5v 0-700C TSSOP8RoHS Tube FT24C04A-CTR-T 1.8v-5.5v 0-700C TSSOP8RoHS T/R FT24C04A-ITG-B 1.8v-5.5v -40-850C TSSOP8GreenPackage Tube FT24C04A-ITG-T 1.8v-5.5v -40-850C TSSOP8GreenPackage T/R FT24C04A-ITR-B 1.8v-5.5v -40-850C TSSOP8RoHS Tube FT24C04A-ITR-T 1.8v-5.5v -40-850C TSSOP8RoHS T/RDS3001H-page12 © 2007 Fremont Micro Devices Inc.ORDER INFORMATION（CONTINUED）Order code Vcc TemperatureRangePackage Option PackagingFT24C08A-CDG-B 1.8v-5.5v 0-700C DIP8GreenPackage Tube FT24C08A-CDR-B 1.8v-5.5v 0-700C DIP8RoHS Tube FT24C08A-IDG-B 1.8v-5.5v -40-850C DIP8GreenPackage Tube FT24C08A-IDR-B 1.8v-5.5v -40-850C DIP8RoHS Tube FT24C08-CDG-B 2.5v-5.5v 0-700C DIP8GreenPackage Tube FT24C08-CDR-B 2.5v-5.5v 0-700C DIP8RoHS Tube FT24C08-IDG-B 2.5v-5.5v -40-850C DIP8GreenPackage Tube FT24C08-IDR-B 2.5v-5.5v -40-850C DIP8RoHS Tube FT24C08A-CSG-B 1.8v-5.5v 0-700C SOP8GreenPackage Tube FT24C08A-CSG-T 1.8v-5.5v 0-700C SOP8GreenPackage T/R FT24C08A-CSR-B 1.8v-5.5v 0-700C SOP8RoHS Tube FT24C08A-CSR-T 1.8v-5.5v 0-700C SOP8RoHS T/R FT24C08A-ISG-B 1.8v-5.5v -40-850C SOP8GreenPackage Tube FT24C08A-ISG-T 1.8v-5.5v -40-850C SOP8GreenPackage T/R FT24C08A-ISR-B 1.8v-5.5v -40-850C SOP8RoHS Tube FT24C08A-ISR-T 1.8v-5.5v -40-850C SOP8RoHS T/R FT24C08-CSG-B 2.5v-5.5v 0-700C SOP8GreenPackage Tube FT24C08-CSG-T 2.5v-5.5v 0-700C SOP8GreenPackage T/R FT24C08-CSR-B 2.5v-5.5v 0-700C SOP8RoHS Tube FT24C08-CSR-T 2.5v-5.5v 0-700C SOP8RoHS T/R FT24C08-ISG-B 2.5v-5.5v -40-850C SOP8GreenPackage Tube FT24C08-ISG-T 2.5v-5.5v -40-850C SOP8GreenPackage T/R FT24C08-ISR-B 2.5v-5.5v -40-850C SOP8RoHS Tube FT24C08-ISR-T 2.5v-5.5v -40-850C SOP8RoHS T/R FT24C08A-CTG-B 1.8v-5.5v 0-700C TSSOP8GreenPackage Tube FT24C08A-CTG-T 1.8v-5.5v 0-700C TSSOP8GreenPackage T/R FT24C08A-CTR-B 1.8v-5.5v 0-700C TSSOP8RoHS Tube FT24C08A-CTR-T 1.8v-5.5v 0-700C TSSOP8RoHS T/R FT24C08A-ITG-B 1.8v-5.5v -40-850C TSSOP8GreenPackage Tube FT24C08A-ITG-T 1.8v-5.5v -40-850C TSSOP8GreenPackage T/R FT24C08A-ITR-B 1.8v-5.5v -40-850C TSSOP8RoHS Tube FT24C08A-ITR-T 1.8v-5.5v -40-850C TSSOP8RoHS T/R© 2007 Fremont Micro Devices Inc. DS3001H-page13ORDER INFORMATION（CONTINUED）Order code Vcc TemperatureRangePackage Option PackagingFT24C16A-CDG-B 1.8v-5.5v 0-700C DIP8GreenPackage Tube FT24C16A-CDR-B 1.8v-5.5v 0-700C DIP8RoHS Tube FT24C16A-IDG-B 1.8v-5.5v -40-850C DIP8 GreenPackage Tube FT24C16A-IDR-B 1.8v-5.5v -40-850C DIP8 RoHS TubeFT24C16-CDG-B 2.5v-5.5v 0-700C DIP8GreenPackage Tube FT24C16-CDR-B 2.5v-5.5v 0-700C DIP8RoHS Tube FT24C16-IDG-B 2.5v-5.5v-40-850C DIP8 GreenPackage Tube FT24C16-IDR-B 2.5v-5.5v-40-850C DIP8 RoHS Tube FT24C16A-CSG-B 1.8v-5.5v 0-700C SOP8GreenPackage Tube FT24C16A-CSG-T 1.8v-5.5v 0-700C SOP8GreenPackage T/R FT24C16A-CSR-B 1.8v-5.5v 0-700C SOP8RoHS Tube FT24C16A-CSR-T 1.8v-5.5v 0-700C SOP8RoHS T/R FT24C16A-ISG-B 1.8v-5.5v -40-850C SOP8 GreenPackage Tube FT24C16A-ISG-T 1.8v-5.5v -40-850C SOP8 GreenPackage T/R FT24C16A-ISR-B 1.8v-5.5v -40-850C SOP8 RoHS TubeFT24C16A-ISR-T 1.8v-5.5v -40-850C SOP8 RoHS T/RFT24C16-CSG-B 2.5v-5.5v 0-700C SOP8GreenPackage Tube FT24C16-CSG-T 2.5v-5.5v 0-700C SOP8GreenPackage T/R FT24C16-CSR-B 2.5v-5.5v 0-700C SOP8RoHS Tube FT24C16-CSR-T 2.5v-5.5v 0-700C SOP8RoHS T/R FT24C16-ISG-B 2.5v-5.5v-40-850C SOP8 GreenPackage Tube FT24C16-ISG-T 2.5v-5.5v-40-850C SOP8 GreenPackage T/R FT24C16-ISR-B 2.5v-5.5v-40-850C SOP8 RoHS Tube FT24C16-ISR-T 2.5v-5.5v-40-850C SOP8 RoHS T/R FT24C16A-CTG-B 1.8v-5.5v 0-700C TSSOP8GreenPackage Tube FT24C16A-CTG-T 1.8v-5.5v 0-700C TSSOP8GreenPackage T/R FT24C16A-CTR-B 1.8v-5.5v 0-700C TSSOP8RoHS TubeFT24C16A-CTR-T 1.8v-5.5v 0-700C TSSOP8RoHS T/RFT24C16A-ITG-B 1.8v-5.5v -40-850C TSSOP8GreenPackage Tube FT24C16A-ITG-T 1.8v-5.5v -40-850C TSSOP8GreenPackage T/R FT24C16A-ITR-B 1.8v-5.5v -40-850C TSSOP8RoHS TubeFT24C16A-ITR-T 1.8v-5.5v -40-850C TSSOP8RoHS T/RFT24C16A-CLG-T 1.8v-5.5v 0-700C SOT23-5GreenPackage T/R FT24C16A-CLR-T 1.8v-5.5v 0-700C SOT23-5RoHS T/RFT24C16A-ILG-T 1.8v-5.5v -40-850C SOT23-5GreenPackage T/R FT24C16A-ILR-T 1.8v-5.5v -40-850C SOT23-5RoHS T/RFT24C16-CLG-T 2.5v-5.5v 0-700C SOT23-5GreenPackage T/R FT24C16-CLR-T 2.5v-5.5v 0-700C SOT23-5RoHS T/RFT24C16-ILG-T 2.5v-5.5v-40-850C SOT23-5GreenPackage T/R FT24C16-ILR-T 2.5v-5.5v-40-850C SOT23-5RoHS T/RDS3001H-page14 © 2007 Fremont Micro Devices Inc.TSSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxD 2.900 3.100 0.114 0.122E 4.300 4.500 0.169 0.177b 0.190 0.300 0.007 0.012c 0.090 0.200 0.004 0.008E1 6.250 6.550 0.246 0.258A 1.100 0.043A2 0.800 1.000 0.031 0.039A1 0.020 0.150 0.001 0.006(BSC)(BSC) 0.026e 0.65L 0.500 0.700 0.020 0.028H 0.25 (TYP) 0.01 (TYP)θ 1° 7° 1° 7°© 2007 Fremont Micro Devices Inc. DS3001H-page15DS3001H-page 16 © 2007 Fremont Micro Devices Inc. SOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min Max A 1.350 1.750 0.053 0.069A1 0.100 0.250 0.004 0.010A2 1.350 1.550 0.053 0.061b 0.330 0.510 0.013 0.020c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157E1 5.800 6.200 0.228 0.244e 1.270 (BSC)0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0°8°0° 8°© 2007 Fremont Micro Devices Inc. DS3001H-page17MSOP8 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbol Min Max Min MaxA 0.820 1.100 0.320 0.043A1 0.020 0.150 0.001 0.006A2 0.750 0.950 0.030 0.037b 0.250 0.380 0.010 0.015c 0.090 0.230 0.004 0.009D 2.900 3.100 0.114 0.122e 0.65 (BSC) 0.026 (BSC)E 2.900 3.100 0.114 0.122E1 4.750 5.050 0.187 0.199L 0.400 0.800 0.016 0.031θ 0° 6° 0° 6°SOT-23-5 PACKAGE OUTLINE DIMENSIONSDimensions In Millimeters Dimensions In InchesSymbolMin Max Min MaxA 1.050 1.250 0.041 0.049A1 0.000 0.100 0.000 0.004A2 1.050 1.150 0.041 0.045b 0.300 0.500 0.012 0.020c 0.100 0.200 0.004 0.008D 2.820 3.020 0.111 0.119E 1.500 1.700 0.059 0.067E1 2.650 2.950 0.104 0.116(BSC)(BSC) 0.037e 0.95e1 1.800 2.000 0.071 0.079L 0.300 0.600 0.012 0.024θ0° 8° 0° 6°DS3001H-page18 © 2007 Fremont Micro Devices Inc.Info rmation furnished is believed to be accurate and reliable. However, Fremont Micro Devices.,Ltd.(FMD) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices.,Ltd.(FMD). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices.,Ltd.(FMD) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices.,Ltd.(FMD).The FMD logo is a registered trademark of Fremont Micro Devices.,Ltd.All other names are the property of their respective owners©2007Fremont Micro Devices.,Ltd.-All rights reserved© 2007 Fremont Micro Devices Inc. DS3001H-page19。

常规的贴片电阻的标准封装及额定功率常规的贴片电阻的标准封装及额定功率常规的贴片电阻的标准封装及额定功率如下表:英制(mil 公制(mm 额定功率(W@ 70°C0201 0603 1/200402 1005 1/160603 1608 1/100805 2012 1/81206 3216 1/41210 3225 1/31812 4832 1/22010 5025 3/42512 6432 1国内贴片电阻的命名方法:1、5%精度的命名:RS-05K102JT2、1%精度的命名:RS-05K1002FTR -表示电阻S -表示功率 0402是 1/16W、 0603是 1/10W、 0805是 1/8W、 1206是 1/4W、1210是 1/3W、1812是 1/2W、2010是 3/4W、2512是 1W。

05 -表示尺寸(英寸:02表示 0402、 03表示 0603、 05表示 0805、 06表示1206、 1210表示 1210、1812表示 1812、10表示 1210、12表示 2512。

K -表示温度系数为 100PPM,102-5%精度阻值表示法:前两位表示有效数字, 第三位表示有多少个零, 基本单位是Ω,102=10000Ω=1KΩ。

1002是 1%阻值表示法:前三位表示有效数字,第四位表示有多少个零,基本单位是Ω,1002=100000Ω=10KΩ。

J -表示精度为 5%、F-表示精度为 1%。

T -表示编带包装0805的焊盘大小虽然固定,但是厚度和陶瓷的材质会有差别,普通的允许耗散功率是 1/10W-1/8W,功率型(绿色可以做到 1/4W。

如果你想让贴片电阻有较大的功耗, 建议你把焊盘做在面积比较大的覆铜上, 这样, 普通 0805封装的电阻 1/4W也不会有问题, 只是热稳定性稍微差一点点。

1206的在 1/8W-1/2W之间电容电阻外形尺寸与封装的对应关系是:0402=1.0mmx0.5mm 0603=1.6mmx0.8mm 0805=2.0mmx1.2mm1206=3.2mmx1.6mm 1210=3.2mmx2.5mm 1812=4.5mmx3.2mm2225=5.6mmx6.5mm封装额定功率@ 70°C英制公制(mil (mm 常规功率系列提升功率系列最大工作电压(V第 1页02010603 1/20W /2504021005 1/16W /5006031608 1/16W 1/10W 5008052012 1/10W 1/8W 15012063216 1/8W 1/4W 20012103225 1/4W 1/3W 20018124832 1/2W /20020105025 1/2W 3/4W20025126432 1W /200标准阻值表 1E-96 0603F(+1% Standard Resistance Table阻值代码阻值代码阻值代码阻值代码阻值代码10.0 01X 100 01A 1.00K 01B 10.0K 01C 100K 01D 10.2 02X 102 02A 1.02K 02B 10.2K 02C 102K 02D 10.5 03X 105 03A 1.05K 03B 10.5K 03C 105K 03D10.7 04X 107 04A 1.07K 04B 10.7K 04C 107K 04D11.0 05X 110 05A 1.10K 05B 11.0K 05C 110K 05D 11.3 06X 113 06A 1.13K 06B 11.3K 06C 113K 06D 11.5 07X 115 07A 1.15K 07B 11.5K 07C 115K 07D 11.8 08X 118 08A 1.18K 08B 11.8K 08C 118K 08D12.1 09X 121 09A 1.21K 09B 12.1K 09C 121K 09D 12.4 10X 124 10A 1.24K 10B 12.4K 10C 124K 10D12.7 11X 127 11A 1.27K 11B 12.7K 11C 127K 11D13.0 12X 130 12A 1.30K 12B 13.0K 12C 130K 12D 13.3 13X 133 13A 1.33K 13B 13.3K 13C 133K 13D 第 2页13.7 14X 137 14A 1.37K 14B 13.7K 14C 137K 14D14.0 15X 140 15A 1.40K 15B 14.0K 15C 140K 15D 14.3 16X 143 16A 1.43K 16B 14.3K 16C 143K 16D14.7 17X 147 17A 1.47K 17B 14.7K 17C 147K 17D15.0 18X 150 18A 1.50K 18B 15.0K 18C 150K 18D 15.4 19X 154 19A 1.54K 19B 15.4K 19C 154K 19D15.8 20X 158 20A 1.58K 20B 15.8K 20C 158K 20D16.2 21X 162 21A 1.62K 21B 16.2K 21C 162K 21D 16.5 22X 165 22A 1.65K 22B 16.5K 22C 165K 22D16.9 23X 169 23A 1.69K 23B 16.9K 23C 169K 23D17.4 24X 174 24A 1.74K 24B 17.4K 24C 174K 24D17.8 25X 178 25A 1.78K 25B 17.8K 25C 178K 25D18.2 26X 182 26A 1.82K 26B 18.2K 26C 182K 26D18.7 27X 187 27A 1.87K 27B 18.7K 27C 187K 27D19.1 28X 191 28A 1.91K 28B 19.1K 28C 191K 28D19.6 29X 196 29A 1.96K 29B 19.6K 29C 196K 29D20.0 30X 200 30A 2.00K 30B 20.0K 30C 200K 30D20.5 31X 205 31A 2.05K 31B 20.5K 31C 205K 31D21.0 32X 210 32A 2.10K 32B 21.0K 32C 210K 32D21.5 33X 215 33A 2.15K 33B 21.5K 33C 215K 33D22.1 34X 221 34A 2.21K 34B 22.1K 34C 221K 34D22.6 35X 226 35A 2.26K 35B 22.6K 35C 226K 35D23.2 36X 232 36A 2.32K 36B 23.2K 36C 232K 36D23.7 37X 237 37A 2.37K 37B 23.7K 37C 237K 37D24.3 38X 243 38A 2.43K 38B 24.3K 38C 243K 38D24.9 39X 249 39A 2.49K 39B 24.9K 39C 249K 39D25.5 40X 255 40A 2.55K 40B 25.5K 40C 255K 40D26.1 41X 261 41A 2.61K 41B 26.1K 41C 261K 41D26.7 42X 267 42A 2.67K 42B 26.7K 42C 267K 42D27.4 43X 274 43A 2.74K 43B 27.4K 43C 274K 43D28.0 44X 280 44A 2.80K 44B 28.0K 44C 280K 44D 28.7 45X 287 45A 2.87K 45B 28.7K 45C 287K 45D29.4 46X 294 46A 2.94K 46B 29.4K 46C 294K 46D30.1 47X 301 47A 3.01K 47B 30.1K 47C 301K 47D 30.9 48X 309 48A 3.09K 48B 30.9K 48C 309K 48D 1, 电阻常用封装 :0402 0603 0805 1206 1210 2010 2512 第 3页2,电阻常用阻值 :精度为 5%的电阻的电阻,, 以欧姆为单位的标称值 :1.0 5.6 33 160 820 3.9K 20K100K 510K 2.7M1.1 6.2 36 180 910 4.3K 22K110K 560K 3M1.2 6.8 39 200 1K 4.7K 24K 120K 620K 3.3M1.3 7.5 43 220 1.1K 5.1K 27K130K 680K 3.6M1.5 8.2 47 240 1.2K 5.6K 30K150K 750K 3.9M1.6 9.1 51 270 1.3K 6.2K 33K160K 820K 4.3M1.8 10 56 300 1.5K 6.6K 36K180K 910K 4.7M2.0 11 62 330 1.6K 7.5K 39K200K 1M 5.1M2.2 12 68 360 1.8K 8.2K 43K220K 1.1M 5.6M2.4 13 75 390 2K 9.1K 47K 240K 1.2M 6.2M 2.7 15 82 430 2.2K 10K 51K270K 1.3M 6.8M3.0 16 91 470 2.4K 11K 56K 300K 1.5M 7.5M 3.3 18 100 510 2.7K 12K 62K330K 1.6M 8.2M3.6 20 110 560 3K 13K 68K 360K 1.8M 9.1M 3.9 22 120 620 3.2K 15K 75K390K 2M 10M4.3 24 130 680 3.3K 16K 82K430K 2.2M 15M4.7 27 150 750 3.6K 18K 91K470K 2.4M 22M5.1 30精度为 1%的电阻的电阻,, 以欧姆为单位的标称值 :10 33 100 332 1K 3.32K 10.5K 34K 107K 357K 10.2 33.2 102 340 1.02K 3.4K 10.7K第 4页34.8K 110K 360K10.5 34 105 348 1.05K 3.48K 11K35.7K 113K 365K10.7 34.8 107 350 1.07K 3.57K 11.3K36K 115K 374K11 35.7 110 357 1.1K 3.6K 11.5K 36.5K 118K 383K 11.3 36 113 360 1.13K 3.65K 11.8K37.4K 120K 390K11.5 36.5 115 365 1.15K 3.74K 12K38.3K 121K 392K11.8 37.4 118 374 1.18K 3.83K 12.1K39K 124K 402K12 38.3 120 383 1.2K 3.9K 12.4K 39.2K 127K 412K 12.1 39 121 390 1.21K 3.92K 12.7K40.2K 130K 422K12.4 39.2 124 392 1.24K 4.02K 13K41.2K 133K 430K12.7 40.2 127 402 1.27K 4.12K 13.3K42.2K 137K 432K13 41.2 130 412 1.3K 4.22K 13.7K 43K 140K 442K 13.3 42.2 133 422 1.33K 4.32K 14K43.2K 143K 453K13.7 43 137 430 1.37K 4.42K 14.3K44.2K 147K 464K14 43.2 140 432 1.4K 4.53K 14.7K 45.3K 150K 470K 14.3 44.2 143 442 1.43K 4.64K 15K46.4K 154K 475K14.7 45.3 147 453 1.47K 4.7K 15.4K47K 158K 487K15 46.4 150 464 1.5K 4.75K 15.8K 47.5K 160K 499K15.4 47 154 470 1.54K 4.87K 16K48.7K 162K 511K15.8 47.5 158 475 1.58K 4.99K 16.2K49.9K 165K 523K16 48.7 160 487 1.6K 5.1K 16.5K 51K 169K 536K16.2 49.9 162 499 1.62K 5.11K 16.9K51.1K 174K 549K16.5 51 165 510 1.65K 5.23K 17.4K第 5页52.3K 16.9 53.6K 17.4 54.9K 17.8 56K 18 56.2K 18.2 57.6K 18.7 59K 19.1 60.4K 19.6 61.9K 20 62K 20.5 63.4K 21 64.9K 21.5 66.5K 22 68K 22.1 68.1K 22.6 69.8K 23.2 71.5K 23.7 73.2K 24 75K 24.3 76.8K 24.7 78.7K 24.9 80.6K 25.5 75.5 73.2 69.8 68.1 66.5 63.4 61.9 59 57.6 56.2 56 53.6 51.1 178K 169 560K 511 1.69K 5.36K 17.8K 180K 52.3 182K 562K 174 576K 178 536 590K 180 604K 182 560 1.82K 5.76K 19.1K 549 1.8K 5.62K 18.7K 1.78K 5.6K 18.2K 523 1.74K 5.49K 18K 187K 54.9 191K 196K 187 200K 191 205K 619K 562 620K 565 634K 196 578 1.96K 6.19K 20.5K 1.91K 6.04K20K 1.87K 5.9K 19.6K 210K 60.4 649K 200 215K 205 680K 210 221K 215 698K 220 232K 221 732K 226 665 2.26K 6.98K 23.7K 715K 649 2.21K 6.81K 23.2K 634 2.2K 6.8K 22.6K 681K 620 2.15K 6.65K 22.1K 619 2.1K 6.49K 22K 590 665K 604 2.05K 6.34K 21.5K 2K 6.2K 21K 220K 62 226K 64.9 237K 68 240K 750K 232 680 768K 237 787K 240 255K 243 820K 249 732 2.49K 7.87K 26.1K 806K 715 2.43K 7.68K 25.5K 698 2.4K 7.5K 24.9K 681 2.37 7.32K 24.3K 2.32K 7.15K 24K 243K 249K 71.5 261K 75 267K 825K 255 845K 261 768 2.61K 8.2K 27K 750 2.55K 8.06K 26.7K 270K 76.8 第6页82K 26.1 82.5K 26.7 84.5K 27 86.6K 27.4 88.7K 28 90.9K 28.7 91K 29.4 93.1K 30 95.3K 30.1 97.6K 30.9 100K 31.6 102K 32.4 105K 97.6 95.3 93.1 91 86.6 82.5 82 78.7 280K 80.6 274K 267 887K 270 287K 866K 787 2.67K 8.25K 27.4K 806 909K 274 820 2.7K 8.45K 28K 2.74K 8.66K 28.7K 294K 280 300K 84.5 301K 294 910K 825 931K 287 953K 866 976K 300 887 1.0M 301 1.5M 309 910 3.09K 9.53K 32.4K 909 3.01K 9.31K 31.6K 3.0K 9.1K 30.9K 2.94K 9.09K 30.1K 845 2.87K 8.87K 30K 2.8K 8.8K 29.4K 309K 88.7 316K 90.9 324K 330K 316 332K 324 340K 330 2.2M 931 3.16K9.76K 33K 953 3.24K 10K 33.2K 976 3.3K 10.2K 33.6K 348K 第7页。

Features•Low-Voltage and Standard-Voltage Operation–5.0 (V CC = 4.5V to 5.5V)–2.7 (V CC = 2.7V to 5.5V)–2.5 (V CC = 2.5V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Low-Power Devices (ISB= 2=µA @ 5.5V) Available•Internally Organized 4096 x 8, 8192 x 8•2-Wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression•Bidirectional Data Transfer Protocol•100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate•Write Protect Pin for Hardware Data Protection•32-Byte Page Write Mode (Partial Page Writes Allowed)•Self-Timed Write Cycle (10 ms max)•High Reliability–Endurance: 1 Million Write Cycles–Data Retention: 100 Years–ESD Protection: >3,000V•Automotive Grade and Extended Temperature Devices Available•8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,and 8-pin TSSOP PackagesDescriptionThe AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Pin ConfigurationsPin Name FunctionA0 - A2Address InputsSDA Serial DataSCL Serial Clock InputWP Write Protect8-Pin PDIP8-Pin SOIC8-Pin TSSOPBlock DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus sys-tem (device addressing is discussed in detail under theDevice Addressing section). When the pins are not hard-wired, the default A 2, A 1, and A 0 are zero.WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC , all write operations to the upper quandrant (8/16K bits) of memory are inhibited. If left unconnected,WP is internally pulled down to GND.Memory OrganizationAT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256 pages of 32 bytes each. Ran-dom word addressing requires a 12/13 bit data word address.Absolute Maximum Ratings*Operating Temperature..................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mAAT24C32/64Note:1.This parameter is characterized and is not 100% tested.Notes:1.V IL min and V IH max are reference only and are not tested.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VDC CharacteristicsApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AC = 0°C to +70°C,V CC = +1.8V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 2.7 5.5V V CC4Supply Voltage 4.55.5V I CC1Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC2Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current (1.8V option)V CC = 1.8V V IN = V CC or V SS0.1µAV CC = 5.5V 2.0I SB2Standby Current (2.5V option)V CC = 2.5V V IN = V CC or V SS0.5µA V CC = 5.5V 2.0I SB3Standby Current (2.7V option)V CC = 2.7V V IN = V CC or V SS 0.5µA V CC = 5.5V 2.0I SB4Standby Current (5V option)V CC = 4.5 - 5.5V V IN = V CC or V SS2035µA I LI Input Leakage CurrentV IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2VNote: 1.This parameter is characterized and is not 100% tested. Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is nor-mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing dia-gram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are seri-ally transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.STANDBY MODE: The AT24C32/64 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow-ing these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.AC CharacteristicsApplicable over recommended operating range from T A = -40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).Symbol Parameter1.8-volt2.7-, 2.5-volt 5.0-voltUnits Min Max Min Max Min Maxf SCL Clock Frequency, SCL100100400kHz t LOW Clock Pulse Width Low 4.7 4.7 1.2µs t HIGH Clock Pulse Width High 4.0 4.00.6µs t I Noise Suppression Time(1)10010050ns t AA Clock Low to Data Out Valid0.1 4.50.1 4.50.10.9µst BUF Time the bus must be freebefore a new transmission can start(1)4.7 4.7 1.2µst HD.STA Start Hold Time 4.0 4.00.6µs t SU.STA Start Set-up Time 4.7 4.70.6µs t HD.DAT Data In Hold Time000µs t SU.DA T Data In Set-up Time200200100ns t R Inputs Rise Time(1) 1.0 1.00.3µs t F Inputs Fall Time(1)300300300ns t SU.STO Stop Set-up Time 4.7 4.70.6µs t DH Data Out Hold Time10010050ns t WR Write Cycle Time201010msEndurance(1) 5.0V, 25°C, Page Mode1M1M1MWrite CyclesAT24C32/64Bus TimingSCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingSCL: Serial Clock, SDA: Serial Data I/ONote: 1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/writecycle.Data ValidityStart and Stop DefinitionOutput AcknowledgeAT24C32/64Device AddressingThe 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write opera-tion select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state.NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. A low-V CC detector (5-volt option) resets the device to prevent data corruption in a noisy envi-ronment.DATA SECURITY: The AT24C32/64 has a hardware data protection scheme that allows the user to write protect the upper quadrant (8/16K bits) of memory when the WP pin is at V CC.Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcon-troller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 5 bits are internally incre-mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, inter-nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are dis-abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.Read OperationsRead operations are initiated the same way as write opera-tions with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed dur-ing the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ:Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives anacknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteNotes: 1.* = DON’T CARE bits2.† = DON’T CARE bits for the 32KAT24C32/64 Figure 4. Current Address ReadFigure 5. Random ReadNote: 1.* = DON’T CARE bitsFigure 6. Sequential ReadAT24C32 Ordering Informationt WR (max)(ms)I CC (max)(µA)I SB (max)(µA)f MAX(kHz)Ordering Code Package Operation Range10300035400A T24C32-10PCA T24C32N-10SCA T24C32W-10SC 8P38S18S2Commercial(0°C to 70°C)300035400A T24C32-10PIA T24C32N-10SIA T24C32W-10SI 8P38S18S2Industrial(-40°C to 85°C)1015000.5100A T24C32-10PC-2.7A T24C32N-10SC-2.7A T24C32W-10SC-2.78P38S18S2Commercial(0°C to 70°C)15000.5100A T24C32-10PI-2.7A T24C32N-10SI-2.7A T24C32W-10SI-2.78P38S18S2Industrial(-40°C to 85°C)1010000.5100A T24C32-10PC-2.5A T24C32N-10SC-2.5A T24C32W-10SC-2.58P38S18S2Commercial(0°C to 70°C)10000.5100A T24C32-10PI-2.5A T24C32N-10SI-2.5A T24C32W-10SI-2.58P38S18S2Industrial(-40°C to 85°C)108000.1100A T24C32-10PC-1.8A T24C32N-10SC-1.8A T24C32W-10SC-1.88P38S18S2Commercial(0°C to 70°C)8000.1100A T24C32-10PI-1.8A T24C32N-10SI-1.8A T24C32W-10SI-1.88P38S18S2Industrial(-40°C to 85°C)Package Type8P38-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S28-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)OptionsBlank Standard Operation (4.5V to 5.5V)-2.7Low Voltage (2.7V to 5.5V)-2.5Low Voltage (2.5V to 5.5V)-1.8Low Voltage (1.8V to 5.5V)AT24C32/64AT24C64 Ordering Informationt WR (max)(ms)I CC (max)(µA)I SB (max)(µA)f MAX (kHz)Ordering Code Package Operation Range 10300035400A T24C64-10PC A T24C64N-10SC A T24C64W-10SC A T24C64-10TC 8P38S18S28T Commercial (0°C to 70°C)300035400A T24C64-10PI A T24C64N-10SI A T24C64W-10SI A T24C64-10TI 8P38S18S28T Industrial (-40°C to 85°C)1015000.5100A T24C64-10PC-2.7A T24C64N-10SC-2.7A T24C64W-10SC-2.7A T24C64-10TC-2.78P38S18S28T Commercial (0°C to 70°C)15000.5100A T24C64-10PI-2.7A T24C64N-10SI-2.7A T24C64W-10SI-2.7A T24C64-10TI-2.78P38S18S28T Industrial (-40°C to 85°C)1010000.5100A T24C64-10PC-2.5A T24C64N-10SC-2.5A T24C64W-10SC-2.5A T24C64-10TC-2.58P38S18S28T Commercial (0°C to 70°C)10000.5100A T24C64-10PI-2.5A T24C64N-10SI-2.5A T24C64W-10SI-2.5A T24C64-10TI-2.58P38S18S28T Industrial (-40°C to 85°C)108000.1100A T24C64-10PC-1.8A T24C64N-10SC-1.8A T24C64W-10SC-1.8A T24C64-10TC-1.88P38S18S28T Commercial (0°C to 70°C)8000.1100A T24C64-10PI-1.8A T24C64N-10SI-1.8A T24C64W-10SI-1.8A T24C64-10TI-1.88P38S18S28TIndustrial (-40°C to 85°C)AT24C32/6412Packaging Information© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. 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AT24C32DI2C-Compatible (2-Wire) Serial EEPROM32-Kbit (4,096 x 8)DATASHEET Features●Low-voltage and Standard-voltage OperationV CC = 1.7V to 5.5V●Internally Organized as 4,096 x 8 (32K)●I2C-compatible (2-Wire) Serial Interface●Schmitt Trigger, Filtered Inputs for Noise Suppression●Bidirectional Data Transfer Protocol●400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility●Write Protect Pin for Hardware Protection●32-byte Page Write ModePartial Page Writes Allowed●Self-timed Write cycle (5ms Max)●High ReliabilityEndurance: 1,000,000 Write CyclesData Retention: 100 Years●Lead-free/Halogen-free devices Available●Green Package Options (Pb/Halide-free/RoHS Compliant)8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-leadSOT23, 5-ball WLCSP, and 8-ball VFBGA packages●Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers DescriptionThe Atmel® AT24C32D provides 32,768 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 4,096 words of 8 bits each. The device’s cascading feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-lead SOT23, 5-ball WLCSP, and 8-ball VFBGA packages. In addition, this device operates from 1.7V to 5.5V.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201621.Pin Configurations and PinoutsTable 1-1.Pin Configuration Note:When using the 5-lead SOT-23 or the 5-ball WLCSP , the software bits A2, A1, and A0 must be set to Logic 0 to properly communicate with the device.2.Absolute Maximum Ratings*8-pad UDFN/XDFNV CC WP SCL SDAA 0A 1A 2GND123487658-ball VFBGABottom View8-lead SOIC8-lead TSSOPTop View12348765A 0A 1A 2GNDV CC WP SCL SDATop View Top ViewA 0A 1A 2GND V CC WP SCL SDA87651234SCL GND SDA123545-lead SOT23WPV CC* Note: Drawings are not to scale5-ball WLCSPBall Side View(1)A 0A 1A 2GNDV CC WP SCL SDA12348765(1)Operating Temperature . . . . . . . . . . .-55°C to +125°C Storage Temperature . . . . . . . . . . . . -65°C to + 150°C Voltage on any pinwith respect to ground . . . . . . . . . . . . . . .-1.0 V +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA*Notice:Stresses beyond those listed under “AbsoluteMaximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.3AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220163.Block Diagram4.Pin DescriptionsSerial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device.Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.Device Addresses (A 2, A 1, A 0): The A 2, A 1, and A 0 pins are device address inputs that are hard wired (directly to GND or to V CC ) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 32K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing” on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A 2, A 1, and A 0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is connected directly to V CC , all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND; however, due to capacitive coupling that may appear during customerapplications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Table 4-1.Write ProtectV CC GND WP SCL SDAA 2A 1A 0AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201645.Memory OrganizationAT24C32D, 32K Serial EEPROM : The 32K is internally organized as 128 pages of 32-bytes each. Random word addressing requires a 12-bit data word address.5.1Pin CapacitanceTable 5-1.Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.5.2DC CharacteristicsTable 5-2.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from: T A = 25°C, f = 1.0MHz, V CC = 5.5V.Applicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V (unless otherwise noted).5AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220165.3AC CharacteristicsTable 5-3.AC Characteristics (Industrial Temperature)Notes:1.This parameter is ensured by characterization and is not 100% tested.2.AC measurement conditions:●R L (connects to V CC ): 1.3k Ω (2.5V, 5.5V), 10k Ω (1.7V)●Input pulse voltages: 0.3V CC to 0.7V CC ●Input rise and fall times: ≤ 50ns ●Input and output timing reference voltages: 0.5 x V CCApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V, CL = 100pF (unless otherwise noted). Test conditions are listed in Note 2.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201666.Device OperationClock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop condition as defined below.Figure 6-1.Data ValidityStart Condition : A high-to-low transition of SDA with SCL high is a Start condition that must precede every command.Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop condition will place the EEPROM in a standby power mode.Figure 6-2.Start Condition and Stop Condition DefinitionSDASCLData ChangeData StableData StableSDASCLStart Condition Stop Condition7AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero response is referred to as an Acknowledge.Figure 6-3.Output AcknowledgeStandby Mode: AT24C32D features a low-power standby mode that is enabled upon power-up and after the receipt of the Stop condition and the completion of any internal operations.Software Reset : After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps:1.Create a Start condition (if possible).2.Clock nine cycles.3.Create another Start condition followed by Stop condition as shown below.The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device.Figure 6-4.Software ResetSCLData InData OutStart ConditionAcknowledge981SCLSDAAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220168Figure 6-5.Bus TimingFigure 6-6.Write Cycle TimingNote: 1.The Write cycle time t WR is the time from a valid Stop condition of a Write sequence to the end ofthe internal Clear/Write cycle.SCLSDA InSDA OutSCLSDAStop ConditionStart Condition9AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220167.Device AddressingThe 32K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a Read or Write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant bits which is known as the device type identifier. These four bits are bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1. This is common to all 2-wire Serial EEPROM devices.The next three bits are the A2, A1, and A0 hardware address select bits which allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins, A 2, A 1, and A 0. The A 2, A 1, and A 0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.When utilizing the 5-ball WLCSP or the 5-lead SOT-23 packages, the A 2, A 1, and A 0 pins are not available. The A 2, A 1, and A 0 pins are internally pulled to ground and thus the A2, A1, and A0 device address bits must always be set to a Logic 0 to communicate with the device. This condition is depicted in Figure 7-1 below.The eighth bit of the device address is the Read/write operation select bit. A Read operation is initiated if this bit is a Logic 1, and a Write operation is initiated if this bit is a Logic 0.Upon a successful comparison of the device address, the EEPROM will output a zero during the following clock cycle. If a compare is not made, the device will not acknowledge and will instead return to a standby state.Figure 7-1.Device AddressingData Security: The AT24C32D has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC .AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016108.Write OperationsByte Write : A Write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, must then terminate the write sequence with a Stop condition. At this time, the EEPROM enters an internally-timed Write cycle, t WR , to the nonvolatile memory (See Figure 6-6). All inputs are disabled during this Write cycle and the EEPROM will not respond until the Write is complete.Figure 8-1.Byte WriteNote:* = Don’t care bit.Page Write: The 32K EEPROM is capable of 32-byte Page Writes.A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the Page Write sequence with a Stop condition.The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.Figure 8-2.Page WriteNote:* = Don’t care bit.Acknowledge Polling : Once the internally-timed Write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM respond with a zero, allowing the Read or Write sequence to continue.S T A R TW R I T ES T O PDevice Address FirstWord Address Second Word AddressDataSDA LineM S BA C KR /W A C KA C KA CKSDA LineS T A W R I BK/W KKKKS T9.Read OperationsRead operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the device address word is set to one. There are three Read operations:●Current Address Read ●Random Address Read ●Sequential ReadCurrent Address Read : The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by theEEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a Stop condition.Figure 9-1.Current Address ReadRandom Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address with the Read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-2.Random ReadNote:* = Don’t care bit.SDA LineS T A R TDevice AddressR E A DS T O PM S BA C KR /W N O A C KDataSDA LINES T A R TS T A R TR E A DW R I T ES T O PDevice Address Second Word Address Device AddressFirst Word Address Data (n)M S BA C KA C KAC KL S B A C KN O A C KR /W Dummy WriteR /W12Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address maximum address is reached, the data word address will roll-over and the Sequential Read will continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-3.Sequential ReadNote:* = Don’t care bit.SDA LINESTARTSTARTREADWRITESTOP DeviceAddressSecond WordAddressDeviceAddressFirst WordAddressData (n + 1)Data (n + 2)Data (n + x)Data (n)MSBACKACKACKLSBACKACKACKACKNOACKR/WDummy Write. . .. . .R/AT24C32D [DATASHEET]10.Ordering Code DetailAtmel DesignatorProduct FamilyDevice DensityDevice RevisionShipping Carrier OptionOperating VoltagePackage Option32 = 32K24C = Standard I 2C-compatibleSerial EEPROMB = Bulk (Tubes)T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity OptionM = 1.7V to 5.5VSS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN ST = SOT23U = 5-ball, 3x3 Grid Array, WLCSP C = VFBG A WWU = Wafer UnsawnWDT = Die in Tape and ReelPackage Device Grade or Wafer/Die ThicknessH = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C)U = Green, Matte Sn Lead Finish or SnAgCu Solder Ball Finish, Industrial Temperature Range (-40°C to +85°C)11= 11mil Wafer ThicknessA T 24C 32D -S S H M -TAT24C32D [DATASHEET]1411.Part MarkingsNotes: 1.WLCSP Package: CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells. Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet lightdoes not occur.2.Contact Atmel Sales for Wafer sales.13.18S1 — 8-lead JEDEC SOICAT24C32D [DATASHEET]1613.28X — 8-lead TSSOP13.38MA2 — 8-pad UDFNAT24C32D [DATASHEET] 1813.48ME1 — 8-pad XDFNAT24C32D [DATASHEET]2013.55TS1 — 5-lead SOT2321AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201613.65U-3 — 5-ball, WLCSPAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220162213.78U2-1 — 8-ball VFBGA23AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201614.Revision HistoryX X X X X XAtmel Corporation1600 Technology Drive, San Jose, CA 95110 USAT: (+1)(408) 441.0311F: (+1)(408) 436.4200|© 2015 Atmel Corporation. / Rev.: Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016.Atmel ®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities ®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 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