Datasheet_CY8CTMA340_Brief

SpecificationForLTCC 3dB Hybrid Coupler Model Name : RCP890A03RN2 Technologies co., Ltd.RN2 Technologies co., Ltd.284-2, Galgot-ri, Jinwe-myeon, Pyeongtaek-si, Kyunggi-do, KOREA Phone : (+82) 31 - 376 - 5400FAX : (+82) 31 - 376 - 9151 Distributor:Shenzhen Jushou electronics Co., Ltd.6F,building3,Sege science park, futian shenzhen Tel: 0086-0755-******** Mobile:0086-136******** Email: Fisher@Contact:Mr yu1. Description1-1. Part number: RCP890A031-2. Features- Hybrid Coupler 3dB, 90˚- Surface mount type- Suitable for operation frequency 815~960MHz- RoHS compliance- High stability in temperature and humidity for LTCC base - Low loss for Silver(Ag) conductor- Miniature size and high power capability- Lead-free alloy solderable- Thermal expansion corresponding with common substrate 2. Electrical SpecificationFreq. (MHz) Amplitude Balancemax (dB)Isolationmin (dB)Insertion Lossmax (dB)815-960 ±0.15 -23 -0.15VSWR MaxPhase(degrees)Power CapacityAvg. (Watt)Operating Temp.(℃)1.2 90 ±2.0 200 -55 to +1253. Mechanical Specification 3-1. Outline Dimension3-2. Weight- 1.35 Grams typical4. Port ConfigurationConfiguration Port 1 Port 2 Port 3 Port 4Case 1. Input Isolated Coupling-3dB, 0˚Output-3dB, -90˚Case 2. Isolated Input Output-3dB, 90˚Coupling -3dB, 0˚Case 3. Coupling-3dB, 0˚Output-3dB, 90˚Input IsolatedCase 4.Output-3dB, 90˚Coupling-3dB, 0˚Isolated Input * Once Port 1 is determined, the other three ports are defined automatically.5. Schematic DrawingPort1P inP cou P out P isoPort3 Port4Port26. Typical Performance Data (25℃)Return Loss [dB]Freq. [MHz]Coupling[dB]Out [dB] IL [dB]Amp.Bal.[dB]Phase[degree]S11 S22 S33 S44815 -3.12 -3.07 -0.09 ±0.02 -90.22 -26.15 -27.56 -26.33 -25.85 820 -3.11 -3.08 -0.08 ±0.02 -90.19 -26.37 -27.85 -26.56 -26.07 830 -3.11 -3.10 -0.09 ±0.00 -90.21 -26.85 -28.42 -27.07 -26.52 840 -3.09 -3.11 -0.09 ±0.01 -90.27 -27.34 -29.01 -27.61 -26.97 850 -3.09 -3.13 -0.10 ±0.02 -90.36 -27.92 -29.68 -28.18 -27.47 860 -3.08 -3.13 -0.09 ±0.03 -90.31 -28.50 -30.34 -28.82 -27.99 870 -3.07 -3.13 -0.09 ±0.03 -90.36 -29.12 -31.06 -29.44 -28.53 880 -3.06 -3.14 -0.09 ±0.04 -90.39 -29.81 -31.71 -30.12 -29.12 890 -3.07 -3.16 -0.11 ±0.05 -90.38 -30.50 -32.40 -30.84 -29.72 900 -3.06 -3.14 -0.09 ±0.04 -90.39 -31.22 -32.98 -31.48 -30.27 910 -3.06 -3.14 -0.09 ±0.04 -90.43 -31.95 -33.45 -32.22 -30.88 920 -3.06 -3.16 -0.10 ±0.05 -90.46 -32.69 -33.70 -32.94 -31.45 930 -3.06 -3.15 -0.09 ±0.04 -90.54 -33.41 -33.71 -33.55 -31.92 940 -3.07 -3.14 -0.10 ±0.04 -90.48 -34.05 -33.48 -34.03 -32.38 950 -3.07 -3.13 -0.09 ±0.03 -90.51 -34.53 -33.00 -34.41 -32.73 960 -3.08 -3.14 -0.10 ±0.03 -90.55 -34.72 -32.38 -34.50 -32.89* Data with PCB and Connector Loss ( 0.89 GHz = 0.03dB )7. Operation Temperature Curve (a)RCP650A03 Return Loss(Port1)M a g n i t u d e [d B ]Frequency[MHz]RCP890A03 Return Loss(Port2)M a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Return Loss(Port3)M a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Return Loss(Port4)M a g n i t u d e [d B ]Frequency[MHz]8. Operation Temperature Curve (b)70080090010001100RCP890A03 Coupling & Transmission LossM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Insertion LossM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 IsolationM a g n i t u d e [d B ]Frequency[MHz]70080090010001100RCP890A03 Phase BalanceP h a s e [d e g ]Frequency[MHz]9. Test Method- Refer to ‘Case 1’ of ‘4. Port Configuration’ on page 4 - Have the network analyzer calibrated properly.- Measure the data of Coupling through port 1 to port 3. (S31) - Measure the data of Transmission through port 1 to port 4. (S41) - Measure the data of Isolation through port 1 to port 2. (S21)- Calculate the Insertion Loss and Amplitude Balance of coupler on the below power method formula.in out P cou : Power of Coupling Port P iso : Power of Isolated Port10. Measurement board layout11. Recommended PCB layout and Solder mask pattern12. Reflow profilePeakSoakingUpPre-HeatingRamp℃ T1:160±5℃ T2:180±5℃ T4:260±5℃ T3:230±5℃Temp.[]Time [sec] t1:60±5sec t2:100±15sec t3:30±5sec t4:60±10sec13. Using note for LTCC CouplersI.Be careful when transportingA.Excessive stress or shock may make products broken or cracked due to the nature ofceramics structure.B.The products cracked or damaged on terminals may have their property changed.II.Be careful during storageA.Store the products in the temperature of -55 ~ 125℃B.Keep the humidity at 45 ~ 75% around the products.C.Prevent corrosive gas (Cl2, NH3, SO X, NO X, etc.) from contacting the products.D.It is recommended to use the products within 6 months of receipt. If the period exceeds6 months, solderability may need to be verified.III.Be careful when solderingA.All the ground terminals, IN and OUT pad of coupler should be soldered on the groundplane of the PCB.B.Products may be cracked or broken by uneven forces from a claw or suction device.C.Mechanical stress by any other devices may damage products when positioning them onPCB.D. A dropped product is recommended not to be used.E.Soldering must be carried out by the condition of specification sheet.F.Any couplers which are de-soldered from PCB should not be used again.14. Packaging15. Environmental ReliabilityITEM PROCEDURE REQUIREMENTS/RESULTTemperature Cycle (Thermal Shock)1. One cycle : 30 minutesStep 1 : 125 ± 5 for 15 minutesStep 2 : -55 ± 5 for 15 minutes2. Time to approach low or high temperature: 10 seconds3. Number of Cycles : 100 cycles4. Keep normal temperature for 1 hour.1. Meet the electrical Specification after testSolderability1. Solder : 230 ± 5°C for 5± 1 sec. 1. More than 85% of the I/Oelectrode pad shall be covered with solder.Heat Resistance 1. Temperature : 100 ± 2 °C 2. Duration : 96 ± 2 hours 1. Meet the electrical Specification after testLow Temp. Resistance1. Temperature : -55 ± 5 °C2. Duration : 24 ± 2 hours 1. Meet the electrical Specification after testVibration Resistance1. Frequency: 5~ 15MHz2. Acceleration : 10g3. Sweep Time: 0.1 oct/min, 15min/axis4. Axis : X, Y and Z direction 1. No appearance damage 2. Meet the electrical Specification after testHumidity Resistance1. One Cycle :Step1:increase Temperature -25~65°C for 2hours with humidity 85%Step2:Maintain for 4 hour after increasing Humidity 90% to 95%Step3: Decrease Temperature 65°C to 25°C 2. Number of Cycles : 103. Maintain for 3hour after decreasing temperature -10°C 1. Meet the electrical Specification after testDrop Shock 1. Dropped onto hard wood from height of 50 cm for 5 times; each x, y and z direction except I/O direction.1. No appearance damage2. Meet the electrical Specification after test16. RoHS test result-RN2 Technologies warrants and represents as follows.。

CY62157ELL-45ZSXI8-Mbit (512K x 16) Static RAMCY62157E MoBL ®Features•Very high speed: 45 ns •Wide voltage range: 4.5V–5.5V •Ultra-low standby power —Typical Standby current: 2 µA—Maximum Standby current: 8 µA (Industrial)•Ultra-low active power— Typical active current: 1.8 mA @ f = 1 MHz •Ultra-low standby power•Easy memory expansion with CE 1, CE 2 and OE features •Automatic power-down when deselected •CMOS for optimum speed/power•Available in Pb-free 44-pin TSOP II and 48-ball VFBGA packageFunctional Description [1]The CY62157E is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current.This is ideal for providing More Battery Life ™ (MoBL ®) in portable applications such as cellular telephones. The devicealso has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling.The device can also be put into standby mode when deselected (CE 1 HIGH or CE 2 LOW or both BHE and BLE are HIGH). The input/output pins (IO 0 through IO 15) are placed in a high-impedance state when: deselected (CE 1HIGH or CE 2LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH),or during a write operation (CE 1 LOW, CE 2 HIGH and WE LOW).Writing to the device is accomplished by taking Chip Enable (CE 1 LOW and CE 2 HIGH) and Write Enable (WE) input LOW.If Byte Low Enable (BLE) is LOW, then data from IO pins (IO 0through IO 7), is written into the location specified on the address pins (A 0 through A 18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO 8 through IO 15) is written into the location specified on the address pins (A 0 through A 18).Reading from the device is accomplished by taking Chip Enable (CE 1 LOW and CE 2 HIGH) and Output Enable (OE)LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO 0 to IO 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO 8 to IO 15. See the truth table at the back of this data sheet for a complete description of read and write modes.Note:1.For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on .Logic Block Diagram512K x 16RAM ArrayIO 0–IO 7R O W D E C O D E RA 8A 7A 6A 5A 2COLUMN DECODERA 11A 12A 13A 14A 15S E N S E A M P SDATA IN DRIVERSOE A 4A 3IO 8–IO 15WEBLEBHE A 16A 0A 1A 17A 9BHE BLEA 10A 18POWER-DOWNCIRCUITCE 2CE 1CE 2CE 1CY62157E MoBL ®Pin Configuration [2, 3]Product PortfolioProduct Range V CC Range (V)Speed(ns)Power DissipationOperating I CC , (mA)Standby, I SB2(µA)f = 1MHz f = f max Min Typ [4]Max Typ [4]Max Typ [4]Max Typ [4]Max CY62157E-45Ind’l 4.5 5.0 5.545 1.83182528CY62157E-55[5]Auto4.55.05.555 1.841835230Notes:2.NC pins are not connected on the die.3.The 44-pin TSOP II package has only one chip enable (CE) pin.4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = V CC(typ), T A = 25°C.5.Automotive product information is Preliminary.WE A 11A 10A 6A 0A 3CE 1IO 10IO 8IO 9A 4A 5IO 11IO 13IO 12IO 14IO 15V SS A 9A 8OE Vss A 7IO 0BHE CE 2A 17A 2A 1BLE V CC IO 2IO 1IO 3IO 4IO 5IO 6IO 7A 15A 14A 13A 12NC A 18NC326541D E B A C F G HVFBGAA 16 NC Vcc Top View12345678911143132363534333740393812134144434216152930A 5181720192728252622212324TSOP II Top ViewA 6A 7A 3A 2A 1A 0A 17A 4A 9A 10A 11A 12A 15A 16OE BHE BLE CE WE IO 0IO 1IO 2IO 3IO 4IO 5IO 6IO 7IO 8IO 9IO 10IO 11IO 12IO 13IO 14IO 15V CC V CC V SS V SS 10A 18A 14A 8A 13CY62157E MoBL ®Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature ................................–65°C to + 150°C Ambient Temperature withPower Applied ...........................................–55°C to + 125°C Supply Voltage to GroundPotential ..........................................................–0.5V to 6.0V DC Voltage Applied to Outputsin High Z State [6, 7]...........................................–0.5V to 6.0VDC Input Voltage [6, 7]........................................–0.5V to 6.0V Output Current into Outputs (LOW) ............................20 mA Static Discharge Voltage ..........................................> 2001V (per MIL-STD-883, Method 3015)Latch-Up Current ...................................................> 200 mAOperating RangeDevice Range Ambient Temperature V CC [8]CY62157EIndustrial–40°C to +85°C4.5V to5.5VAutomotive –40°C to +125°CElectrical Characteristics (Over the Operating Range)Parameter Description Test Conditions45 ns (Industrial)55 ns (Automotive)Unit Min Typ [4]MaxMin Typ [4]MaxV OH Output HIGH Voltage I OH = –1 mA V CC = 4.5V 2.42.4V V OL Output LOW Voltage I OL = 2.1 mAV CC = 4.5V0.40.4V V IH Input HIGH Voltage V CC = 4.5V to 5.5V 2.2V CC + 0.5 2.2V CC + 0.5V V IL Input LOW Voltage V CC = 4.5V to 5.5V –0.50.8–0.50.8V I IX Input Leakage CurrentGND < V I < V CC–1+1–1+1µA I OZ Output Leakage Current GND < V O < V CC , Output Disabled –1+1–1+1µAI CCV CC Operating Supply Current f = f max = 1/t RC V CC = V CCmaxI OUT = 0 mACMOS levels 18251835mA f = 1 MHz1.83 1.84I SB1Automatic CE Power-Down Current — CMOS Inputs CE 1 > V CC − 0.2V, CE 2 < 0.2V,V IN > V CC – 0.2V, V IN < 0.2V, f = f max (Address and Data Only), f = 0 (OE, BHE, BLE and WE),V CC = 3.60V28230µAI SB2Automatic CE Power-Down Current — CMOS InputsCE 1 > V CC – 0.2V or CE 2 < 0.2V,V IN > V CC – 0.2V or V IN < 0.2V,f = 0, V CC = 3.60V28230µACapacitance [9]Parameter DescriptionTest ConditionsMax Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = V CC(typ)10pF C OUTOutput Capacitance10pFNotes:6.V IL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.7.V IH(max) = V CC + 0.75V for pulse durations less than 20 ns.8.Full device AC operation assumes a 100 µs ramp time from 0 to V CC (min) and 200 µs wait time after V CC stabilization.9.Tested initially and after any design or process changes that may affect these parameters.CY62157E MoBL ®Thermal Resistance [9]Parameter DescriptionTest ConditionsTSOP II VFBGA Unit ΘJA Thermal Resistance (Junction to Ambient)Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board7772°C/W ΘJCThermal Resistance (Junction to Case)138.86°C/WAC Test Loads and WaveformsParametersValues Unit R11800ΩR2990ΩR TH 639ΩV TH1.77VData Retention Characteristics (Over the Operating Range)Parameter DescriptionConditionsMin Typ [4]MaxUnit V DR V CC for Data Retention 2V I CCDR Data Retention Current V CC =2V, CE 1> V CC – 0.2V,CE 2 < 0.2V, V IN > V CC – 0.2V or V IN < 0.2VIndustrial 8µAAutomotive30t CDR [9]Chip Deselect to Data Retention Time0ns t R [10]Operation Recovery Timet RCnsData Retention Waveform [11]Notes:10.Full device operation requires linear V CC ramp from V DR to V CC(min) > 100 µs or stable at V CC(min) > 100 µs.11.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.3VV CC OUTPUTR230 pFINCLUDINGJIG AND SCOPEGND90%10%90%10%Rise Time = 1 V/nsFall Time = 1 V/nsOUTPUT VEquivalent to:THEVENIN EQUIVALENTALL INPUT PULSESR THR1V CC(min)t CDRV DR >2 VDATA RETENTION MODEt RV CC CE 1or BHE.BLECE 2V CC(min)CY62157E MoBL®Switching Characteristics Over the Operating Range[12]Parameter Description45 ns55 nsUnit Min Max Min MaxRead Cyclet RC Read Cycle Time4555nst AA Address to Data Valid4555nst OHA Data Hold from Address Change1010nst ACE CE1 LOW and CE2 HIGH to Data Valid4555nst DOE OE LOW to Data Valid2225nst LZOE OE LOW to LOW Z[13]55nst HZOE OE HIGH to High Z[13, 14]1820nst LZCE CE1 LOW and CE2 HIGH to Low Z[13]1010nst HZCE CE1 HIGH and CE2 LOW to High Z[13, 14]1820nst PU CE1 LOW and CE2 HIGH to Power-Up00nst PD CE1 HIGH and CE2 LOW to Power-Down4555nst DBE BLE/BHE LOW to Data Valid4555nst LZBE BLE/BHE LOW to Low Z[13]1010nst HZBE BLE/BHE HIGH to HIGH Z[13, 14]1820ns Write Cycle[15]t WC Write Cycle Time4555nst SCE CE1 LOW and CE2 HIGH to Write End3540nst AW Address Set-Up to Write End3540nst HA Address Hold from Write End00nst SA Address Set-Up to Write Start00nst PWE WE Pulse Width3540nst BW BLE/BHE LOW to Write End3540nst SD Data Set-Up to Write End2525nst HD Data Hold from Write End00nst HZWE WE LOW to High-Z[13, 14]1820nst LZWE WE HIGH to Low-Z[13]1010ns Notes:12.Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V CC(typ)/2, input pulselevels of 0 to V CC(typ), and output loading of the specified I OL/I OH as shown in the “AC Test Loads and Waveforms” section.13.At any given temperature and voltage condition, t HZCE is less than t LZCE, t HZBE is less than t LZBE, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for anygiven device.14.t HZOE, t HZCE, t HZBE, and t HZWE transitions are measured when the outputs enter a high-impedance state.15.The internal Write time of the memory is defined by the overlap of WE, CE1 = V IL, BHE and/or BLE = V IL, and CE2 = V IH. All signals must be ACTIVE to initiatea write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signalthat terminates the Write.CY62157E MoBL ®Switching WaveformsRead Cycle 1 (Address Transition Controlled)[16, 17]Read Cycle 2 (OE Controlled)[17, 18]Notes:16.The device is continuously selected. OE, CE 1 = V IL , BHE and/or BLE = V IL , and CE 2 = V IH .17.WE is HIGH for read cycle.18.Address valid prior to or coincident with CE 1, BHE, BLE transition LOW and CE 2 transition HIGH.PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHAADDRESSDATA OUT50%50%DATA VALIDt RCt ACEt DOEt LZOEt LZCEt PUHIGH IMPEDANCE t HZOEt PDt HZBE t LZBEt HZCEt DBEHIGH I CC I SBIMPEDANCEOECE 1ADDRESSV CC SUPPLY CURRENTBHE/BLEDATA OUT CE 2CY62157E MoBL ®Write Cycle 1 (WE Controlled)[15, 19, 20, 21]Write Cycle 2 (CE 1 or CE 2 Controlled)[15, 19, 20, 21]Notes:19.Data IO is high impedance if OE = V IH .20.If CE 1 goes HIGH and CE 2 goes LOW simultaneously with WE = V IH , the output remains in a high-impedance state.21.During this period, the IOs are in output state and input signals should not be applied.Switching Waveforms (continued)t HDt SDt PWEt SAt HAt AWt SCEt WCt HZOEVALID DATAt BWSee Note 21ADDRESSWEDATA IOOEBHE/BLECE 1CE 2t HDt SDt PWEt HAt AWt SCEt WCt HZOEVALID DATASee Note 21t BWt SACE 1ADDRESSWEDATA IOOEBHE/BLECE 2CY62157E MoBL ®Write Cycle 3 (WE Controlled, OE LOW)[20, 21]Write Cycle 4 (BHE/BLE Controlled, OE LOW)[20, 21]Switching Waveforms (continued)VALID DATAt HD t SDt LZWEt PWEt SA t HAt AWt SCEt WCt HZWEt BW See Note 21CE 1ADDRESSCE 2WEDATA IOBHE/BLEt HDt SDt SAt HAt AWt WCVALID DATAt BWt SCEt PWESee Note 21DATA IOADDRESSCE 1 WEBHE/BLECE 2CY62157E MoBL® Truth TableCE1CE2WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X X High Z Deselect/Power-Down Standby (I SB)X L X X X X High Z Deselect/Power-Down Standby (I SB) X X X X H H High Z Deselect/Power-Down Standby (I SB) L H H L L L Data Out (IO0–IO15)Read Active (I CC) L H H L H L Data Out (IO0–IO7);High Z (IO8–IO15)Read Active (I CC)L H H L L H High Z (IO0–IO7);Data Out (IO8–IO15)Read Active (I CC) L H H H L H High Z Output Disabled Active (I CC) L H H H H L High Z Output Disabled Active (I CC) L H H H L L High Z Output Disabled Active (I CC) L H L X L L Data In (IO0–IO15)Write Active (I CC) L H L X H L Data In (IO0–IO7);High Z (IO8–IO15)Write Active (I CC)L H L X L H High Z (IO0–IO7);Data In (IO8–IO15)Write Active (I CC) Ordering InformationSpeed(ns)Ordering Code PackageDiagram Package TypeOperatingRange45CY62157ELL-45ZSXI51-8508744-pin Thin Small Outline Package Type II (Pb-free)Industrial 55CY62157ELL-55ZSXE51-8508744-pin Thin Small Outline Package Type II (Pb-free)Automotive CY62157ELL-55BVXE51-8515048-ball Very Fine Pitch Ball Grid Array (Pb-free)Document #: 38-05695 Rev. *C Page 10 of 12Package Diagrams44-pin TSOP II (51-85087)51-85087-*ADocument #: 38-05695 Rev. *C Page 11 of 12© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.Package Diagrams (continued)Document #: 38-05695 Rev. *C Page 12 of 12Document History PageDocument Title: CY62157E MoBL ®, 8-Mbit (512K x 16) Static RAM Document Number: 38-05695REV.ECN NO.Issue Date Orig. of Change Description of Change **291273See ECN PCI New data sheet*A457689See ECNNXRAdded Automotive Product Removed Industrial ProductRemoved 35 ns and 45 ns speed bins Removed “L” binUpdated AC Test Loads tableCorrected t R in Data Retention Characteristics from 100 µs to t RC nsUpdated the Ordering Information and replaced the Package Name column with Package Diagram*B 467033See ECN NXRAdded Industrial Product (Final Information)Removed 48 ball VFBGA package and its relevant informationChanged the I CC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz Changed the I SB2(typ) value of Automotive from 5 µA to 1.8 µA Modified footnote #4 to include current limit Updated the Ordering Information table *C 569114See ECN VKNAdded 48 ball VFBGA package Updated Logic Block Diagram Added footnote #3Updated the Ordering Information tableCY62157ELL-45ZSXI。

——————————————产品特性隔离功能；“ISO 11898-24 V”标准； ； 个节点；具有极低电磁辐射和高的抗电磁干扰性；（设备人体放电方式±，浪涌（耦合方式±4kV 高低温特性好，满足工业级产品要求；产品数据手册广州致远电子股份有限公司—————————————订购信息————————————————————————————————典型应用1.1所示为CTM8251S 的应用示例，该模块可以连接任何一款CAN ISO 11898标准的CAN 节点间隔离收发功能。

在以往的设计方案中需要光耦、隔离、CAN 收发器等其他元器件才能实现带隔离的CAN 收发电路，但现在您只需利用一片CTM8251(A)S 接口模块就可以实现带隔离的CAN 收发电路，隔离电压可以2500VDC ，其接口简单，使用方便，是您组成嵌入式CAN 网络的理想选择。

图 1.1 CTM8251S 与传统分立器件方案对比图 2.1 CTM8251S和CTM8251AS实物图产品尺寸：长(L)×宽(W)×高(H)，19.90×19.90×5.00mm。

2.2 CTM8251(A)S引脚分布（底视图）2.1 CTM收发器引脚定义引脚名称1 VIN2 GND3 TXDCAN4 RXDCAN6 CANHCANH7 CANLCANL8 CANG 隔离电源输出地时，请悬空此引脚。

图 3.1 CTM8251S和CTM8251AS数据速率与电源对应输入电流图 3.2 串行接口（单通道）输入电流与数据速率对应关系绝缘特性CTM系列模块绝缘特性测试，温度：+25℃，各电压下的耐压测试时间为测试曲线如图所示：图 3.3 绝缘特性曲线图图 4.1 CTM8251S接口电路注：详细的应用见CTM8251S应用实例，CTM8251AS供电电源为3.3V。

网络拓扑结构图 4.2 CTM8251S典型应用如图 4.2所示CTM8251S与CTM8251S以及CTM8251AS等互连的应用实例，在同一个CAN-bus网络中，至少可连接110个CTM8251(A)S模块。

RatingSymbol Parameter N-Ch P-Ch Units V DS Drain-Source Voltage 40 -40 V V GS Gate-Sou r ce Voltage±20 ±20 V I D @T C =25℃ Continuous Drain Current, V GS @ 10V 1 23 -20 A I D @T C =100℃Continuous Drain Current, V GS @ 10V 118 -16 A I DM Pulsed Drain Current 246 -40 A EAS Single Pulse Avalanche Energy 328 66 mJ I AS Avalanche Current 17.8-27.2 A P D @T C =25℃Total Power Dissipation 425 31.3 W T STG Storage Temperature Range -55 to 150 -55 to 150 ℃ T JOperating Junction Temperature Range-55 to 150-55 to 150℃Symbol ParameterTyp.Max.UnitR θJA Thermal Resistance Junction-Ambient 1 --- 62 ℃/W R θJCThermal Resistance Junction-Case 1 --- 5 ℃/WBVDSS RDSON ID40V 26m Ω 23A -40V 40m Ω -20AThe UD4803 is the highest performance trench N-ch and P-ch MOSFETs with extreme high cell density , which provide excellent RDSON and gate charge for most of the synchronous buck converter applications . The UD4803 meet the RoHS and Green Product requirement 100% EAS guaranteed with full function reliability approved. zAdvanced high cell density Trench technology zSuper Low Gate Charge zExcellent CdV/dt effect decline z100% EAS Guaranteed z Green Device Available Featuresz High Frequency Point-of-Load Synchronous Buck Converter for MB/NB/UMPC/VGA z Networking DC-DC Power System z CCFL Back-light InverterTO252 Pin ConfigurationProduct SummerySymbol ParameterConditionsMin.Typ.Max.UnitBV DSSDrain-Source Breakdown VoltageV GS =0V , I D =250uA 40 --- --- V△BV DSS /△T J BVDSS Temperature Coefficient Reference to 25℃ , I D =1mA--- 0.034 --- V/℃V GS =10V , I D =12A --- 22 26R DS(ON)Static Drain-Source On-Resistance 2V GS =4.5V , I D =10A --- 28 35m ΩV GS(th) Gate Threshold Voltage 1.0 1.5 2.5 V △V GS(th) V GS(th) Temperature Coefficient V GS =V DS , I D =250uA --- -4.56 --- mV/℃V DS =32V , V GS =0V , T J =25℃ --- --- 1 I DSS Drain-Source Leakage Current V DS =32V , V GS =0V , T J =55℃ --- --- 5 uA I GSSGate-Source Leakage CurrentV GS =±20V , V DS =0V --- --- ±100nA gfs Forward Transconductance V DS =5V , I D =12A --- 8 --- S R g Gate Resistance V DS =0V , V GS =0V , f=1MHz --- 2.6 5.2 ΩQ gTotal Gate Charge (4.5V)---5.5---Q gs Gate-Source Charge --- 1.25 --- Q gd Gate-Drain Charge V DS =20V , V GS =4.5V , I D =12A--- 2.5 --- nC T d(on) Turn-On Delay Time --- 8.9 --- T r Rise Time--- 2.2 --- T d(off) Turn-Off Delay Time --- 41 --- T f Fall Time V DD =20V , V GS =10V , R G =3.3Ω I D =1A--- 2.7 --- nsC iss Input Capacitance --- 593 --- C oss Output Capacitance --- 76 --- C rss Reverse Transfer CapacitanceV DS =15V , V GS =0V , f=1MHz --- 56 ---pFSymbol ParameterConditionsMin.Typ.Max.UnitEASSingle Pulse Avalanche Energy 5V DD =25V , L=0.1mH , I AS =10A9 --- --- mJSymbol Parameter Conditions Min. Typ. Max.UnitI S Continuous Source Current 1,6 --- --- 23 AI SM Pulsed Source Current 2,6V G =V D =0V , Force Current --- --- 46 A V SD Diode Forward Voltage 2V GS =0V , I S =1A , T J =25℃ --- --- 1.2 VNote :1.The data tested by surface mounted on a 1 inch 2 FR-4 board with 2OZ copper.2.The data tested by pulsed , pulse width ≦ 300us , duty cycle ≦ 2%3.The EAS data shows Max. rating . The test condition is V DD =25V,V GS =10V,L=0.1mH,I AS =17.8A4.The power dissipation is limited by 150℃ junction temperature5.The Min. value is 100% EAS tested guarantee.6.The data is theoretically the same as I D and I DM , in real applications , should be limited by total power dissipation.Symbol ParameterConditionsMin.Typ.Max.UnitBV DSSDrain-Source Breakdown VoltageV GS =0V , I D =-250uA -40 --- --- V△BV DSS /△T J BV DSS Temperature Coefficient Reference to 25℃ , I D =-1mA--- -0.012 --- V/℃V GS =-10V , I D =-8A --- 32 40R DS(ON)Static Drain-Source On-Resistance 2V GS =-4.5V , I D =-4A ---52 65 m ΩV GS(th) Gate Threshold Voltage -1.0 -1.6 -2.5 V △V GS(th) V GS(th) Temperature Coefficient V GS =V DS , I D =-250uA --- 4.32 --- mV/℃V DS =-32V , V GS =0V , T J =25℃ --- --- 1 I DSS Drain-Source Leakage Current V DS =-32V , V GS =0V , T J =55℃ --- --- 5 uA I GSSGate-Source Leakage CurrentV GS =±20V , V DS =0V --- --- ±100nA gfs Forward Transconductance V DS =-5V , I D =-8A --- 12.6 --- SR g Gate Resistance V DS =0V , V GS =0V , f=1MHz --- 13 16 ΩQ gTotal Gate Charge (-4.5V)---9---Q gs Gate-Source Charge --- 2.54 --- Q gd Gate-Drain Charge V DS =-20V , V GS =-4.5V , I D =-12A--- 3.1 --- nC T d(on) Turn-On Delay Time --- 19.2 ---T r Rise Time --- 12.8 ---T d(off) Turn-Off Delay Time --- 48.6 --- T f Fall Time V DD =-15V , V GS =-10V , R G =3.3Ω, I D =-1A --- 4.6 --- nsC iss Input Capacitance --- 1004 ---C oss Output Capacitance --- 108 --- C rss Reverse Transfer CapacitanceV DS =-15V , V GS =0V , f=1MHz --- 80 ---pFSymbol ParameterConditionsMin.Typ.Max.UnitEASSingle Pulse Avalanche Energy 5V DD =-25V , L=0.1mH , I AS =-15A20 --- --- mJSymbol ParameterConditionsMin.Typ.Max.UnitI S Continuous Source Current 1,6 --- --- -20 AI SM Pulsed Source Current 2,6V G =V D =0V , Force Current --- --- -40 A V SDDiode Forward Voltage 2V GS =0V , I S =-1A , T J =25℃--- --- -1 VNote : 1.The data tested by surface mounted on a 1 inch 2FR-4 board with 2OZ copper. 2.The data tested by pulsed , pulse width ≦ 300us , duty cycle ≦ 2%3.The EAS data shows Max. rating . The test condition is V DD =-25V,V GS =-10V,L=0.1mH,I AS =-27.2A4.The power dissipation is limited by 150℃ junction temperature5.The Min. value is 100% EAS tested guarantee.6.The data is theoretically the same as I D and I DM , in real applications , should be limited by total power dissipation.1212101DSGS12T J ,Junction Temperature ( ℃)T J , Junction Temperature (℃)。

User ManualSCI340-HS Analog Hotplate Magnetic StirrerS CI-S Analog Magnetic StirrerPlease read the User Manual and the related Video of this instrument on our website carefully before use, and follow all operating and safety instructions!The website ContentsContents 1 Preface 2 Service 2 Warranty 21 Safety Instructions 32 Proper use 43 Inspection4 3.1 Receiving Inspection 43.2 Listing of Items 44 Trial run 55 Control and Display 56 Operation 67 Faults68 Maintenance and Cleaning 69 A ssociated Standards and Regulations 710 Technical data711 Products and Accessories 8PrefaceWelcome to the “MS-(H)-S Analog Hotplate Magnetic Stirrer User Manual”. Users should read this Manual carefully, follow the instructions and procedures, and beware of all the cautions when using this instrument.ServiceWhen help needed, you can always contact the sevice department of manufacturer for technical support in the following ways: SCILOGEX, LLC1275 Cromwell AveSuite C6Rocky Hill, CT 06067USATel：1- (860) 436-9221Fax：1- (860) 436-9745***************** Please provide the customer care representative with the following information:•Serial Number（on the rear panel）•Description of problem (i.e., hardware or software)•Methods and procedures adopted to resolve the problems •Your contact informationWarrantyYou have purchased a Scilogex instrument. This instrument is warranted to be free from defects in materials and workmanship under normal use and service, for a period of 24 months from the date of invoice. The warranty is extended only to the original purchaser. It shall not apply to any product or parts which have been damaged on account of improper installation, improper connections, misuse, accident or abnormal conditions of operation.For claims under the warranty please contact your local dealer. You may also send the instrument direct to our works, enclosing the invoice copy and by giving reasons for the claim. You would be solely liable for freight costs.1 Safety InstructionsWarning!•Read the operating instructions carefully before use the instrument.•Ensure that only trained staff work with the instrument.•Forbid to heat the substances with low- burning point or easy-volatile （MS-H-S）Risk of burn!•Caution when touching the housing parts and the heating plate. The heating plate can reach temperatures of 340 ℃.•Pay attention to the residual heat after switchingoff.Protective ground contact ！•Make sure that socket is earthed (protective ground contact) before use.•When work ，wear the personal guard to avoid the risk from:-Splashing and evaporation of liquids -Release of toxic or combustible gases.•Set up the instrument in a spacious area on an stable,clean, non-slip, dry and fireproof surface, do not operate the instrument in explosive atmospheres, with hazardoussubstances or under water.•Gradually increase the speed, reduce the speed if :-The stirring bar breakaway because of too high speed -The instrument is not running smoothly, or if the container moves on the base plate.•Temperature must always be set to at least 25 ℃ lower than the fire point of the media used.•Beware of hazards due to:-Flammable materials or media with a low boiling temperature -Overfilling of media -Unsafe container•Process pathogenic materials only in closed vessels.•If the case of the stirrer bar is PTFE,please note ：-Elemental fluorine, three fluoride and alkali metals will corrode the PTFE and Halogen alkanes make it expansion at room temperature- Molten alkali ，alkaline earth metals or their solution, as well as the powder in second and third ethnic of the periodic table of elements will have chemical reaction with PTFE when temperature reaches 300 ~ 400 ℃.• The voltage stated on the label must correspond to the main power supply.•Ensure that the mains power supply cable does not touch the hotplate. Do not cover the instrument.•The instrument may only be opened by experts.•Keep away from high magnetic field.•Observe the minimum distances between the devices, between the instruments and the wall and above theassembly (min. 100 mm).Figure 12 Proper useThe instrument is designed for schools, laboratories orfactories. This device is not suitable for use in residentialareas or other areas that may cause danger to the user orinstrument as mentioned in Chapter 1.3 Inspection3.1 Receiving InspectionUnpack the equipment carefully and check for any damageswhich may have arisen during transport. If it happens, pleasecontact manufacturer Limited for technical support.Note:If there is any apparent damage to the system,please do not plug it into the power line.3.2 Listing of ItemsThe packing includes the following items:Items QtyMain unit 1Power cable 15 Control and DisplayLED HeatHeating Knob (MS-H-S)Stirring KnobLED StirFigure 2Figure 3Stirrer bar 1User manual1Table 14 Trial run•Make sure the required operating voltage and power supply voltage match.•Ensure the socket must be earthed.•Ensure the power be off and the speed control knob and the temperature control knob to the lowest position •Plug in the power cable and power on the device.• Add the medium into the vessel with a stirring bar.•Put the vessel on the plate.•Set the rated stirring speed and the device begins to work.•Set the rated temperature and the device begins to work(MS-H-S).•Keep the temperature control knob and the speed control knob slowly to the lowest position to turn off the function.If these operations above are normal, the device is ready to operate. If these operations are not normal, the device may be damaged during transportation, please contact DragonLab corporation for technical support.Items DescriptionsStir knob Set the rated rotary speed in the safe stirring range from 0 to 1500 rpm. The function “Stirring” is switched ON or OFF via the knobHeat knob (MS-H-S)Set the rated temperature in the safe temperature range from room temperature to 340 ℃. The function “heating” is switched ON or OFF via the knob.LED heating Lit when heatingLED Power When the device is switched ON, theLED power is lit.Mains switch Switch ON or OFF.Table 26 Operation•Put the device on the stable and safe place，ensure the speed control knob and the temperature control knob to the lowest position and plug in the mains power.•Turn ON the power switch.•Turn the speed control knob regulation to set the rated rotary speed in the safe speed limit from 0 to 1500 rpm.•Turn the temperature control knob regulation to set the rated temperature in the safe limit from 0 to 340℃.(MS-H-S)•The instrument begins to work.Note：Forbid to transfer the vessel when the instrumentworking，or you must restart Stir function again,avoiding Stirring bar breakaway.7 Faults•If a unit fault happens, please power down the instrument.•Switch OFF the unit at the main ON/OFF switch for a few seconds.•The stirring function will continue to operate at the speed set before the fault took place.•The heating function will continue to operate at the set point before the fault took place.•If the problem is not solved, take the unit to your technical service center.8 Maintenance and Cleaning•Proper maintenance can keep instruments working in a good state and lengthen its lifetime.•Be careful not spray the cleanser into the instrument whencleaning.•Unplug the power line when cleaning.•Only use cleanser that we advised as below:Dyes Isopropyl alcoholConstruction materials Water containing tenside /isopropyl alcoholCosmetics Water containing tenside /isopropyl alcohol Foodstuffs Water containing tenside Fuels Water containing tensideTable 3•Before using other method for cleaning or decontamination, the user must ascertain with the manufacturer that this method does not harm or destroy the instrument.•Wear the proper protective gloves during cleaning of the instrument.•The instrument must be cleaned and put it into the initial packaging carton before sending to service for repair, avoiding the contamination of hazardous.•Use the instrument in a dry clean room and temperature stable environment.9 Associated standards and regulationsMachine guidelines: 73/023/EWG10 Technical dataItems ParametersV oltage [V AC] 200-240 / 100-120 Frequency [Hz]50/60Power [W]530(MS-H-S) / 130(MS-S) Stirring point positionquantity 1Max. stirring quantity (H2O) [L]20Max. magnetic bar [mm]80Motor type External rotorbrushless motorMax. power input of motor [W]18Max.power output of motor [W]10Speed range[rpm]0 ~ 1500Speed display accuracy [rpm]1Hotplate material Stainless steel/porcelain enamel Øof the hotplate [mm]Ø135Heating power[W]500(MS-H-S)Heating rate (1L water) [K/min]6(MS-H-S) Temperature range[℃]RT~340(MS-H-S)The safety temperature rangeof the hotplate [℃]350(MS-H-S) Dimensions (mm)280×160×85Weight [kg] 2.8Permitted ambienttemperature[℃] 5 ~ 40Permitted relative humidity80%Protection class acc. to DIN 60529IP42Table 4Accessories18900001MS 135.1 Carrier plate，Used withMS135.2--518900002MS 135.2 Quarter, 4 ml reaction vessel 18900003MS 135.3 Quarter, 20 ml reaction vessel 18900004MS 135.4 Quarter, 30 ml reaction vessel 18900005MS 135.5 Quarter, 40 ml reaction vessel 18900048MS 135.6 Quarter, 8 ml reaction vessel 18900049MS 135.7 Quarter, 16 ml reaction vessel 18900006Stirring bars（10mm x 6mm），1pcs/pk 18900007Stirring bars（15mm x 8mm），1pcs/pk 18900008Stirring bars（20mm x 8mm），1pcs/pk 18900009Stirring bars（25mm x 8mm），1pcs/pk 12500005Stirring bars（30mm x 6mm），1pcs/pk 12500005Stirring bars（30mm x 6mm），1pcs/pk 18900011Stirring bars（40mm x 8mm），1pcs/pk 12500004Stirring bars（50mm x 8mm），1pcs/pk 18900013Stirring bars（65mm x 8mm），1pcs/pk 18900014Stirring bars（80mm x 13mm），1pcs/pk 18900015Stirring bar mover，1pcTable 5SCILOGEX, LLC1275 Cromwell Ave.Suite C6Rocky Hill, CT 06067 USATel: +1(860) 436-9221Fax: +1(860) 436-9745*****************|。

MVSILICON AP8048A Audio Application ProcessorAP8048A DatasheetAudio Application Processor(ARM Cortex-M3 based)Rev0.4MVSILICON AP8048A Audio Application ProcessorDISCLAIMERAll information and data contained in this document are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this document invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on delivered development samples delivered. By this publication, Shanghai Mountain View Silicon Co., Ltd.(“MVSILICON”) does not assume responsibility for patent infringements or other rights of third parties that may result from its use.No part of this publication may be reproduced, photocopied, stored in a retrieval system, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of Shanghai Mountain View Silicon Co., Ltd.Shanghai Mountain View Silicon Co., Ltd. Assumes no responsibility for any errors contained herein.Revision HistoryDescriptionDate RevisionInitialV0.1chipname2013-10-21 V0.2 Change2013-11-4 V0.3 Change pin namefeatures2013-11-13 V0.4 ModifyMVSILICON AP8048A Audio Application Processor ContentsRevision History (ii)Contents (iii)Figures (iii)Tables (iii)1. Overview (1)1.1 Features (1)2.1 Pin Description (2)3. Package (3)3.1 Package Diagram (3)3.2 Package Dimension Parameter (4)4. Electrical Specification (5)4.1 Absolute Maximum Ratings (Note 1) (5)4.2 Recommended Operating Conditions (5)4.3 Electrical Characteristics (5)4.4 Audio Performance (5)FiguresFigure 1 Package Diagram (LQFP48-7x7mm / TOP View) (3)Figure 2 LQFP48-7x7mm Package Dimension Parameter (4)TablesTable 1 Pin Description (2)Table 2 Absolute Maximum Ratings (5)Table 3 Recommended Operating Conditions (5)Table 4 Electrical Characteristics (5)Table 5 Audio DAC Performance (5)Table 6 Linein Channel Characteristics (6)Table 7 FM Channel Characteristics (7)Table 8 MIC Channel Characteristics (7)MVSILICON AP8048A Audio Application Processor1. OverviewA highly integrated SOC for Audio application processing, AP8048A integrates ARM Cortex-M3 MCU, Bluetooth stack, MP3/WMA/FLAC decoder, MP2 encoder, OTG, SD/MMC card controller, SARADC, Audio DAC, Audio ADC, segment LED display driver, RTC and IR decoder in a single chip, AP8048A offers low power consumption, flexible and more powerful Bluetooth Audio player solution.1.1 Featuresz Embedded ARM Cortex-M3, running @ 96MHzz Support 2-wired debug portz Built-in 128K byte SRAMz Support booting from SPI-flash and the firmware can be updated through SD or USB diskz Provide code encryption mechanism in external flashz Embedded Bluetooth stack, supporting A2DP, AVRCP, Hand Free protocolz OTG 2.0 full-speed controllerz SD/MMC card controllerz Built-in MP2/MP3/WMA/FLAC(8/16/24bit)/WAV(IMA-ADPCM and raw PCM) decoderz Built-in MP2 encoderz Built-in super bass sound effectz Built-in echo generatorz Built-in parametric EQz Support FAT16/FAT32 file systemz Embedded 20-bit Audio DAC and 16-bit Audio ADCz Built-in Capless Earphone driverz Built-in MIC amplify block with AGCz Support 2 pairs of auxiliary audio inputz Embedded SARADCz Embedded RTCz Embedded NVM to save external EEPROMz Support segment LED displayz Embedded tone generatorz Support IR controlz GPIO for various purposesMVSILICON AP8048A Audio Application Processorz Embedded LDO2. Pin DescriptionAP8048A is a CMOS device. Floating level on input signals causes unstable deviceoperation and abnormal current consumption. Pull-up or Pull-down resistors should be used appropriately for input or bidirectional pins.Notation DescriptionI InputO OutputI/O BidirectionalPWR PowerGND Ground2.1 Pin Description Table 1 Pin DescriptionPin name Pin # Type DescriptionAudio CODEC interface pinsDAC_R 8 AO audio right channel outputDAC_L 9 AO audio left channel outputDACVMID 7 AI Internal voltage referenceMICIN 11 AI MIC inputGPIO/MCU IO pinsGPIO_A[10] 20 I/O GPIO PORT, bank AGPIO_A[25:13] 33:21 I/O GPIO PORT, bank AGPIO_B[8:5] 37:34 I/O GPIO PORT, bank BGPIO_B[20] 39 I/O GPIO PORT, bank BGPIO_B[29:22] 47:40 I/O GPIO PORT, bank BGPIO_B[31] 48 I/O GPIO PORT, bank BGPIO_C[2] 1 I/O GPIO PORT, bank CGPIO_C[14:11] 5:2 I/O GPIO PORT, bank CCLK pinsXIN 12 I 32.768KHz Crystal oscillator input for PLLXOUT 13 O 32.768KHz Crystal oscillator output for PLLPower/Ground pinsDVSS 19 GND ground for digitalLDOIN 15 PWR LDO power inLDO33O 14 PWR LDO 3.3V outLDO12O 17 PWR LDO 1.2V outIOVDD 38 PWR IO 3.3VDCOVDD 18 PWR power for PLLMVSILICON AP8048A Audio Application Processor DACVDD 10 PWRpower for DACDACAVSS 6 GND ground for DACMISC pinsPOWER_KEY 16 I Power Key3. Package3.1 Package DiagramMVsilicon GPIO_C2GPIO_C11GPIO_C12GPIO_C13GPIO_C14DACVDD DAC_L DACVMID DACAVSS GPIO_A22GPIO_A23GPIO_A24GPIO_A25GPIO_B5GPIO_B6GPIO_A17GPIO_A18GPIO_A20DAC_R MICIN XINFigure 1 Package Diagram (LQFP48-7x7mm / TOP View)MVSILICON AP8048A Audio Application Processor 3.2 Package Dimension ParameterFigure 2 LQFP48-7x7mm Package Dimension ParameterMVSILICON AP8048A Audio Application Processor4. Electrical Specification4.1 Absolute Maximum Ratings (Note 1) Table 2 Absolute Maximum RatingsParameter Symbol Rating Unit Storage Temperature TEMP_STG -65 to 150 C4.2 Recommended Operating Conditions Table 3 Recommended Operating Conditions4.3 Electrical CharacteristicsTable 4 Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit VIH Input High Voltage 1.6 3.6 VVIL Input Low Voltage -0.3 1.4 V VOH Output high voltage @IOH=2mA 3.0 VVOL Output low voltage @IOL=2mA 0.3 VIL Input leakage current -10 10 uA P_PLAY current Current consumption when playingPlaying mode 30 mARTC current Current consumption for RTC & NVM16 uA4.4 Audio PerformanceTable 5 Audio DAC PerformancePARAMETER TEST CONDITIONS MIN TYP MAX UNITNo Filter 93.6/93.6 dBDynamic Range With A-Weighted Filter 95/95 dBNo Filter 95.5/95.6 dBSignal-to-Noise Ratio With A-Weighted Filter 98/98 dBPeak THD+N (@0dBFS) -81/-81 dBTHD+N 0dBFS -75/-75 dBParameter Symbol Min Typ Max Unit Power Supply Voltage (LDO) VCC_LDO 3.35 5 VIO Input Voltage VIN 0 3.6 VOperating Free Air Temperature TEMP_OPR -40 85 CMVSILICON AP8048A Audio Application ProcessorFrequency Response 0.06 dBV Output Swing 0.993 VrmsInter-channel Gain Mismatch 0.003 dB Volume Control Step TBD dBVolume Control Range TBD dB Group Delay 80 usInter-channel Phase Deviation 0.01 degree Crosstalk -99/-98 dBThe measured output audio spectrum when the output is at -60 dBVTable 6 Linein Channel CharacteristicsMAXUNITMIN TYP PARAMETER TESTCONDITIONSNo Filter 88/88 dB Dynamic RangeWith A-Weighted Filter 90/90 dBNo Filter 88/88 dB Signal-to-Noise RatioWith A-Weighted Filter 90/90 dB THD+N Peak THD+N (@-2.4dBFS) -84/-84 dB Volume Control Step TBD dBVolume Control Range TBD dB Group Delay 26 fs Power Consumption 7.6 mWPower Supply Rejection Ratio 1kHz, 300mVrms 55 dBMVSILICON AP8048A Audio Application ProcessorThe measured audio spectrum when the analog input is at -2.6 dBVTable 7 FM Channel CharacteristicsMAXMIN TYPUNITCONDITIONSPARAMETER TESTNo Filter 86 dB Dynamic RangeWith A-Weighted Filter dBNo Filter 85 dB Signal-to-Noise RatioWith A-Weighted Filter dB THD+N Peak THD+N (@-12dBFS) -75 dBGroup Delay 26 fs Power Consumption 7.6 mWPower Supply Rejection Ratio 1kHz, 300mVrms 55 dBTable 8 MIC Channel CharacteristicsMAXUNITCONDITIONSMIN TYP PARAMETER TESTNo Filter 87.5/87.5 dB Dynamic RangeWith A-Weighted Filter 90/90 dBNo Filter 85.5/85.5 dB Signal-to-Noise RatioWith A-Weighted Filter 88.5/88.5 dB THD+N Peak THD+N (@-2dBFS) -82/-82 dBGroup Delay 26 fsCrosstalk TBD dB Power Consumption 7.6 mWMVSILICON AP8048A Audio Application Processor Power Supply Rejection Ratio 1kHz, 300mVrms 55 dBNote:1.“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Theyare not meant to imply that the device should be operated at these limits.MVSILICON AP8048A Audio Application Processor Contact InformationShanghai Mountain View Silicon Co LtdShanghai Headquarter:Room 602,Building Y2,No.112 Liangxiu Road,Pudong,Shanghai, P.R. ChinaZip code: 201203Tel: 86-21-68549851/68549853/68549857/61630160Fax: 86-21-61630162Shenzhen Sales & Technical Support Office:Suite 6A Olympic Plaza, Shangbao Road, Futian District,Shenzhen, Guangdong, P.R. ChinaZip code: 518034Tel: 86-755-83522955Fax: 86-755-83522957Email: support@Website: 。

TS34063AADc to Dc Converter ControllerSupply Voltage Range 3 V to 40V Output Driving Current 1.5A Oscillator Frequency up to 100KHzGeneral DescriptionThe TS34063A is a monolithic switching regulator and subsystem intended for use as DC to DC converter. It contains an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active peak current limit circuit, drive and a high current output switch.The TS34063A is specifically designed to be incorporated in step-up, step-down and voltage inverting converter applications.The TS34063A is offered in SOP-8 and DIP-8 package.FeaturesPower forward control circuit Operating voltage form 3V to 40V Low standby current Current limit adjustable Output switch current up to 1.5AVariable oscillator frequency up to 100KHz (max)Output voltage adjustablePin DescriptionsName DescriptionSC Switch CollectorSE Switch Emitter CT Timing Capacitor Gnd Ground Comp. Comparator Inverting Input Vcc Vcc Collector Ipk Ipk Sense Vdriver DriverApplicationsChargerxD-ROM, xDSL productDC to DC converter sOrdering InformationPart No.Operating Temp.(Ambient)PackageTS34063ACD DIP-8 TS34063ACS-20 ~ +85 oCSOP-8Block DiagramPin assignment:1. SC 2. SE 3. CT 4. Gnd 5. Comp. 6. Vcc 7. Ipk 8. VdriverAbsolute Maximum RatingSupply Voltage V CC 40 V Comparator Input Voltage Range V FB- 0.3 ~ 40 VSwitch Collector Output Voltage V C(SW) 40 V Switch Emitter Voltage V E(SW) 40 V Switch Collector to Emitter Voltage V CE(SW) 40 V Driver Collector Voltage Vc(driver) 40 VDriver Collector Current (note 1) Ic(driver) 100 mAOutput Switching Current I SW 1.5 APower Dissipation DIP-8SOP-8 Pd1.00.5WOperating Junction Temperature Range T J-0 ~ +125 o C Storage Temperature Range T STG-65 ~ +150 o C Note: Maximum package power dissipation limits must be observedElectrical Characteristics (VCC=5V, Ta =25 o C; unless otherwise specified.)Parameter SymbolTestConditionsMinTypMaxUnit Oscillator (OSC)Frequency F OSC C T = 1nF, Vpin5= 0V 24 33 42 KHz Charge Current I CHARGE V CC = 5V ~ 40V -- 30 -- uA Discharge Current I DISCHARGE V CC = 5V ~ 40V -- 200 -- uADischarge to Charge current ratio I DISCHARGE/ I CHARGEPin7 to Vcc -- 6.5 -- --Current Limit Sense Voltage V IPK(SENSE)I DISCHARGE = I CHARGE 250--350mV Output switch (note1)Saturation Voltage V CE(SAT)I SW= 1A, pin1,8 connected) -- 1.0 1.3 VSaturation Voltage V CE(SAT)I SW= 1A, Id=50mA -- 0.45 0.7 VDC current gain H FE I SW = 1A, Vce= 0.5V -- 75 -- --Collector off-state current I C(OFF)Vce= 40V -- 0.01 100 uA ComparatorThreshold Voltae V REF 1.225 1.25 1.275 VLine regulation RegLine V CC = 3V ~ 40V -- -- 6 mVTotal deviceSupply Current I CC V CC = 5V ~ 40V, C T = 1nF,pin7=Vcc, pin5>Vth,pin2=Gnd, remaining pinsopen-- 1.6 3 mANote: 1. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible2. If the output switch is driven into hard saturation (non-Darlington configuration) at low switch currents (<=300mA)and high driver currents (>=30mA), it may take up to 2uS for it to come out of saturation. This condition will shorten the off time at frequencies >= 30KHz, and is magnified at high temperature. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a non-Darlington configuration is used, the following output drive condition is recommended:Forced Bata of output switch: Ic output / (Ic driver – 7mA*) >= 10* The 100ohm resistor in the emitter of the driver divide requires about 7mA before the output switch conducts.Circuit DescriptionTypical Application CircuitFigure 7. Step Up ConverterResults Test ConditionsLINE REGULATION Vin= 8V~16V, Io= 175mA 30mV +/- 0.05%Load Regulation Vin= 12V, Io= 75mA to 175mA 10mV +/- 0.017%Output Ripple Vin=12V, Io= 175mA 400mVppEfficiency Vin=12V, Io= 175mA 87.7%Output Ripple with Optional Filter Vin=12V, Io= 175mA 40mVppTypical Application Circuit (continues)Figure 9. Step Down ConverterResults Test ConditionsLine Regulation Vin= 15V~25V, Io= 500mA 12mV +/- 0.12%Load Regulation Vin= 25V, Io= 50mA to 500mA 3mV +/- 0.03%Output Ripple Vin= 25V, Io= 500mA 120mVppShort Circuit Current Vin= 25V, RL= 0.1ohm 1.1AEfficiency Vin= 25V, Io= 500mA 83.7%Output Ripple with Optional Filter Vin= 25V, Io= 500mA 40mVppTypical Application Circuit (continues)Figure 11. Voltage Inverting ConverterResults Test ConditionsLine Regulation Vin= 4.5V~6.0V, Io= 100mA 3mV +/- 0.012%Load Regulation Vin= 5V, Io= 10mA to 100mA 22mV +/- 0.09%Output Ripple Vin= 5V, Io= 100mA 500mVppShort Circuit Current Vin= 5V, RL= 0.1ohm 900mAEfficiency Vin= 5V, Io= 100mA 62.2%Output Ripple with Optional Filter Vin= 5V, Io= 100mA 70mVpp。

CY8CMBR3002, CY8CMBR3102CY8CMBR3106S, CY8CMBR3108CY8CMBR3110, CY8CMBR3116具有SmartSense™自动调试16按键、2个滑条和接近传感器的CapSense®Express™控制器概述CY8CMBR3xxx CapSense®Express™控制器使先进但易于实现的电容触摸用户接口方案成为可能。

该系列寄存器配置型的控制器可支持多达16个电容式感应输入，并消除了设计周期的费时固件开发。

因此，当实现电容按键、滑条和接近感应解决方案时，这些控制需要最小的开发周期时间。

CY8CMBR3xxx系列提供了一个高级模拟检测通道和Capacitive Sigma Delta PLUS (CSD PLUS)感应算法。

该算法会发出高于100:1的信噪比，以确保正确触摸（即使在极端噪声环境中） 通过赛普拉斯SmartSense™自动调试算法来使能这些控制器，能够补偿生产变化造成的影响，并在所有环境条件下动态监控和维持最佳的传感器性能。

另外，通过SmartSense自动调试，在开发和生产过程中，由于可以缩短手动调试工作时间，所以可以加快产品的上市进程。

由于高级性能（如LED亮度控制、接近检测和系统诊断）的优点，可以节省开发时间。

这些控制器通过消除由薄雾、湿气、水滴、液体或流水导致的假触摸使能具有强大耐水性的设计。

CY8CMBR3xxx可包含在小尺寸工业标准封装中。

CY8CMBR3xxx系列系统包括多个开发工具（软件和硬件），能够快速启用用户界面设计。

例如，EZ-Click定制器工具是一个具有简单的图形用户界面的软件，用于通过I2C借口配置器件功能。

该工具还支持CapSense数据阅览，以操控系统性能和支持验证和调试。

另一个工具，Design Toolbox，通过提供设置指南和布局建议简化电路板布局，从而能够优化传感器大小、走线长度和寄生电容。

Small Form Factor Copyright © 2005 by Silicon Laboratories5.5.2005Analog Peripherals10-Bit ADC-Programmable throughput up to 200 ksps-Up to 16 external inputs; programmable as single-ended or differential -Reference from internal V REF , V DD , or external pin -Internal or external start of conversion sources -Built-in temperature sensor (±3 °C)10-bit DAC (Current Mode)Comparator-Programmable hysteresis and response time -Configurable to generate interrupts or reset -Low current (0.4 µA)On-Chip Debug-On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required)-Provides breakpoints, single stepping, watchpoints -Inspect/modify memory, registers, and stack-Superior performance to emulation systems using ICE-chips, target pods, and socketsSupply Voltage: 2.7 to 3.6 V-Typical operating current:6.4 mA at 25 MHz 9 µA at 32 kHz -Typical stop mode current: <0.1 µATemperature Range: –40 to +85 °CHigh-Speed 8051 µC Core-Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks-Up to 25 MIPS throughput with 25 MHz clock -Expanded interrupt handlerMemory-768 bytes data RAM-8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved)Digital Peripherals-17 port I/O; all are 5 V tolerant-Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports available concurrently-Programmable 16-bit counter/timer array with three capture/compare modules, WDT- 4 general-purpose 16-bit counter/timers-Real-time clock mode using PCA or timer and external clock source Clock Sources-Two internal oscillators:-24.5 MHz, 2% accuracy supports UART operation -80 kHz low frequency, low-power-External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)-Can switch between clock sources on-the-fly Package-20-pin QFN (standard lead and lead-free package)Ordering Part Numbers-Lead-free package: C8051F330-GM -Standard package: C8051F330Small Form Factor Copyright © 2005 by Silicon Laboratories5.5.2005Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holdersSelected Electrical Specifications(T A = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)Package InformationC8051F330DK Development Kit。

USB to UART Bridge Controller CH340DataSheetVersion: 2F1. IntroductionCH340 is a USB bus converter chip, which converts USB to serial UART interface or to printer interface.In serial UART mode, CH340 provides common MODEM signal, to expand UART interface of computer or upgrade common serial devices to USB bus directly. For more information about converting USB to printer interface, please refer to the manual CH340DS2.2. Features● Full speed USB device interface, USB 2.0 compatible.● Emulate standard UART interface, used to upgrade the original serial peripherals or expand additionalserial UART via USB.● Original serial applications are totally compatible without any modification.● Hardware full duplex serial UART interface, integrated transmit-receive buffer, supports communicationbaud rate varies from 50bps to 2Mbps.● Supports common MODEM interface signals RTS, DTR, DCD, RI, DSR and CTS.● Provides further RS232, RS485, RS422 interface, etc. through external voltage conversion chip.● CH340R supports IrDA criterion SIR infrared communication, supports baud rate varies from 2400bps to115200bps.● Software compatible with CH341, use driver of CH341 directly.● Supports 5V and 3.3V power supply even 3V.● CH340C/N/K/E and CH340B have integrated 12MHz clock, no external crystal required, CH340B alsointegrates EEPROM used to configure the serial number, etc.● RoHS compliant SOP-16, SOP-8, SSOP-20 and ESSOP-10, MSOP-10 lead-free package.3. PackagesPackage Width Of Plastic Pitch Of Pin Instruction Of PackageOrdering InformationSOP-16 3.9mm 150mil 1.27mm 50mil Small outline 16-pin patch CH340G SOP-16 3.9mm 150mil 1.27mm 50mil Small outline 16-pin patch CH340C SOP-8 3.9mm 150mil 1.27mm 50mil Small outline 8-pin patch CH340NESSOP-10 3.9mm 150mil 1.00mm 39mil Shrink Small outline 10-pin patch withbackplaneCH340KSOP-16 3.9mm 150mil 1.27mm 50mil Small outline 16-pin patch CH340B MSOP-10 3.0mm 118mil 0.50mm 19.7mil Miniature Small outline 10-pin patch CH340E SSOP-20 5.30mm 209mil 0.65mm 25mil Shrink Small outline 20-pin patch CH340T SSOP-20 5.30mm 209mil 0.65mm 25mil Shrink Small outline 20-pin patch CH340RModel differences:CH340C, CH340N, CH340K, CH340E and CH340B have integrated clock, no external crystal required.CH340B has also integrated EEPROM used to configure the serial number, etc. Some functions can be customized.The CH340K has three diodes built in to reduce current flow backwards between the I/O pins of the MCU.The backplane of the CH340K is 0# pin GND, which is an optional connection; the 3# pin GND is the necessary connection.CH340R provides reverse polarity TXD and MODEM interface signals. (Discontinued)4. Pin OutSSOP20 Pin No. SOP16Pin No.ESSOP10Pin No.SOP8Pin No.PinNamePin TypePin Description (description in bracket is only aboutCH340R)19 16 7 5 VCC POWER Power supply voltage input, requires an external0.1uF decoupling capacitor8 1 3, 0 3 GND POWER Ground5 4 10 8 V3 POWER Connect to VCC when VCC is 3V3, connect to 0.1uF decoupling capacitor when VCC is 5V9 7 NONE NONEXI INCH340T/R/G: Input of crystal oscillator, connect to12MHz crystal and capacitorNC. NONE CH340C: No Connection, must be suspended RST# INCH340B: Input of external reset, active low,integrated pull-up resistor10 8 NONE NONEXO OUTCH340T/R/G: Output of crystal oscillator, connect tocrystal and capacitorOUT# OUTCH340C: MODEM output IO, software controlled,active lowNC. NONE CH340B: No Connection, must be suspended6 5 1 1 UD+ USB signal Connect to USB D+ Signal directly7 6 2 2 UD- USB signal Connect to USB D- Signal directly20 NONE NONE NONE NOS# IN Forbid USB device suspending, active low, integratedpull-up resistor3 2 8 6 TXD OUT Transmit asynchronous data output(reverse output forCH340R)4 3 9 7 RXD IN Receive asynchronous data input, integrated configurable pull-up and pull-down resistor11 9 5 NONE CTS# IN MODEM input signal, clear to send, active low(high)12 10 NONE NONE DSR# IN MODEM input signal, data set ready, activelow(high)13 11 NONE NONE RI# IN MODEM input signal, ring indicator , activelow(high)14 12 NONE NONE DCD# IN MODEM input signal, data carrier detect, activelow(high)15 13 4 NONE DTR# OUT MODEM output signal, data terminal ready, activelow(high)16 14 6 4 RTS# OUT MODEM output signal, request to send, activelow(high)2 NONE NONE NONE ACT# OUT USB configuration completed state output, active low18 15 NONE NONE R232 IN CH340T/R/G/C: Assistant RS232 enable, active high, integrated pull-down resistor17 15 NONE NONE TNOW OUTCH340T/E/B: Ongoing data transmission statusindicator, active highIR# INCH340R:Serial mode input setting, integrated pull-upresistor, SIR infrared serial interface when low,common serial interface when high1 NONE NONE NONE CK0 OUT CH340T: clock outputNC. NONE CH340R:No Connection, must be suspended5. Function DescriptionCH340 has integrated USB pull-up resistor, UD+ and UD- pins should be connected to USB bus directly.CH340 has integrated power-on reset circuit. CH340B also provides low active external reset pin.CH340G/CH340T/CH340R need to work with 12MHz clock signal supplied to XI pin. Generally, clock signal is generated by the inverter in CH340 through crystal oscillation. The peripheral circuit needs to place a crystal of 12MHz between XI and XO, and connect to a capacitor to ground separately.CH340C, CH340N, CH340K, CH340E and CH340B have integrated clock generator, no external crystal and oscillating capacitor required.CH340B also provides EEPROM for configuring data area, product serial number and other information could be customized for each chip by specific software tools, configurable data area is shown in the table below.Byte Address AbbreviationDescription Of Chip Configuration Data Area Default00H SIG For CH340B: internal configuration information valid reg,must be 58H.For CH340H/S: external configuration information validreg, must be 53H.Invalid for other value00H01H MODE Serial mode, must be 23H 23H02H CFGSpecific configuration of chip,bit5 is used to configure product Serial Number:0= valid; 1= invalid.FEH03H WP Internal configuration information write protect flag，57Himply read only, otherwise can be rewrite00H05~04H VID Vendor ID, high byte is behind, any value. Set to 0000H or0FFFFH implies VID and PID using vendor default value1A86H07~06H PID Product ID, high byte is behind, any value 7523H 0AH PWR Max Power, The maximum supply current in 2mA units 31H17~10H SN Serial Number, the length of ASCII string is 8, disable theSerial number when the first byte is not ASCII character(21H~7FH)123456783FH~1AH PRODFor CH340B: Product String, Unicode string for productdescription. The first byte is by total bytes (less than 26H),the next byte is 03H, Unicode string after that, using vendordefault description when do not meet characteristics above.Using productdefaultdescription whenthe first byte is00HOthers (Reserved) 00H or FFHCH340 supports 5V and 3.3V power voltage. When using 5V power supply, the VCC pin connects 5V power and the V3 pin should connect with decoupling 0.1uF capacitor. When using 3.3V power supply, connects V3 with VCC, both powered with 3.3V power supply, and the other circuit voltage which connected with CH340 cannot exceed 3.3V.CH340 supports USB device suspending automatically to save power. USB device suspend is forbidden when NOS# is driven low.The DTR# pin of CH340 is used as a configuration input pin before the USB configuration completion. An external 4.7KΩ pull-down resistor can be connected with this pin to generate default low during USB enumeration, to apply larger supply current to the USB bus via the configuration descriptor for CH340.In serial UART mode, CH340 contains these pins: data transfer pins, MODEM interface signals and assistant pins.Data transfer pins contain: TXD and RXD. RXD keeps high when UART reception is idle. For CH340G/C/T/R, If pin R232 is driven high, assistant RS232 function will be enabled, an internal inverter will automatically insert to the RXD, and the pin becomes low by default. When UART transmission is idle, the TXD of CH340G/C/N/E/B/T keeps high, CH340K is weak high, while CH340R keeps low.MODEM interface signals contain: CTS#, DSR#, RI#, DCD# and RTS#, CH340C also provides OUT# pin. All these MODEM interface signals are controlled and function defined by computer applications.Assistant pins contain: IR#, R232, CK0, ACT# and TNOW. When IR# is low, infrared serial interface mode is enabled. R232 is used to control assistant RS232 function. If R232 is driven high, the RXD input will be reversed automatically. ACT# is USB device configuration complete status output (such as USB infrared adapter ready). TNOW indicates CH340 is transmitting data from UART when it is high and becomes low when transmits over. In RS485 and other half-duplex mode, TNOW could be used to indicate UART transmit-receive status. IR# and R232 are detected only once when chip powered on and reset.CH340 has integrated separate transmit-receive buffer and supports simplex, half-duplex and full duplex UART communication. Serial data contains one low-level start bit , 5, 6, 7 or 8 data bits and 1 or 2 high-level stop bits, supports odd/even/mark/space check. CH340 supports common baud rate: 50, 75, 100, 110, 134.5, 150, 300, 600, 900, 1200, 1800, 2400, 3600, 4800, 9600, 14400, 19200, 28800, 33600, 38400, 56000, 57600, 76800, 115200, 128000, 153600, 230400, 460800, 921600, 1500000, 2000000 etc.The baud rate error of CH340 UART reception allows not less than 2%, the baud rate error of CH340G/CH340T/CH340R UART transmission is less than 0.3%, less than 1% for CH340C/CH340N/CH340K/CH340E/CH340B.In the Windows OS, CH340 driver can emulate standard serial port. So the mostly original serial applications are totally compatible, without any modification.CH340 can be used to upgrade the serial interface peripherals, or expand extra serial port for computers via USB bus, through external level conversion chip provide further RS232, RS485, RS422 interface, etc.Through extra infrared transceiver, CH340R can expand SIR infrared adapter for computer via USB bus, realize infrared communication between computers and peripheral equipment that comply with IrDA specifications.6. Parameters6.1. Absolute Maximum Ratings(critical state or exceeding maximum can cause chip to not work or even be damaged)Name Parameter Description Min. Max. UnitTA Operating AmbientTemperatureCH340G/CH340T/CH340R -40 85 ℃CH340C/CH340N/CH340K/CH340E/CH340B-20 70 ℃TS Storage Temperature -55 125 ℃VCC Supply Voltage(VCC connects to power, GND to ground) -0.5 6.0 V VIO The voltage of input or output pin -0.5 VCC+0.5 V6.2. Electrical Parameters (test conditions: TA=25,VCC=5V, exclude pin℃s connected to USB bus) (all the current parameters should multiply the coefficient of 40% when the supply voltage is 3.3V)Name Parameter Description Min. Typical Max. UnitVCC Supply VoltageV3 doesn’t connect to VCC 4.0 5 5.3V V3 connects toVCCCH340G/T/R 2.8 3.3 3.6CH340C/N/K/E/B 3.1 3.3 3.6ICCOperating SupplyCurrent(Normal Operation)CH340G/C/N/K/E/T/R7 20mACH340B 6 15ISLP Operating Supply Current(USBSuspend)VCC=5V 0.1 0.2mAVCC=3.3V 0.09 0.15VIL Input Low Voltage -0.5 0.7 V VIH Input High Voltage 2.0 VCC+0.5 V VOL Output Low Voltage(4mA draw current) 0.5 VVOH Output High Voltage(3mA output current)(Output 100uA current during chip reset)VCC-0.5 VIUP Draw current of input with integrated pull-up resistor 3 150 300 uAIDN Draw current of input with integrated pull-downresistor-50 -150 -300 uAVR Voltage threshold when power-up reset 2.4 2.6 2.8 V 6.3. Timing Parameters (test conditions: TA=25,VCC=5V)℃Name Parameter Description Min. Typical Max. Unit FCLK Frequency of input clock in XI 11.98 12.00 12.02 MHz TPR Reset time of power-up 20 35 50 mS 7. Applications7.1. USB to RS232 converter configurationThe image above use CH340T/CH340B (or CH340C ) to realize USB to RS232 converter. CH340 provides common UART and MODEM signals, converts TTL to RS232 through level conversion chip U8. Port P11 is DB9 connector, the pins and their functions are the same as common PC DB9 connector, the chips similar with U8 have MAX213/ADM213/SP213/MAX211 etc.U8 and C46/C47/C48/C49/C40 could be removed when realize USB to TTL converter only. The signal lines in the image only RXD、TXD and public ground need connected, the other signal lines should suspend when not use.P2 is USB port, USB bus contains a pair of 5V power lines and a pair of data signal lines . Usually, the color of +5V power line is red, the black one is ground. D+ signal line is green and the D- signal line is white. The max supply current of USB bus is up to 500mA. Generally, CH340 and low power consumption USB products can use the 5V power supplied by USB bus directly. If the USB products supply standing power by other manner, CH340 should use this power too. If the USB bus power and standing power are necessary at the same time, connect a 1Ωresistor between USB bus 5V power line and USB products 5V standing power line, and connect the ground lines of these two power directly.The capacitor C8 on V3 is 0.1uF, used to CH340 internal power node decoupling. The capacitor C9 is 0.1uF, used to external power decoupling.For CH340G/T/R, Crystal X2, capacitor C6 and C7 are used for clock oscillation circuit. The X2 is 12MHz quartz crystal, C6 and C7 are monolithic or high frequency ceramic capacitors with 22pF. If X2 is ceramic with low cost, C6 and C7 must use the recommended value of crystal manufacturer and generally is 47pF. For the crystalwhich is difficult to oscillate, halved value is suggested for C6.For CH340C/N/K/E/B, crystal X2 and capacitor C6, C7 are not required.When designing the PCB, pay attention to: decoupling capacitor C8 and C9 must keep near to connection pin of CH340; make sure D+ and D- signal lines are parallel and provide ground or pour copper on both sides to reduce outside interference; the signal lines relevant to XI and XO should be kept as short as possible. In order to reduce the high frequency interference, around the ground or pour copper around the relevant components.7.2. USB to RS232 converter configuration (3-wire)The image below is USB to 3-wire RS232 converter design which is the most basic and most commonly used, U5 uses MAX232/ICL232/SP232 etc.7.3. USB to RS232 converter configuration (simplified version using RS232)The image above is USB to RS232 converter design too, the function of this circuit is the same with 7.2 section except the range of output RS232 is narrower. When R232 pin is driven high, the assistant RS232 function will be enabled, just need to add some diodes, transistors, resistors and capacitors, the special level conversion chip U5 in section 7.2 could be replaced and the hardware cost is lower.7.4. USB to Infrared AdapterThe image above is a USB to infrared adapter design which is composed with USB convert IrDA infrared chip CH340R and infrared transceiver U14 (ZHX1810/HSDL3000 etc). The resistor R13 is used to weaken influence of large current in infrared transmitting. The current limiting resistor R14 should be adjusted according to the manufacturer’s recommended value of the infrared transceiver U14.7.5. USB to RS485 Converter ConfigurationThe TNOW pin can be used to control DE (high active send enable) and RE# (low active receive enable) pin of RS485 transceiver.3247.6. Connect CH340 to MCU and supply power togetherThe image below is a sample design to achieve USB connection on an MCU by connecting it to a CH340 via TTL serial port. Here we use self-power mode, VCC supports 5V or 3.3V(V3 shorted to VCC if VCC is 3.3V), and don’t use USB bus power VBUS at all(Can be tested by connecting series resistor to I/O of MCU if needed).CH340 shares the same power source with MCU, hence there would be no current inrush through I/O betweenCH340 and MCU.Unused CH340 pins can be suspended. For CH340C, CH340N, CH340E, CH340B, X6 , C17 and C18 are unused.7.7. Connect CH340 to MCU and supply power separatelyThe image below is a sample design to achieve USB connection on an MCU by connecting it to a CH340 via TTL serial port. CH340 is powered by USB bus VBUS. MCU is powered by another power source VDD, VDD supports 5V, 3.3V and even 2.5V, 1.8V. The diodes D6 and D7 are used to help relieve current inrush problems between CH340 and MCU through RXD or diode within RX. The RX pin of the MCU should enable internalpull-up resistor. If not, we suggest adding an 8kΩ ~ 30kΩ pull-up resistor to RX pin.Diode D6 is meant for circumstances when CH340 is not powered but MCU is powered, and TX high level causes current inrush through RXD internal diode; Diode D7 is meant for circumstances when MCU is not powered but CH340 is powered, and TXD high level causes current inrush through RX internal diode. If certain circumstance can be ensured to be avoided, the corresponding diode can be removed. For example, if the MCU has a permanent power source, then D7 can be short-circuited.Prioritized choice for diode is low power Schottky diode. Common diode such as IN4148 is also usable. Besides, replacing the diode with an 1kΩ(better less than 2kΩ) resistor is acceptable too.Usually, we don’t recommend power CH340 and MCU separately if not necessary.7.8. Connect CH340K to MCU and supply power separatelyThe figure above shows the reference circuit for USB communication between the MCU and the CH340K via UART. CH340K is powered by the USB bus VBUS (VCC), the MCU uses another power supply VDD, whichCH340 DataSheet(1st) 11supports 5V, 3.3V or even 2.5V, 1.8V. The backplane of the CH340K package is an optional GND pin that can be easily connected to GND or left floating depending on the PCB trace.The TXD and RTS# pins of the CH340K and the RXD pin have built-in diodes to prevent current flow backwards (as shown), and a weak pull-up resistor of about 75KΩis built in to maintain the default or idle state high level (in the figure). Not marked), this can achieve low-level drive and weak high-level drive, as well as reduce current flow backwards when the CH340K and MCU are independently powered. The CH340K can completely prevent the MCU power supply from powering down the current of the CH340K, and can also greatly reduce the current flow backwards of the MCU power supply to the power-off CH340K(up to 150μA). When used for communication baud rate above 120Kbps, it is recommended to enable built-in or external 2KΩ~ 22KΩpull-up resistor for the RX pin of the MCU.The DTR# pin of the CH340K is a normal push-pull output, and the CTS# pin is a normal input with a built-in pull-up resistor. These two pins have no built-in diodes and do not have the function of preventing current flow backwards. They are generally not used to connect to the MCU.DTR# can be used to control the power switch that VCC supplies to VDD. Four power control schemes are available as shown below. The T4 scheme and the Q1 scheme (Q1 should choose a lower Vth N-OSFET) is a simplified scheme. The VDD output voltage is about VCC-0.8V and the current does not exceed 200mA. The T6 scheme and the Q3 scheme are complete solutions. In the figure, D10 and D11 are used to prevent VDD from flow backwards to VCC, which is optional.。

捷多邦，您值得信赖的PCB打样专家！ML8511-00FCREFERENCE BOARD Manual for UV Sensor (QFN)Issue date: August 27, 2013NOTESNo copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd.The content specified herein is subject to change for improvement without notice.Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage.The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).The Products specified in this document are not designed to be radiation tolerant.While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons.Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual.The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.Copyright 2013 LAPIS Semiconductor Co., Ltd.1. General DescriptionThe ML8511-00FC is a reference board for the Lapis Semiconductor UV Sensor ML8511. Below shows the FRONT and BACK of the PCB with a mounted ML8511 in a QFN package.2. Features∙UV Photodiode sensitive to UV-A and UV-B∙Embedded operational amplifier∙Analog voltage output∙Low supply current (300uA typ.) and low standby current (0.1uA typ.)∙Small SMT package (4.0mm x 3.7mm x 0.73mm, 12-pin ceramic QFN)∙Active high enable pin∙VDD input cap and reference voltage decoupling cap included on reference board3. ApplicationsSmart Phone, Watch, Weather station, Bicycle Navigation, Gaming, Health, Fitness, Accessories4. Recommended Operating ConditionsUnitMaximum Parameter Symbol MinimumTypicalOperating V oltage VDD 2.7 3.3 3.6 VOperating Temperature Ta -20 25 70 °CStorage Temperature Tstg -30 - 85 °C5. UV Sensor Optical FilterAn optical UV transmission filter is recommended with the usage of ML8511. The material recommended is ACRYLITE #000 (1.0mm thickness) with sandblast #220, if opaque filter is desired. The distance from ML8511 to filter is D1. D1 should be ~1.0mm. The aperture size of the filter is D2. D2 should be ~3.0mm.6. Output Voltage – UV CharacteristicsThe below chart shows the linear relationship between the sensor’s output voltage and UV intensity (mW/cm2) when Vdd = 3.0V. The sensor output is stable across the operating temperature range.7. Spectral Response CharacteristicsThe ML8511 has the spectral response of measuring UV A and UVB wavelengths. UV-A: 315-400nmUV-B: 280-315nm8. Reference Board SchematicThe schematic below shows the reference board inputs/outputs and pin connections.9. Reference Board Dimensions10. Table of Pin DescriptionsCN1 through-hole # Through-hole Name Function1 UVOUT Output2 UVEN Active high EN_pin (High: Active /Low: Standby)3 - -4 - -5 GND Ground6 - -7 - -8 - -9 - -V oltage10 VDD Input*Please refer to the ML8511 datasheet for additional details on electrical specifications andrecommendations.Revision HistoryPageDocument No. Issue Date PreviousEditionNewEditionDescriptionFEBL8511_REFBOARD_Manual-012013.08.27 – – First Edition。

• Insert the 3-V coin cell (included with the kit) into the coin cell holder on the rear side of the baseboard1• Move your nger over the CapSense ® slider on the baseboard to control the brightness of the blue LED on the dongle23434BLE Pioneer Kit code examples, documents, and hardware design les from /CY8CKIT-042-B L E-Athe baseboard with the PSoC 4 BLE module to your computer with a USB cable• Refer to Chapter 4 of the Kit Guide for additional information on code examples5Note: If you are evaluating this demo near another BLE Pioneer Kit that is advertising (when using the default out-of-box rmware), the dongle may connect to the other baseboard instead. In this case, press the reset button (SW1) on both the dongle and baseboard of your kit, then repeat step 3 to retry connection between the twoFeature List and Pinout Description for CySmart USB DonglePSoC 4 BLEreset buttonCY8C4248LQI-BL583PSoC 4 BLE devicePSoC 5LPprogramming test pointsCY8C5868LTI-LP039PSoC 5LP programmerand debuggerUser buttonPower LEDUSB plugStatus LEDP1_4 (PSoC 4 BLE)P1_5 (PSoC 4 BLE)Wiggle antenna Antenna matching network (AMN)24-MHz crystal User LED PSoC 4 BLE external programming header32.768-kHzcrystal (bottom side)6GND VDDA P3_6 P3_7P3_4 P3_5P3_2 P3_3P3_0 P3_1P4_0 P5_1P4_1 P5_0P2_6 P2_7P2_4 P2_5P2_2 P2_3P2_0 P2_1VDDR GNDP0_1 P0_0P0_3 P0_2P0_5 P0_4P1_0 VREF P1_2 P1_1P0_6 P1_4P0_7 P1_3XRES P1_5GND P1_7VDDD P1_6V D D G N D P 1_4P 1_5Wiggle antenna32.768-kHz crystal (bottom side)CmodCtank Antenna matching network (AMN)CY8C4248LQI-BL583PSoC 4 BLE devicePSoC 4 BLE module header (J2)PSoC 4 BLE module header (J1)4-pin UART headerSAR bypass capacitor (bottom side)24-MHz crystalFeature List and Pinout Description for PSoC 4 BLE 256KB ModulePSoC 4 BLE - A single chip solution with a 48-MHz ARM ® Cortex ®-M0, BLE 4.2 radio, CapSense, programmable analog (12-bit ADC, 2 Current DACs, 2 Low Power Comparators, 4 Low Power Opamps) and programmable digital peripherals(4 Timer/Counter/PWMs, 4 Universal Digital Blocks, 2 Serial Communication Blocks)© 2016 - 2018 Cypress Semiconductor Corporation. All rights reserved.All trademarks or registered trademarks referenced herein are the properties of their respective owners. Doc.#: 002-11473 Rev.*CArduino Pin De nition BLE Pioneer BaseboardFor the latest information about this kit and to download kit software and hardware les, visit /CY8CKIT-042-BLE-AP 3_5/S C LP 3_4/S D A V R E F /A R E F G N D /G N D P 0_3/D 13P 0_1/D 12P 0_0/D 11P 0_2/D 10P 0_4/D 9P 0_5/D 8P 1_0/D 7P 1_1/D 6P 1_2/D 5P 1_3/D 4P 1_7/D 3P 1_6/D 2P 1_5/D 1P 1_4/D 0G N D P 5L P 12_5P 5L P 3_0P 5L P 12_7P 5L P 3_7P 5L P 3_5P 5L P 0_1P5LP1_2P5LP12_0P5LP2_5VDD P5LP0_0P5LP3_4P5LP3_6P5LP12_6P5LP12_1N C I O R E F /B L E _V D D R E S E T /R E S E T 3.3 V /V 3.35 V /V 5.0G N D /G N D G N D /G N D V i n /V I NA 0/P 3_0A 1/P 3_1A 2/P 3_2A 3/P 3_3A 4/P 3_4A 5/P 3_5P 2_5P 2_4P 2_3P 2_2P 2_1P 2_01 1 RGB LED2 BLE device reset button3 CapSense proximity header4 User button5 CapSense slider6 Arduino compatible I/O Headers (J2/J3/J4)7 Arduino-compatible power header (J1)8 Digilent ® Pmod TM - compatible I/O header (J5)9 Cypress F-RAM 1 Mb (FM24V10-G)10 PSoC 5LP I/O header (J8)11 PSoC 5LP programmer and debugger (CY8C5868L TI-L P039)12 Coin cell holder (bottom side)13 USB connector (J13)14 Power LED and Status LED 15 System power supply jumper (J16) - LDO 1.9 V~5 V 16 BLE power supply jumper / current measurement (J15)17 BLE module headers (J10/J11)2345678910111213141561617Feature List and Pinout Description for BLE Pioneer BaseboardP2_0B LUETOOTH ®LOW ENERGY PIONEER KIT。

TM2AMI8HTi s c l a i me r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t ef o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i ng s u i t a b i l i t y o r r e l i a b i l i t y o f th e s e p r o d u c t s f o r s p e ci f i c u s e r a p p l i c a t i o n sProduct datasheetCharacteristicsTM2AMI8HTanalog input module M238 - 8 inputs voltage/current - non differentialMainRange of productModicon M238 logic controller Product or component type Analog input module Analogue input number 8Analogue input type Current 4...20 mA non differential Voltage 0...10 V non differential Cross talk<= 1 LSBComplementaryRange compatibility TwidoAdvantys OTB Analogue input resolution 10 bits LSB value19.5 µA current 9.7 mV voltage Permissible continuous overload 13 V voltage 40 mA current Input impedance >= 10 kOhm voltage 470 Ohm current Sampling duration <= 160 msAcquisition period 160 ms per channel + 1 controller cycle time Measurement error +/- 0.2 % of full scale 25 °C Temperature coefficient +/-0.01 %FS/°C Repeat accuracy +/- 0.4 %FS Non-linearity +/- 0.002 %FS Total error +/-1 %FS Type of cableShielded cable Insulation between channel and internal logic Photocoupler SupplyExternal supply [Us] rated supply voltage24 V DCSupply voltage limits 20.4...28.8 VElectrical connection 1 removable screw terminal block power supply 1 removable screw terminal block sensors Current consumption 45 mA 24 V DC external 60 mA 5 V DC internal Product weight0.085 kgEnvironmentDielectric strength 2500 V between the I/O and internal logic Width 23.5 mm Depth 70 mm Height90 mmOffer SustainabilitySustainable offer status Green Premium productRoHS (date code: YYWW)Compliant - since 1039 - Schneider Electric declaration of conformity Schneider Electric declaration of conformity REAChReference not containing SVHC above the threshold Reference not containing SVHC above the threshold Product environmental profileAvailableProduct environmental Product end of life instructionsAvailableEnd of life manualContractual warrantyWarranty period18 monthsProduct datasheetDimensions DrawingsTM2AMI8HTAnalog Input Module (8-channel, Voltage/Current)DimensionsNOTE: * 8.5 mm (0.33 in) when the clip-on lock is pulled out.Product datasheetMounting and ClearanceTM2AMI8HTDIN Rail MountingProduct datasheetTM2AMI8HT Mounting and ClearanceModule Mounting on a Panel SurfaceMounting Hole LayoutProduct datasheetTM2AMI8HT Connections and SchemaWiring RequirementsCable Types and Wire Sizes for Removable Screw Terminal BlockProduct datasheetTM2AMI8HT Connections and SchemaAnalog Input Module (8-channel, Voltage/Current)Wiring DiagramTM2AMI8HT。

CY7C67300 EZ-Host™ Programmable EmbeddedUSB Host/Peripheral ControllerTABLE OF CONTENTS1.0 INTRODUCTION (10)1.1 EZ-Host Features (10)2.0 TYPICAL APPLICATIONS (11)3.0 FUNCTIONAL OVERVIEW (11)3.1 Processor Core (11)3.1.1 Processor (11)3.1.2 Clocking (11)3.1.3 Memory (11)3.1.4 Interrupts (11)3.1.5 General Timers and Watchdog Timer (11)3.1.6 Power Management (11)4.0 INTERFACE DESCRIPTIONS (11)4.1 USB Interface (13)4.1.1 USB Features (13)4.1.2 USB Pins. (14)4.2 OTG Interface (14)4.2.1 OTG Features (14)4.2.2 OTG Pins. (14)4.3 External Memory Interface (14)4.3.1 External Memory Interface Features (14)4.3.2 External Memory Access Strobes (14)4.3.3 Page Registers (15)4.3.4 Merge Mode (15)4.3.5 Program Memory Hole Description (15)4.3.6 DMA to External Memory Prohibited (15)4.3.7 External Memory Interface Pins (16)4.3.8 External Memory Interface Block Diagrams (17)4.4 General Purpose I/O Interface (GPIO) (18)4.4.1 GPIO Description (18)4.4.2 Unused Pin Descriptions (18)4.5 UART Interface (18)4.5.1 UART Features (18)4.5.2 UART Pins. (18)4.6 I2C EEPROM Interface (18)4.6.1 I2C EEPROM Features (18)4.6.2 I2C EEPROM Pins. (18)4.7 Serial Peripheral Interface (18)4.7.1 SPI Features (19)4.7.2 SPI Pins (19)4.8 High-speed Serial Interface (19)4.8.1 HSS Features (19)4.8.2 HSS Pins (20)4.9 Programmable Pulse/PWM Interface (20)4.9.1 Programmable Pulse/PWM Features (20)4.9.2 Programmable Pulse/PWM Pins. (20)4.10 Host Port Interface (20)4.10.1 HPI Features (20)4.10.2 HPI Pins. (21)TABLE OF CONTENTS (continued)4.11 IDE Interface (21)4.11.1 IDE Features (22)4.11.2 IDE Pins (22)4.12 Charge Pump Interface (22)4.12.1 Charge Pump Features (23)4.12.2 Charge Pump Pins. (23)4.13 Booster Interface (23)4.13.1 Booster Pins. (24)4.14 Crystal Interface (25)4.14.1 Crystal Pins (25)4.15 Boot Configuration Interface (25)4.16 Operational Modes (26)4.16.1 Coprocessor Mode (26)4.16.2 Standalone Mode (26)5.0 POWER-SAVINGS AND RESET DESCRIPTION (27)5.1 Power-Savings Mode Description (27)5.2 Sleep (27)5.3 External (Remote) wakeup Source (27)5.4 Power-On-Reset Description (27)5.5 Reset Pin (27)5.6 USB Reset (27)6.0 MEMORY MAP (28)6.1 Mapping (28)6.1.1 Internal Memory (28)6.1.2 External Memory (28)7.0 REGISTERS (30)7.1 Processor Control Registers (30)7.1.1 CPU Flags Register [0xC000] [R] (30)7.1.2 Bank Register [0xC002] [R/W] (31)7.1.3 Hardware Revision Register [0xC004] [R] (31)7.1.4 CPU Speed Register [0xC008] [R/W] (32)7.1.5 Power Control Register [0xC00A] [R/W] (33)7.1.6 Interrupt Enable Register [0xC00E] [R/W] (35)7.1.7 Breakpoint Register [0xC014] [R/W] (36)7.1.8 USB Diagnostic Register [0xC03C] [R/W] (37)7.1.9 Memory Diagnostic Register [0xC03E] [W] (38)7.2 External Memory Registers (39)7.2.1 Extended Page n Map Register [R/W] (39)7.2.2 Upper Address Enable Register [0xC038] [R/W] (39)7.2.3 External Memory Control Register [0xC03A] [R/W] (40)7.3 Timer Registers (41)7.3.1 Watchdog Timer Register [0xC00C] [R/W] (41)7.3.2 Timer n Register [R/W] (42)7.4 General USB Registers (42)7.4.1 USB n Control Register [R/W] (42)7.5 USB Host Only Registers (45)7.5.1 Host n Control Register [R/W] (45)7.5.2 Host n Address Register [R/W] (46)TABLE OF CONTENTS (continued)7.5.3 Host n Count Register [R/W] (46)7.5.4 Host n Endpoint Status Register [R] (47)7.5.5 Host n PID Register [W] (48)7.5.6 Host n Count Result Register [R] (49)7.5.7 Host n Device Address Register [W] (50)7.5.8 Host n Interrupt Enable Register [R/W] (50)7.5.9 Host n Status Register [R/W] (52)7.5.10 Host n SOF/EOP Count Register [R/W] (53)7.5.11 Host n SOF/EOP Counter Register [R] (53)7.5.12 Host n Frame Register [R] (54)7.6 USB Device Only Registers (54)7.6.1 Device n Endpoint n Control Register [R/W] (55)7.6.2 Device n Endpoint n Address Register [R/W] (56)7.6.3 Device n Endpoint n Count Register [R/W] (57)7.6.4 Device n Endpoint n Status Register [R/W] (57)7.6.5 Device n Endpoint n Count Result Register [R/W] (59)7.6.6 Device n Port Select Register [R/W] (60)7.6.7 Device n Interrupt Enable Register [R/W] (60)7.6.8 Device n Address Register [W] (63)7.6.9 Device n Status Register [R/W] (63)7.6.10 Device n Frame Number Register [R] (65)7.6.11 Device n SOF/EOP Count Register [W] (66)7.7 OTG Control Registers (66)7.7.1 OTG Control Register [0xC098] [R/W] (66)7.8 GPIO Registers (68)7.8.1 GPIO Control Register [0xC006] [R/W] (68)7.8.2 GPIO n Output Data Register [R/W] (70)7.8.3 GPIO n Input Data Register [R] (70)7.8.4 GPIO n Direction Register [R/W] (71)7.9 IDE Registers (71)7.9.1 IDE Mode Register [0xC048] [R/W] (71)7.9.2 IDE Start Address Register [0xC04A] [R/W] (72)7.9.3 IDE Stop Address Register [0xC04C] [R/W] (72)7.9.4 IDE Control Register [0xC04E] [R/W] (73)7.9.5 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] (74)7.10 HSS Registers (74)7.10.1 HSS Control Register [0xC070] [R/W] (75)7.10.2 HSS Baud Rate Register [0xC072] [R/W] (77)7.10.3 HSS Transmit Gap Register [0xC074] [R/W] (77)7.10.4 HSS Data Register [0xC076] [R/W] (78)7.10.5 HSS Receive Address Register [0xC078] [R/W] (78)7.10.6 HSS Receive Counter Register [0xC07A] [R/W] (79)7.10.7 HSS Transmit Address Register [0xC07C] [R/W] (79)7.10.8 HSS Transmit Counter Register [0xC07E] [R/W] (79)7.11 HPI Registers (80)7.11.1 HPI Breakpoint Register [0x0140] [R] (80)7.11.2 Interrupt Routing Register [0x0142] [R] (81)7.11.3 SIEXmsg Register [W] (82)7.11.4 HPI Mailbox Register [0xC0C6] [R/W] (83)7.11.5 HPI Status Port [] [HPI: R] (83)TABLE OF CONTENTS (continued)7.12 SPI Registers (85)7.12.1 SPI Configuration Register [0xC0C8] [R/W] (86)7.12.2 SPI Control Register [0xC0CA] [R/W] (87)7.12.3 SPI Interrupt Enable Register [0xC0CC] [R/W] (89)7.12.4 SPI Status Register [0xC0CE] [R] (89)7.12.5 SPI Interrupt Clear Register [0xC0D0] [W] (90)7.12.6 SPI CRC Control Register [0xC0D2] [R/W] (91)7.12.7 SPI CRC Value Register [0xC0D4] [R/W] (92)7.12.8 SPI Data Register [0xC0D6] [R/W] (92)7.12.9 SPI Transmit Address Register [0xC0D8] [R/W] (93)7.12.10 SPI Transmit Count Register [0xC0DA] [R/W] (93)7.12.11 SPI Receive Address Register [0xC0DC [R/W] (93)7.12.12 SPI Receive Count Register [0xC0DE] [R/W] (94)7.13 UART Registers (94)7.13.1 UART Control Register [0xC0E0] [R/W] (94)7.13.2 UART Status Register [0xC0E2] [R] (95)7.13.3 UART Data Register [0xC0E4] [R/W] (96)7.14 PWM Registers (96)7.14.1 PWM Control Register [0xC0E6] [R/W] (97)7.14.2 PWM Maximum Count Register [0xC0E8] [R/W] (98)7.14.3 PWM n Start Register [R/W] (99)7.14.4 PWM n Stop Register [R/W] (99)7.14.5 PWM Cycle Count Register [0xC0FA] [R/W] (100)8.0 PIN DIAGRAM (101)9.0 PIN DESCRIPTIONS (101)10.0 ABSOLUTE MAXIMUM RATINGS (105)11.0 OPERATING CONDITIONS (105)12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) (105)13.0 DC CHARACTERISTICS (105)13.1 USB Transceiver (106)14.0 AC TIMING CHARACTERISTICS (107)14.1 Reset Timing (107)14.2 Clock Timing (107)14.3 SRAM Read Cycle (108)14.4 SRAM Write Cycle (109)14.5 I2C EEPROM Timing (110)14.6 HPI (Host Port Interface) Write Cycle Timing (111)14.7 HPI (Host Port Interface) Read Cycle Timing (112)14.8 IDE Timing (113)14.9 HSS BYTE Mode Transmit (113)14.10 HSS Block Mode Transmit (113)14.11 HSS BYTE and BLOCK Mode Receive (113)14.12 Hardware CTS/RTS Handshake (114)15.0 REGISTERS SUMMARY (114)16.0 ORDERING INFORMATION (118)17.0 PACKAGE DIAGRAMS (118)LIST OF FIGURESFigure 1-1. Block Diagram (10)Figure 4-1. Page n Registers External Address Pins Logic (15)Figure 4-2. Interfacing to 64k × 8 Memory Array (17)Figure 4-3. Interfacing up to 256k × 16 for External Code/Data (17)Figure 4-4. Interfacing up to 512k × 8 for External Code/Data (17)Figure 4-5. Charge Pump (23)Figure 4-6. Power Supply Connection With Booster (24)Figure 4-7. Power Supply Connection Without Booster (24)Figure 4-8. Crystal Interface (25)Figure 4-9. Minimum Standalone Hardware Configuration – Peripheral Only (26)Figure 6-1. Memory Map (29)Figure 7-1. Processor Control Registers (30)Figure 7-2. CPU Flags Register (30)Figure 7-3. Bank Register (31)Figure 7-4. Revision Register (31)Figure 7-5. CPU Speed Register (32)Figure 7-6. Power Control Register (33)Figure 7-7. Interrupt Enable Register (35)Figure 7-8. Breakpoint Register (36)Figure 7-9. USB Diagnostic Register (37)Figure 7-10. Memory Diagnostic Register (38)Figure 7-11. External Memory Control Registers (39)Figure 7-12. Extended Page n Map Register (39)Figure 7-13. External Memory Control Register (39)Figure 7-14. External Memory Control Register (40)Figure 7-15. Timer Registers (41)Figure 7-16. Watchdog Timer Register (41)Figure 7-17. Timer n Register (42)Figure 7-18. General USB Registers (42)Figure 7-19. USB n Control Register (43)Figure 7-20. USB Host Only Register (45)Figure 7-21. Host n Control Register (45)Figure 7-22. Host n Address Register (46)Figure 7-23. Host n Count Register (46)Figure 7-24. Host n Endpoint Status Register (47)Figure 7-25. Host n PID Register (49)Figure 7-26. Host n Count Result Register (49)Figure 7-27. Host n Device Address Register (50)Figure 7-28. Host n Interrupt Enable Register (50)Figure 7-29. Host n Status Register (52)Figure 7-30. Host n SOF/EOP Count Register (53)Figure 7-31. Host n SOF/EOP Counter Register (54)Figure 7-32. Host n Frame Register (54)Figure 7-33. USB Device Only Registers (55)Figure 7-34. Device n Endpoint n Control Register (55)Figure 7-35. Device n Endpoint n Address Register (57)Figure 7-36. Device n Endpoint n Count Register (57)Figure 7-37. Device n Endpoint n Status Register (58)Figure 7-38. Device n Endpoint n Count Result Register (60)LIST OF FIGURES (continued)Figure 7-39. Device n Port Select Register (60)Figure 7-40. Device n Interrupt Enable Register (61)Figure 7-41. Device n Address Register (63)Figure 7-42. Device n Status Register (63)Figure 7-43. Device n Frame Number Register (65)Figure 7-44. Device n SOF/EOP Count Register (66)Figure 7-45. OTG Registers (66)Figure 7-46. OTG Control Register (66)Figure 7-47. GPIO Registers (68)Figure 7-48. GPIO Control Register (68)Figure 7-49. GPIO n Output Data Register (70)Figure 7-50. GPIO n Input Data Register (70)Figure 7-51. GPIO n Direction Register (71)Figure 7-52. IDE Registers (71)Figure 7-53. IDE Mode Register (71)Figure 7-54. IDE Start Address Register (72)Figure 7-55. IDE Stop Address Register (72)Figure 7-56. IDE Control Register (73)Figure 7-57. HSS Registers (74)Figure 7-58. HSS Control Register (75)Figure 7-59. HSS Baud Rate Register (77)Figure 7-60. HSS Transmit Gap Register (77)Figure 7-61. HSS Data Register (78)Figure 7-62. HSS Receive Address Register (78)Figure 7-63. HSS Receive Counter Register (79)Figure 7-64. HSS Transmit Address Register (79)Figure 7-65. HSS Transmit Counter Register (79)Figure 7-66. HPI Registers (80)Figure 7-67. HPI Breakpoint Register (80)Figure 7-68. Interrupt Routing Register (81)Figure 7-69. SIEXmsg Register (82)Figure 7-70. HPI Mailbox Register (83)Figure 7-71. HPI Status Port (83)Figure 7-72. SPI Registers (85)Figure 7-73. SPI Configuration Register (86)Figure 7-74. SPI Control Register (87)Figure 7-75. SPI Interrupt Enable Register (89)Figure 7-76. SPI Status Register (89)Figure 7-77. SPI Interrupt Clear Register (90)Figure 7-78. SPI CRC Control Register (91)Figure 7-79. SPI CRC Value Register (92)Figure 7-80. SPI Data Register (92)Figure 7-81. SPI Transmit Address Register (93)Figure 7-82. SPI Transmit Count Register (93)Figure 7-83. SPI Receive Address Register (93)Figure 7-84. SPI Receive Count Register (94)Figure 7-85. UART Registers (94)Figure 7-86. UART Control Register (94)Figure 7-87. UART Status Register (95)LIST OF FIGURES (continued)Figure 7-88. UART Data Register (96)Figure 7-89. PWM Registers (96)Figure 7-90. PWM Control Register (97)Figure 7-91. PWM Maximum Count Register (98)Figure 7-92. PWM n Start Register (99)Figure 7-93. PWM n Stop Register (99)Figure 7-94. PWM Cycle Count Register (100)Figure 8-1. EZ-Host Pin Diagram (101)LIST OF TABLESTable 4-1. Interface Options for GPIO Pins (12)Table 4-2. Interface Options for External Memory Bus Pins (12)Table 4-3. USB Port Configuration Options (13)Table 4-4. USB Interface Pins (14)Table 4-5. OTG Interface Pins (14)Table 4-6. External Memory Interface Pins (16)Table 4-7. UART Interface Pins (18)Table 4-8. I2C EEPROM Interface Pins (18)Table 4-9. SPI Interface Pins (19)Table 4-10. HSS Interface Pins (20)Table 4-11. PWM Interface Pins (20)Table 4-12. HPI Interface Pins (21)Table 4-13. HPI Addressing (21)Table 4-14. IDE Throughput (22)Table 4-15. IDE Interface Pins (22)Table 4-16. Charge Pump Interface Pins (23)Table 4-17. Charge Pump Interface Pins (24)Table 4-18. Crystal Pins (25)Table 4-19. Boot Configuration Interface (25)Table 5-1. Wakeup Sources (27)Table 7-1. Bank Register Example (31)Table 7-2. CPU Speed Definition (32)Table 7-3. Force Select Definition (38)Table 7-4. Memory Arbitration Select (38)Table 7-5. Period Select Definition (41)Table 7-6. USB Data Line Pull-up and Pull-down Resistors (44)Table 7-7. Port A/B Force D± State (44)Table 7-8. Port Select Definition (47)Table 7-9. PID Select Definition (49)Table 7-10. Mode Select Definition (69)Table 7-11. Mode Select Definition (72)Table 7-12. IDE PIO Port Registers (74)Table 7-13. Scale Select Field Definition for SCK Frequency (86)Table 7-14. CRC Mode Definition (91)Table 7-15. UART Baud Select Definition (95)Table 7-16. Prescaler Select Definition (97)Table 9-1. Pin Descriptions (101)Table 12-1. Crystal Requirements (105)Table 13-1. DC Characteristics (105)Table 13-2. DC Characteristics: Charge Pump (106)Table 15-1. Register Summary (114)Table 16-1. Ordering Information (118)1.0 INTRODUCTIONEZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable I/O interface block allowing a wide range of interface options.Figure 1-1. Block Diagram1.1EZ-Host Features•Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and four USB ports•Support for USB On-The-Go (OTG) protocol•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed•Configurable I/O block supporting a variety of I/O options or up to 32 bits of General Purpose I/O (GPIO)•4K x 16 internal masked ROM containing built-in BIOS that supports a communication ready state with access to I2C EEPROM Interface, external ROM, UART, or USB•8K x 16 internal RAM for code and data buffering•Extended memory interface port for external SRAM and ROM•16-bit parallel Host Port Interface (HPI) with a DMA/Mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip SIEs•Fast serial port supports from 9600 baud to 2.0 Mbaud•SPI support in both master and slave•On-chip 16-bit DMA/Mailbox data path interface•Supports 12-MHz external crystal or clock•3.3V operation•Package option — 100-pin TQFP2.0 Typical ApplicationsEZ-Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications. It is primarily intended to enable host capability in applications such as:•Set-top boxes•Printers•KVM switches•Kiosks•Automotive applications•Wireless access points.3.0 Functional Overview3.1Processor Core3.1.1ProcessorEZ-Host has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.3.1.2ClockingEZ-Host requires a 12-MHz source for clocking. Either an external crystal or TTL level oscillator may be used. EZ-Host has an internal PLL that produces a 48-MHz internal clock from the 12-MHz source.3.1.3MemoryEZ-Host has a built-in 4K × 16 masked ROM and an 8K × 16 internal RAM. The masked ROM contains the EZ-Host BIOS. The internal RAM can be used for program code or data.3.1.4InterruptsEZ-Host provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts.3.1.5General Timers and Watchdog TimerEZ-Host has two built-in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-Host.3.1.6Power ManagementEZ-Host has one main power saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.4.0 Interface DescriptionsEZ-Host has a wide variety of interface options for connectivity. With several interface options available, EZ-Host can act as a seamless data transport between many different types of devices.See Table4-1 and Table4-2 to understand how the interfaces share pins and which can coexist. It should be noted that some interfaces have more then one possible port location selectable through the GPIO Control Register [0xC006]. Below are some general guidelines:•HPI and IDE interfaces are mutually exclusive.•If 16-bit external memory is required, then HSS and SPI default locations must be used.•I2C EEPROM and OTG do not conflict with any interfaces.Notes:1.Default interface location.2.Alternate interface location.Table 4-1. Interface Options for GPIO Pins GPIO Pins HPIIDEPWMHSSSPIUARTI2C OTGGPIO31SCL/SDA GPIO30SCL/SDAGPIO29OTGIDGPIO28TX [1]GPIO27RX [1]GPIO26PWM3CTS [1]GPIO25GPIO24INT IOREADY GPIO23nRD IOR GPIO22nWR IOW GPIO21nCS GPIO20A1CS1GPIO19A0CS0GPIO18A2PWM2RTS [1]GPIO17A1PWM1RXD [1]GPIO16A0PWM0TXD [1]GPIO15D15D15GPIO14D14D14GPIO13D13D13GPIO12D12D12GPIO11D11D11MOSI [1]GPIO10D10D10SCK [1]GPIO9D9D9nSSI [1]GPIO8D8D8MISO [1]GPIO7D7D7TX [2]GPIO6D6D6RX [2]GPIO5D5D5GPIO4D4D4GPIO3D3D3GPIO2D2D2GPIO1D1D1GPIO0D0D0Table 4-2. Interface Options for External Memory Bus Pins MEM Pins HPIIDEPWMHSS SPIUARTI2COTGD15CTS [2]D14RTS [2]D13RXD [2]D12TXD [2]D11MOSI [2]D10SCK [2]D9nSSI [2]D8MISO [2]D[7:0]A[18:0]CONTROL4.1USB InterfaceEZ-Host has two built-in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combi-nation of Host and Peripheral ports simultaneously as shown in Table4-3.Table 4-3. USB Port Configuration OptionsPort Configurations Port 1A Port 1B Port 2A Port 2BOTG OTG–––OTG + 2 Hosts OTG–Host HostOTG + 1 Host OTG–Host–OTG + 1 Host OTG––HostOTG + 1 Peripheral OTG–Peripheral–OTG + 1 Peripheral OTG––Peripheral4 Hosts Host Host Host Host3 Hosts Any Combination of Ports2 Hosts Any Combination of Ports1 Host Any Port2 Hosts + 1 Peripheral Host Host Peripheral–2 Hosts + 1 Peripheral Host Host–Peripheral2 Hosts + 1 Peripheral Peripheral–Host Host2 Hosts + 1 Peripheral–Peripheral Host Host1 Host + 1 Peripheral Host–Peripheral–1 Host + 1 Peripheral Host––Peripheral1 Host + 1 Peripheral–Host–Peripheral1 Host + 1 Peripheral–Host Peripheral–1 Host + 1 Peripheral Peripheral–Host–1 Host + 1 Peripheral Peripheral––Host1 Host + 1 Peripheral–Peripheral–Host1 Host + 1 Peripheral–Peripheral Host–2 Peripherals Peripheral–Peripheral–2 Peripherals Peripheral––Peripheral2 Peripherals–Peripheral–Peripheral2 Peripherals–Peripheral Peripheral–1 Peripheral Any Port4.1.1USB Features•USB 2.0-compliant for full and low speed•Up to four downstream USB host ports•Up to two upstream USB peripheral ports•Configurable endpoint buffers (pointer and length), must reside in internal RAM•Up to eight available peripheral endpoints (one control endpoint)•Supports Control, Interrupt, Bulk, and Isochronous transfers•Internal DMA channels for each endpoint•Internal pull-up and pull-down resistors•Internal Series termination resistors on USB data lines4.1.2USB Pins.Table 4-4. USB Interface PinsPin Name Pin NumberDM1A22DP1A23DM1B18DP1B19DM2A9DP2A10DM2B4DP2B54.2OTG InterfaceEZ-Host has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A.4.2.1OTG Features•Internal Charge Pump to supply and control VBUS•VBUS Valid Status (above 4.4V)•VBUS Status for 2.4V< VBUS <0.8V•ID Pin Status•Switchable 2KΩ internal discharge resistor on VBUS•Switchable 500Ω internal Pull-up resistor on VBUS•Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines4.2.2OTG Pins.Table 4-5. OTG Interface PinsPin Name Pin NumberDM1A22DP1A23OTGVBUS11OTGID41CSwitchA13CSwitchB124.3External Memory InterfaceEZ-Host provides a robust interface to a wide variety of external memory arrays. All available external memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF. 4.3.1External Memory Interface Features•Supports 8-bit or 16-bit SRAM or ROM•SRAM or ROM can be used for code or data space•Direct addressing of SRAM or ROM•Two external memory mapped page registers4.3.2External Memory Access StrobesAccess to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle. Up to seven wait state cycles may be inserted for external memory access. Each additional wait state cycle stretches the external memory access time by 21 nsec. An external memory device with 12-nsec access time is necessary to support 48-MHz code execution.4.3.3Page RegistersEZ-Host allows extended data or program code to be stored in external SRAM, or ROM. The total size of extended memory can be up to 512K bytes. The CY16 processor can access extended memory via two address regions of 0x8000-0x9FFF and 0xA000-0xBFFF. The page register 0xC018 can be used to control the address region 0x8000-0x9FFF and the page register 0xC01A controls the address region of 0xA000-0xBFFF.Figure4-1 illustrates that when the nXMEMSEL pin is asserted the upper CPU address pins are driven by the contents of the Page x Registers.Figure 4-1. Page n Registers External Address Pins Logic4.3.4Merge ModeMerge modes enabled through the External Memory Control Register [0xC03] allow combining of external memory regions in accordance with the following:•nXMEMSEL is active from 0x8000 to 0xBFFF•nXRAMSEL is active from 0x4000 to 0x7FFF when RAM Merge is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when RAM Merge is enabled•nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled; nXROMSEL is active from 0x8000 to 0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM Merge is enabled4.3.5Program Memory Hole DescriptionCode residing in the 0xC000-0xC0FF address space is not accessible by the cpu.4.3.6DMA to External Memory ProhibitedEZ-Host supports an internal DMA engine to rapidly move data between different functional blocks within the chip. This DMA engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can only transfer data between the specified block and internal RAM or ROM. Setting up the DMA engine to transfer to or from an external memory space might result in internal RAM data corruption because the hardware (i.e HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address range. For example, setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000.External Memory Related Resource Considerations:•By default A[18:15] are not available for general addressing and are driven high on power up. The Upper Address Enable Register must be written appropriately to enable A[18:15] for general addressing purposes.•47k ohm external pull-up on A15-pin for 12-MHz crystal operation.•During the 3-msec BIOS boot procedure the CPU external memory bus is active.•ROM boot load value 0xC3B6 located at 0xC100.•HPI, HSS, SPI, SIE1, SIE2, and IDE can't DMA to external memory arrays.•Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF.•Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF.•CPU memory bus strobes may wiggle when chip selects are inactive.4.3.7External Memory Interface PinsTable 4-6. External Memory Interface PinsPin Name Pin Number nWR64nRD62 nXMEMSEL (optional nCS)34nXROMSEL (ROM nCS)35nXRAMSEL (RAM nCS)36A1896A1795A1697A1538A1433A1332A1231A1130A1027A925A824A720A617A58A47A33A22A11nBEL/A099nBEH98D1567D1468D1369D1270D1171D1072D973D874D776D677D578D479D380D281D182D0834.3.8External Memory Interface Block DiagramsFigure4-2 illustrates how to connect a 64k × 8 memory array (SRAM/ROM) to the EZ-Host external memory interface.Figure 4-2. Interfacing to 64k × 8 Memory ArrayFigure4-3 illustrates the interface for connecting a 16-bit ROM or 16-bit RAM to the EZ-Host external memory interface. In 16-bit mode, up to 256K words of external ROM or RAM are supported. Note that the Address lines do not map directly.Figure 4-3. Interfacing up to 256k × 16 for External Code/DataFigure4-4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bit mode, up to 512K bytes of external ROM or RAM are supported.Figure 4-4. Interfacing up to 512k × 8 for External Code/Data4.4General Purpose I/O Interface (GPIO)EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs.4.4.1GPIO DescriptionAll Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are latched directly into registers, a single flip-flop.4.4.2Unused Pin DescriptionsUnused USB pins should be three-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled low through the internal pull-down resistor.Unused GPIO pins should be configured as outputs and driven low.4.5UART InterfaceEZ-Host has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins.4.5.1UART Features•Supports baud rates of 900 to 115.2K•8-N-14.5.2UART Pins.Table 4-7. UART Interface PinsPin Name Pin NumberTX42RX434.6I2C EEPROM InterfaceEZ-Host provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation for additional details on this interface.4.6.1I2C EEPROM Features•Supports EEPROMs up to 64KB (512K bit)•Auto-detection of EEPROM size4.6.2I2C EEPROM Pins.Table 4-8. I2C EEPROM Interface PinsPin Name Pin NumberSMALL EEPROMSCK39SDA40LARGE EEPROMSCK40SDA394.7Serial Peripheral InterfaceEZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port.。

© Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 31Publication Order Number:MPN3404/DMPN3404Silicon Pin DiodeThis device is designed primarily for VHF band switching applications but is also suitable for use in general−purpose switching circuits. It is supplied in a cost−effective TO−92 type plastic package for economical, high−volume consumer and industrial requirements. Features•Rugged PIN Structure Coupled with Wirebond Construction for Optimum Reliability•Low Series Resistance @ 100 MHz: R S = 0.7 W (Typ) @ I F = 10 mAdc •Sturdy TO−92 Style Package for Handling Ease•Pb−Free Packages are Available*MAXIMUM RATINGSRating Symbol Value Unit Reverse Voltage V R20VdcForward Power Dissipation @ T A = 25°CDerate above 25°C P D4004.0mWmW/°CJunction Temperature T J+125°C Storage Temperature Range T stg−55 to +150°C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted)Characteristic Symbol Min Typ Max Unit Reverse Breakdown Voltage(I R = 10 m Adc)V(BR)R20−−VdcDiode Capacitance(V R = 15 Vdc, f = 1.0 MHz)C T− 1.3 2.0pFSeries Resistance (Figure 5)(I F = 10 mAdc)R S−0.70.85WReverse Leakage Current(V R = 15 Vdc)I R−−0.1m Adc*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.MARKING DIAGRAMA= Assembly LocationY= YearWW= Work WeekG= Pb−Free PackageDevice ShippingORDERING INFORMATIONMPN3404TO−92MPN3404G TO−92(Pb−Free)(Note: Microdot may be in either location)MPN3403AYWW GGPackage1000 Units / Bulk1000 Units / Bulk2TYPICAL CHARACTERISTICSFigure 2. Forward VoltageV F , FORWARD VOLTAGE (VOLTS)Figure 3. Diode Capacitance T A , AMBIENT TEMPERATURE (°C)Figure 4. Leakage Current5040, R E V E R S E C U R R E N T ( A )1000.010.001I R 0.11.0101.61.20.80.4R S , S E R I E S R E S I S T A N C E (O H M S )1.41.00.61.83020100I F , F O R W A R D C U R R E N T (m A )V R , REVERSE VOLTAGE (VOLTS)C T , D I O D E C A P A C I T A N C E (p F )μ0.040.0044.0400.4PACKAGE DIMENSIONSNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.CONTOUR OF PACKAGE BEYOND ZONE R IS UNCONTROLLED.4.LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM.STYLE 1:PIN 1.ANODE2.CATHODEPLANEDIM MIN MAX MIN MAX MILLIMETERS INCHESA 0.1750.205 4.45 5.21B 0.1700.210 4.32 5.33C 0.1250.165 3.18 4.19D 0.0160.0210.4070.533G 0.050 BSC 1.27 BSC H 0.100 BSC 2.54 BSC J 0.0140.0160.360.41K 0.500−−−12.70−−−L 0.250−−− 6.35−−−N 0.0800.105 2.03 2.66P −−−0.050−−− 1.27R 0.115−−− 2.93−−−V 0.135−−− 3.43−−−TO−92 (TO−226)CASE 182−06ISSUE LON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息: ONSEMIMPN3404G。