IMX8中文资料

MaaXBoard (EM-MC-SBC-IMX8M) Hardware User ManualV1.2Copyright Statement:The MaaXBoard single board computer (partnumber: EM-MC-SBC-IMX8M) and its relatedintellectual property are owned by Avnet Manufacturing Services.Avnet Manufacturing Services has the copyright of this document and reserves all rights. Any part ofthe document should not be modified, distributed or duplicated in any approach and form with the written permission issued by Avnet Manufacturing Services.Disclaimer:Avnet Manufacturing Services does not take warranty of any kind, either expressed or implied, as tothe program source code, software and documents provided along with the products, and including, but not limited to, warranties of fitness for a particular purpose; The entire risk as to the quality or performance of the program is with the user of products.Regulatory Compliance:MaaXBoard single board computer has passed the CE, FCC & SRRC certification.Revision HistoryRev. Description Author DateV1.0 Update description Hugo 20190815Hugo 20191121 V1.1 Update block diagram, picture anddescriptionV1.2 Add SRRC description Hugo 20200527CatalogRevision History (3)Chapter 1Product Overview (8)1.1Brief Introduction (8)1.2System Block Diagram (8)1.3Packing List (9)1.4Product Specifications (9)1.5Other Customer Provide Parts (10)1.6Interface Locations (11)1.7Product Dimensions (mm) (12)1.8Height Distribution (mm) (13)Chapter 2Introduction of Hardware System (14)2.1MaaXBoard Hardware Installation and Start up (14)2.1.1Installation (14)2.1.2Booting Configuration (14)2.2Details of Interfaces (15)2.2.1POWER IN (15)2.2.2Button (16)2.2.3HDMI (17)2.2.4USB Host (19)2.2.5RJ-45 (21)2.2.6Camera (23)2.2.740 Pin Expansion Pin Header (26)2.2.8Wi-Fi/Bluetooth (Optional) (30)2.2.9Micro SD Card (TF Card) (32)2.2.10Extend Interface J26 (34)2.2.11Extend Interface J23 (36)2.2.12MIPI-DSI (37)2.3Introduction of Peripheral Chips (40)2.3.1AR8035 (40)2.3.2BD71837 (40)2.3.3AW-CM256SM (40)Chapter 3Appendix (41)3.1Software (41)Chapter 4Technical Support and Warranty (42)4.1Technical Support (42)4.2Warranty Conditions (42)Chapter 5Contact Information (44)FigureFigure 1.1 MaaXBoard System Block Diagram (8)Figure 1.2 MaaXBoard Top View (11)Figure 1.3 MaaXBoard Bottom View (11)Figure 1.4 Product Dimensions (12)Figure 1.5 Height Distribution (13)Figure 2.1 USB Type C Slot (15)Figure 2.2 Button (16)Figure 2.3 HDMI Connector (17)Figure 2.4 Double-layer USB Host connector (19)Figure 2.5 RJ45 Connector (21)Figure 2.6 Camera Connector (23)Figure 2.7 2.54mm Double Row Pin Header (26)Figure 2.8 40Pin Pin Header Pin1 Position (27)Figure 2.9 IPEX Antenna Connector (30)Figure 2.10 Onboard Ceramic Antenna (31)Figure 2.11 Micro SD Card Slot (32)Figure 2.12 12Pin Wafer Connector (34)Figure 2.13 12Pin Wafer Connector (36)Figure 2.14 30 Pin FPC Connector (MIPI-DSI) (37)TableTable 2.1 HDMI Pin Definitions (18)Table 2.2 USB Interface Pin Definition (20)Table 2.3 Ethernet Interface Pin Definition (22)Table 2.4 Camera Connector Pin Definition (24)Table 2.5 40 Pin Expansion Pin Header Definition (27)Table 2.6 Antenna Connector Pin Definition (30)Table 2.7 Micro SD Card Slot Pin Definition (33)Table 2.8 12Pin Definition (35)Table 2.9 J23 Pin Definition (36)Table 2.10 J16 Pin Definition (38)Chapter 1 Product Overview1.1 Brief IntroductionMaaXBoard is a development board for makers, designed by Avnet Manufacturing Services. The MaaXBoard is a single board computer based on NXP IMX8M SOC series, which can be used for the areas such as medical instruments, video surveillance, communications, IOT, makers and so on.In the design of a compact body size, it is provided with rich resources of peripheral interface, include: Gigabit Ethernet interface, USB 3.0 interface, MIPI-DSI interface, MIPI-CSI interface, HDMI interface, Micro SD Card interface, UART interface, GPIO interface, Wi-Fi/Bluetooth interface, etc.1.2 System Block DiagramFigure 1.1 MaaXBoard System Block Diagram1.3 Packing List1 ×MaaXBoard1 × Desiccant1 × Anti-static Bag1 × Safety Flyer1 × Quick Start Guide2 × Electrostatic Foam1 × Box1.4 Product SpecificationsGeneral Specifications:Operating Temperature: 0~70°C (When the CPU loads heavy, need a heatsink)Power Supply: 5V/3A (Power Adapter)Operating Humidity: 20% ~ 90% (non-condensing)Dimensions: 85mm × 55mmPCB Layers：10LayersCommunication Interface:1 × 40 Pin IO Interface (Expand I2C, SPI, UART, I2S Interface)1 × MIPI-CSI Camera Interface1 × MIPI-DSI Display Interface1 ×Gigabit Ethernet interface (RJ45)2 × USB3.0 Host1 × Micro SD Card (TF Card) Interface1 × 8bits and 1x 7bits GPIO Interface (Support Audio peripheral expand)1 × HDMI 2.0 Interface1 × Power Interface (USB Type C Connector)1 × Power Button2 × User Button1 × Wi-Fi/Bluetooth2 × User LED1.5 Other Customer Provide PartsTo use the various functions of MaaXBoard, customer should also provide the following parts which are not contained in MaaXBoard Packages.1 × USB to serial cable (TTL)1 × 1Gbps Network Cable1 × Camera Module1 × MIPI-DSI Displayer1 × 5V/3A Power Supply (USB Type C Interface)1 × HDMI Cable1 × HDMI DisplayerOther tools needed to implement related function1.6 Interface LocationsFigure 1.2 MaaXBoard Top ViewFigure 1.3 MaaXBoard Bottom View1.7 Product Dimensions (mm)Figure 1.4 Product Dimensions1.8 Height Distribution (mm)Figure 1.5 Height Distribution Note: There is tolerance in height due to mechanical treatment.Chapter 2 Introduction of Hardware SystemThis chapter will introduce the structure, expansion and peripheral interfaces of MaaXBoard hardware system in details.2.1 MaaXBoard Hardware Installation and Start upBefore power up MaaXBoard, you need to connect all necessary peripheral devices, then power on the board.According to the manufactured configuration, MaaXBoard supports two boot mode: boot from Micro SD card or boot from eMMC. These two boot mode is mutual exclusion. If users choose to boot from Micro SD card, they should burn the latest image to the card on PC, then install the card to the board, refer to the software user manual. If users choose to boot from eMMC, just power on the board.Note: If the eMMC firmware is destroyed by accident, users could update the eMMC image in USB Download mode. Please operate carefully and follow the steps in software user manual strictly to avoid damaging the product.2.2 Details of InterfacesThis section will introduce the constructions, principles, interface definitions and considerations of use of MaaXBoard peripherals in detail, so that users may have a deep understanding of the hardware circuitry of the board.MaaXBoard use a USB Type C interface as the +5V power in. Note that the USB Type C interface only provides power supply function, do not support data communication.The Power adapter should support 3A or above current output.Figure 2.1 USB Type C SlotThere are 3 buttons on the MaaXBoard, S2 as the system power button for the board, S3 and S4 as user button.Figure 2.2 ButtonPowerful video display is an important feature of MaaXBoard. The HDMI 2.0 interface support up to 4096 x 2160 at 60Hz display output.J9 is the interface for connecting an HDMI display device on the MaaXBoard, which is a standard HDMI 19Pin connector. Its specification and dimension as follows:Figure 2.3 HDMI ConnectorTable 2.1 HDMI Pin DefinitionsMaaXBoard provides a Double-layer USB Host connector (J5), the two USB port are two independent controllers, and each one could provide full speed USB3.0 data communication function, used to extend external devices in USB protocol.Figure 2.4 Double-layer USB Host connectorTable 2.2 USB Interface Pin DefinitionJ13 is the physical interface of Gigabit Ethernet, the interface information is shown in the following picture:Figure 2.5 RJ45 ConnectorTable 2.3 Ethernet Interface Pin DefinitionJ12 on the MaaXBoard is a 30-pin FPC connector that supports MIPI 2Lane Camera input. The following picture shows the information of J12:Figure 2.6 Camera ConnectorTable 2.4 Camera Connector Pin DefinitionJ10 on the MaaXBoard is a 40 pin Extend Interface, used to support external devices. The following picture shows the information of the 40 Pin expansion connector J10:Figure 2.7 2.54mm Double Row Pin HeaderFigure 2.8 40Pin Pin Header Pin1 Position Table 2.5 40 Pin Expansion Pin Header DefinitionMaaXBoard employs a Wi-Fi/Bluetooth module to support Wi-Fi 2.4G/5G Frequency, and Bluetooth V4.2 standard. The Wi-Fi/Bluetooth antennas have two type: onboard ceramic antenna or IPEX antenna.IPEX antenna (customized version)IPEX antenna is empty welding in default, if the customer needs to use this interface, please contact the Avnet Manufacturing Services to customize.IPEX antenna connector’s specification as follows:Figure 2.9 IPEX Antenna ConnectorTable 2.6 Antenna Connector Pin DefinitionOnboard Ceramic Antenna (Default)Onboard Ceramic Antenna’s specification as follows:Figure 2.10 Onboard Ceramic AntennaMicro SD card (TF Card) is used to start the code, the program system curing storage, or provide external storage function.Figure 2.11 Micro SD Card SlotTable 2.7 Micro SD Card Slot Pin DefinitionJ26 on the MaaXBoard is a 12 pin Wafer connector, used to support GPIO function. The following picture shows the information of the 12 pin Wafer connector J26:Figure 2.12 12Pin Wafer ConnectorTable 2.8 12Pin DefinitionJ23 on the MaaXBoard is a 12 pins Wafer connector, used to support GPIO function. The following picture shows the information of the 12 pins Wafer connector J23:Figure 2.13 12Pin Wafer ConnectorTable 2.9 J23 Pin DefinitionJ16 on the MaaXBoard is a 30 pin FPC connector that supports MIPI-DSI high-definition and small size screen.The following picture shows the information of 30-pin FPC connector J16:Figure 2.14 30 Pin FPC Connector (MIPI-DSI)Table 2.10 J16 Pin Definition2.3 Introduction of Peripheral ChipsAR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver. The AR8035 is a single port 10/100/1000 Mbps Tri-speed Ethernet PHY, which provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks, etc.AR8035 supports IEEE 802.3az Energy Efficient Ethernet (EEE) standard and Atheros proprietary SmartEEE, which allows legacy MAC/SoC devices without 802.3az support to function as the complete 802.3az system.BD71837MWV integrated all the power voltage for iMX8M, include the peripheral power voltage, which significantly reduce the difficulty when customer develop the system, shorten the development cycle and the manufacture period of the product.BD71837MWV is Power Management IC specially designed for iMX8M by ROHM Semiconductor. It integrates 8 Buck regulators and 7 LDOs, support the processor to dynamically adjust the power to achieve the goal of energy saving. The chip provides 1.8V/3.3V optional MMC card power supply at the same time. Users could choose 1.8V or 3.3V output by change the resistor, to fit multimedia card with various type and protocol. It provides a 32.768 kHz Crystal Oscillator Driver which could power to the clock circuit directly. It also provides several protection modes: output short circuit, output overvoltage/current, over thermal protection, etc.The AW-CM256SM wireless module is compliant with the IEEE 802.11a/b/g/n/ac standard, support connection up to 433.3Mbps transmit/receive (connect to WLAN using 802.11 ac protocol).AW-CM256SM module provide SDIO interface Wi-Fi, UART/PCM interface Bluetooth Function. It enables a low power consumption and high performance solution that fit for IOT and other application field.Chapter 3 Appendix3.1 SoftwareMaaXBoard support Linux Yocto system and Android system, for the detail software introduction, please refer to related user manual.LinuxMaaXBoard Linux Software Release NoteMaaXBoard Linux Software User ManualMaaXBoard Linux Software Development GuideAndroidMaaXBoard Android Software Release NoteMaaXBoard Android Software User ManualMaaXBoard Android Development GuideChapter 4 Technical Support and Warranty4.1 Technical SupportAvnet Manufacturing Services provides its product with one-year free technical support including:Providing software and hardware resources related to the embedded products of AvnetManufacturing Services;Helping customers properly compile and run the source code provided by Avnet ManufacturingServices;Providing technical support service if the embedded hardware products do not function properlyunder the circumstances that customers operate according to the instructions in the documents provided by Avnet Manufacturing Services;Helping customers troubleshoot the products.The following conditions will not be covered by our technical support service. We will take appropriatemeasures accordingly:Customers encounter issues related to software or hardware during their development process;Customers encounter issues caused by any unauthorized alter to the embedded operatingsystem;Customers encounter issues related to their own applications;Customers encounter issues caused by any unauthorized alter to the source code provided byAvnet Manufacturing Services.4.2 Warranty Conditions12-month free warranty on the PCB under normal conditions of use since the sales of the product;The following conditions are not covered by free services; Avnet Manufacturing Services will chargeaccordingly:Customers fail to provide valid purchase vouchers or the product identification tag is damaged,unreadable, altered or inconsistent with the products;Not according to the user's manual operation causes damage to the product;Products are damaged in appearance or function caused by natural disasters (flood, fire,earthquake, lightning strike or typhoon) or natural aging of components or other force majeure;Products are damaged in appearance or function caused by power failure, external forces, water,animals or foreign materials;Products malfunction caused by disassembly or alter of components by customers or, productsdisassembled or repaired by persons or organizations unauthorized by Avnet ManufacturingServices, or altered in factory specifications, or configured or expanded with the componentsthat are not provided or recognized by Avnet Manufacturing Services and the resulted damage in appearance or function;Product failures caused by the software or system installed by customers or inappropriatesettings of software or computer viruses;Products purchased from unauthorized sales;Warranty (including verbal and written) that is not made by Avnet Manufacturing Services andnot included in the scope of our warranty should be fulfilled by the party who committed. Avnet Manufacturing Services has no any responsibility.Within the period of warranty, the freight for sending products from customers to AvnetManufacturing Services should be paid by customers; the freight from Avnet Manufacturing Services to customers should be paid by us. The freight in any direction occurs after warranty period should be paid by customers;Please contact technical support if there is any repair request.Avnet Manufacturing Services will not take any responsibility on the products sent backwithout the permission of the company.Chapter 5 Contact InformationTel: +86-755-33190846/33190847/33190848E-mail:Technicalsupport:***********************Salescontact:**************************Fax: +86-755-25616057Website: /Address: Tower B 4/F, Shanshui Building, Nanshan Yungu Innovation Industry Park, LiuxianAve.No.4093,Nanshan District, Shenzhen, Guangdong, China。

基于IMX8MM全自动多通道荧光免疫分析仪系统设计在医学、生命科学和诊断领域，荧光免疫分析技术被广泛应用于病毒检测、蛋白质分析和生物标记物检测等方面。

为了提高实验效率和准确性，全自动多通道荧光免疫分析仪系统成为了研究人员和医生们的首选。

本文将基于IMX8MM处理器，设计一种高性能、稳定可靠的全自动多通道荧光免疫分析仪系统。

系统的设计包括硬件和软件两个方面。

一、硬件设计1. 系统架构设计全自动多通道荧光免疫分析仪系统的硬件架构是关键。

我们采用IMX8MM处理器作为核心处理单元，搭建基于ARM架构的嵌入式系统。

该处理器具有低功耗、高性能和强大的图像处理能力，非常适合用于荧光免疫分析仪系统。

2. 传感器和信号采集为了实现对样本中荧光标记物的检测和分析，我们需要选择合适的传感器和进行信号采集。

例如，我们可以使用光电二极管作为荧光信号的接收器，并选择合适的滤光片以过滤其他光源对荧光信号的干扰。

此外，还需要选择合适的放大器和滤波器来增强信号质量和降低噪声。

3. 液体处理系统全自动多通道荧光免疫分析仪系统需要具备液体处理的功能，包括样本输入、试剂输入和废液排放等。

我们可以设计一个具有多个通道的自动进样系统，通过控制液泵和阀门来实现样本和试剂的输入和排放。

4. 存储和通信系统为了方便数据的处理和分析，系统需要具备存储和通信的功能。

我们可以使用高速的存储器来保存检测结果和相关数据，并且通过以太网或者无线通信模块与计算机进行数据传输。

二、软件设计1. 系统控制和操作界面全自动多通道荧光免疫分析仪系统的软件设计需要实现对硬件的控制和操作。

我们可以使用嵌入式操作系统，开发相应的驱动程序和控制逻辑，实现系统的自动化控制。

此外，还需要设计直观友好的操作界面，方便用户的操作和数据查看。

2. 数据处理和分析荧光免疫分析仪系统收集到的数据需要进行处理和分析，以得到准确的结果。

我们可以使用图像处理算法对荧光信号进行分析和提取，通过统计学方法处理数据，得出相应的浓度和阳性阴性结果。

iMX8M系列技术贴iMX8MMuboot添加新的显示支持OKMX8MM-C开发板基于NXP公司的i.MX8MMini 四核64位处理器设计，采用核心板+底板结构，主频最高1.8GHz，Cortex-A53架构；2GB DDR4 RAM，支持一个通用型Cortex®-M4 400MHz 内核处理器提供多种外设接口，如MIPI-CSI、MIPI-DSI、USB、PCIe、UART 、eCSPI 、IIC和千兆以太网。

本文主要讲解OKMX8MM-C开发板平台uboot添加新的显示支持。

一、MIPI接口能够连接的显示设备OKMX8MM-C开发板只有一个MIPI DSI显示接口，这个接口除了可以连接MIPI显示屏，还可以通过MIPI转LVDS模块，连接LVDS 显示屏或HDMI显示屏。

其中MIPI显示屏还分为需要配置和不需要配置的。

1、不需要配置的MIPI屏MIPI接口的显示屏分为需要DSI进入命令模式配置后才能显示的MIPI屏和不需要配置的MIPI屏。

不需要配置的MIPI屏比较简单，只要MIPI DSI接口正常输出信号就能正常显示，飞凌嵌入式OKMX8MM-C开发板提供的1024x600分辨率的7寸MIPI屏就是一块不需要配置的MIPI屏，它默认就工作在4lanes高速模式下，只需要将CPU内的显示相关的模块配置好，并让其开始工作，MIPI屏就能够正常显示。

2、需要配置的MIPI屏需要配置的MIPI屏，DSI接口在输出显示信号前需要进入命令模式对显示屏进行配置，配置参数一般由屏体厂家提供。

NXP i.MX8MM 评估套件使用的OLED屏RM67191，就是一款需要配置的MIPI显示屏。

3、MIPI转LVDS和HDMI模块这个模块能将MIPI信号转换为LVDS或HDMI信号，通过这个模块可以连接LVDS显示屏或者HDMI显示屏。

MIPI转LVDS&HDMI 模块需要通过I2C配置转接，将包含对应的显示屏的显示参数等信息配置到芯片内，然后MIPI接口输出对应的显示信号。

Preview of i.MX 8M Plus Applications Processor Reference ManualGet entire reference manual (7406 pages, PDF)Document Number: IMX8MPRMRev. 1, 06/2021ContentsSection number Title PageChapter 1Introduction1.1Product Overview (9)1.2Target Applications (9)1.3Acronyms and Abbreviations (9)1.4Architectural Overview (12)Chapter 2Memory Map2.1Memory system overview (23)2.2Cortex-A53 Memory Map (24)2.3Cortex-M7 Memory Map (26)2.4DMA memory maps (29)2.5AIPS Memory Maps (30)2.6DAP Memory Map (36)2.7Audio Processor Memory Map (38)2.8HDMI_TX Subsystem Memory Map (38)Chapter 3Security3.1System Security (41)3.2Resource Domain Controller (RDC) (44)Chapter 4Arm Platform and Debug4.1Arm Cortex A53 Platform (A53) (91)4.2Arm Cortex M7 Platform (CM7) (97)4.3Messaging Unit (MU) (99)4.4Semaphore (SEMA4) (143)4.5On-Chip RAM Memory Controller (OCRAM) (161)4.6Network Interconnect Bus System (NIC) (164)4.7AHB to IP Bridge (AIPSTZ) (165)4.8Shared Peripheral Bus Arbiter (SPBA) (188)4.9TrustZone Address Space Controller (TZASC) (201)4.10System Debug (203)4.11System Counter (SYS_CTR) (207)Chapter 5Clocks and Power Management5.1Clock Control Module (CCM) (227)5.2General Power Controller (GPC) (566)5.3Crystal Oscillator (XTALOSC) (718)5.4Thermal Monitoring Unit (TMU) (722)Chapter 6SNVS, Reset, Fuse, and Boot6.1System Boot (741)6.2Fusemap (808)6.3On-Chip OTP Controller (OCOTP_CTRL) (824)6.4Secure Non-Volatile Storage (SNVS) (868)6.5System Reset Controller (SRC) (897)6.6Watchdog Timer (WDOG) (968)Chapter 7Interrupts and DMA7.1Interrupts and DMA Events (987)7.2Smart Direct Memory Access Controller (SDMA) (1008)7.3Enhanced Direct Memory Access (eDMA) (1256)7.4Interrupt Request Steering (IRQ_STEER) (1318)Chapter 8Chip IO and Pinmux8.1External Signals and Pin Multiplexing (1329)8.2IOMUX Controller (IOMUXC) (1352)8.3General Purpose Input/Output (GPIO) (1982)Chapter 9External Memory9.1External Memory Overview (2001)9.2DDR Controller (DDRC) (2003)9.3DDR BLK_CTRL (2164)9.4DDR PHY (DDR_PHY) (2166)9.5AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) (2177)9.662BIT Correcting ECC Accelerator (BCH) (2217)9.7General Purpose Media Interface (GPMI) (2280)Chapter 10Mass Storage10.1Enhanced Configurable SPI (ECSPI) (2339)10.2FlexSPI Controller (FlexSPI) (2369)10.3Ultra Secured Digital Host Controller (uSDHC) (2500)Chapter 11Connectivity11.1HSIO BLK_CTRL (2659)11.2Universal Serial Bus Controller (USB) (2680)11.3Universal Serial Bus PHY (USB_PHY) (2993)11.4PCI Express (PCIe) (2997)11.5PCI Express PHY (PCIe_PHY) (3369)11.6Ethernet MAC (ENET) (3754)11.7Ethernet Quality Of Service (ENET_QOS) (3957)11.8FlexCAN (4980)Chapter 12Timers12.1General Purpose Timer (GPT) (5123)12.2Pulse Width Modulation (PWM) (5142)Chapter 13Display, Imaging, and Camera13.1Display, Imaging, and Camera Overview (5155)13.2MEDIA BLK_CTRL (5163)13.3LCD Interface (LCDIF) (5233)13.4Image Sensing Interface (ISI) (5265)13.5MIPI CSI Host Controller (MIPI_CSI) (5347)13.6MIPI DSI Host Controller (MIPI_DSI) (5396)13.7MIPI D-PHY (MIPI_DPHY) (5469)13.8LVDS Display Bridge (LDB) (5493)13.9HDMI TX Controller (5496)13.10HDMI TX PHY (5779)13.11HDMI TX BLK_CTRL (5828)13.12HDMI TX Parallel Audio Interface (HTX_PAI) (5859)13.13HDMI TX Parallel Video Interface (HTX_PVI) (5871)13.14Image Signal Processor (ISP) (5895)13.15DeWarp (5901)13.16Machine Learning Neural Processing Unit (NPU) (5907)Chapter 14Audio14.1Audio Overview (5943)14.2AUDIO BLK_CTRL (5947)14.3PDM Microphone Interface (MICFIL) (5977)14.4Synchronous Audio Interface (SAI) (6023)14.5Asynchronous Sample Rate Converter (ASRC) (6077)14.6Enhanced Audio Return Channel (eARC) (6162)14.7Audio DSP (HiFi 4 DSP) (6231)Chapter 15Graphics Processing Unit (GPU)15.1GPU Overview (6239)15.22D Graphics Processing Unit (GPU2D) (6240)15.33D Graphics Processing Unit (GPU3D) (6254)Chapter 16Video Processing Unit (VPU)16.1VPU G1 Decoder (6263)16.2VPU G2 Decoder (6429)16.3VPU VC8000E Encoder (6665)16.4VPU BLK_CTRL (7256)Chapter 17Low Speed Communication and Interconnects17.1I2C Controller (I2C) (7269)17.2Universal Asynchronous Receiver/Transmitter (UART) (7293)Chapter 1Introduction1.1Product OverviewThis chapter introduces the architecture of the i.MX 8M Plus Applications Processor. The i.MX 8M Plus family is a set of NXP products focused on machine learning applications, combining state-of-art multimedia features with high-performance processing optimized for low-power consumption.The i.MX 8M Plus Applications Processor relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster, a Cortex-M7 coprocessor, audio digital signal processor, machine learning and graphics accelerators.The i.MX 8M Plus provides additional computing resources and peripherals:•Advanced security modules for secure boot, cipher acceleration and DRM support •A wide range of audio interfaces•Large set of peripherals that are commonly used in consumer/industrial markets including USB , PCIe, Ethernet, and CAN1.2Target ApplicationsThe i.MX 8M Plus Media Applications Processor targets applications on:•Smart Homes, Buildings and Cities•Machine Learning and Industrial Automation•Consumer and Pro Audio/Voice Systems1.3Acronyms and AbbreviationsThe table below contains acronyms and abbreviations used in this document.Acronyms and AbbreviationsAcronyms and Abbreviated TermsTerm Meaning ADC Analog-to-Digital ConverterAHB Advanced High-performance BusAIPS Arm IP BusALU Arithmetic Logic UnitAMBA Advanced Microcontroller Bus ArchitectureAPB Advanced Peripheral BusASRC Asynchronous Sample Rate ConverterAXI Advanced eXtensible InterfaceCA/CM Arm Cortex-A/Cortex-MCAAM Cryptographic Acceleration and Assurance Module CA53Arm Cortex A53 CoreCAN Controller Area NetworkCM7Arm Cortex M7 CoreCPU Central Processing UnitCSI CMOS Sensor InterfaceCSU Central Security UnitCTI Cross Trigger InterfaceD-cache Data cacheDAP Debug Access PortDDR Double data rateDMA Direct memory accessDPLL Digital phase-locked loopDRAM Dynamic random access memoryECC Error correcting codesECSPI Enhanced Configurable SPILPSPI Low-power SPIEDMA Enhanced Direct Memory AccessEIM External Interface ModuleENET EthernetEPIT Enhanced Periodic Interrupt TimerEPROM Erasable Programmable Read-Only MemoryETF Embedded Trace FIFOETM Embedded Trace MacrocellFIFO First-In-First-OutGIC General Interrupt ControllerGPC General Power ControllerGPIO General-Purpose I/OGPR General-Purpose RegisterGPS Global Positioning SystemTable continues on the next page...Continue Reading This Reference ManualGet entire reference manual (7406 pages, PDF)Stay informed when design resources related to this product are updated.Go to i.MX 8M Plusi.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/202111NXP Semiconductors。

System-on-Module d atasheetVersion 1.11Features●NXP i MX 8M S oC○Quad-core A RM C ortex-A53,p lus C ortex-M4F○2D/3D V ivante G C7000 L ite G PU a nd V PU●Google E dge T PU M L a ccelerator●Cryptographic c oprocessor●Wi-Fi 2x2 M IMO (802.11b/g/n/ac 2.4/5 G Hz)●Bluetooth 4.2●8 o r 16 G B e MMC●1,2,o r 4G B L PDDR4●USB 3.0●Gigabit E thernet●HDMI a nd M IPI-DSI●MIPI-CSI-2●Up t o 95x G PIO (including S PI,I2C,P WM,U ART,S AI,a nd S DIO)DescriptionThe C oral S ystem-on-Module (SoM)i s a f ully-integrated s ystem t hat h elps y ou b uild e mbedded s ystems t hat d emand f ast machine l earning (ML)i nferencing.I t c ontains N XP's i MX 8M s ystem-on-chip (SoC),e MMC m emory,L PDDR4 R AM,W i-Fi, and B luetooth,b ut i ts u nique p ower c omes f rom G oogle's E dge T PU c oprocessor.The E dge T PU i s a s mall A SIC d esigned b y G oogle t hat a ccelerates T ensorFlow L ite m odels i n a p ower efficient m anner:i t's capable o f p erforming 4t rillion o perations p er s econd (4 T OPS),u sing 2w atts o f p ower—that's 2T OPS p er w att.F or example,t he E dge T PU c an e xecute s tate-of-the-art m obile v ision m odels s uch a s M obileNet v2 a t a lmost 400 f rames p er second.T his o n-device M L p rocessing r educes l atency,i ncreases d ata p rivacy,a nd r emoves t he n eed f or a c onstant internet c onnection.Key b enefits o f t he S oM:●High-speed a nd l ow-power M L i nferencing (4 T OPS @2 W)● A c omplete L inux s ystem (running M endel,a D ebian d erivative)●Small f ootprint (40 x48 m m)The S oM i s a lso i ncluded i n t he C oral D ev B oard ,w hich i s a s ingle-board c omputer t hat e nables f ast p rototyping a nd evaluation o f t he s tandalone S oM.Ordering i nformationPart n umber DescriptionG650-04474-01 Coral S ystem -on -Module w ith 1 G B R AM (8 G B e MMC ) G650-05369-01 Coral S ystem -on -Module w ith 2 G B R AM (8 G B e MMC ) G650-05370-01Coral S ystem -on -Module w ith 4 G B R AM (16 G B e MMC )Table o f c ontentsFeatures 1 Description 1 Ordering i nformation 2 Table o f c ontents 3 1 S ystem c omponents 41.1 B lock d iagrams 72 M echanical d imensions 93 S ystem p ower 93.1 P ower s ignals 103.2 P ower c onsumption 113.3 E dge T PU p ower c haracteristics 124 B oot m ode 135 P eripheral i nterfaces 135.1 M IPI c amera (CSI)145.2 M IPI d isplay (DSI)145.3 H DMI 155.4 E thernet 155.5 P CIe 165.6 U SB 165.7 D igital a udio (SAI)175.8 S ony/Philips a udio (SPDIF)195.9 M icro-SD c ard 205.10 J TAG d ebugging 205.11 I2C 215.12 U ART 215.13 S PI 225.14 G PIO 225.15 P WM 236 W i-Fi a nd B luetooth 237 B aseboard d eveloper g uide 247.1 R eference d esign 247.2 B aseboard c onnectors 247.3 C onnectors,k eepouts,a nd c omponent m ax h eights 247.4 T race i mpedance r ecommendations 257.5 M IPI t race l ength c ompensation 267.6 T hermal m anagement 277.7 O ther r ecommendations 278 P inout s chematic 289 E nvironmental r eliability 2810 D ocument r evisions 291 S ystem c omponentsTable 1. A vailable S oM c omponents a nd f eaturesFeature Details8Arm C ortex-A53 M PCore p latform Quad s ymmetric C ortex-A53 p rocessors:●32 K B L1 I nstruction C ache●32 K B L1 D ata C ache●Support L1 c ache R AMs p rotection w ith p arity/ECCSupport o f 64-bit A rmv8-A a rchitecture:● 1 M B u nified L2 c ache●Support L2 c ache R AMs p rotection w ith E CC●Frequency o f 1.5 G HzArm C ortex-M4 c ore p latform ●16 K B L1 I nstruction C ache●16 K B L1 D ata C ache●256 K B t ightly c oupled m emory (TCM)Graphic P rocessing U nit (GPU) ●Vivante G C7000Lite● 4 s haders●267 m illion t riangles/sec●1.6 G igapixel/sec●32 G FLOPs 32-bit o r 64 G FLOPs 16-bit●Supports O penGL E S 1.1,2.0,3.0,3.1,O pen C L 1.2,a nd V ulkan Video P rocessing U nit (VPU) ●4Kp60 H EVC/H.265 m ain,a nd m ain 10 d ecoder●4Kp60 V P9 a nd 4Kp30 A VC/H.264 d ecoder (requires f ull s ystemresources)●1080p60 M PEG-2,M PEG-4p2,V C-1,V P8,R V9,A VS,M JPEG,H.263decoderI/O c onnectivity ●2x U SB 3.0/2.0 c ontrollers w ith i ntegrated P HY i nterfaces●1x U ltra S ecure D igital H ost C ontroller (uSDHC)i nterfaces●1x G igabit E thernet c ontroller w ith s upport f or E EE,E thernet A VB,and I EEE 1588●2x U ART m odules●2x I2C m odules●2x S PI m odules●16x G PIO l ines w ith i nterrupt c apability●4x P WM l ines●Input/output m ultiplexing c ontroller (IOMUXC)t o p rovide c entralizedpad c ontrolNote:T he l ist a bove i s t he n umber o f s ignals a vailable t o t he b aseboard(after c onsidering S oC s ignals u sed b y t he S oM).On-chip m emory ●Boot R OM (128 K B)●On-chip R AM (128 K B +32 K B)Display HDMI D isplay I nterface:●HDMI 2.0a s upporting o ne d isplay u p t o 1080p●Upscale a nd d ownscale b etween 4K a nd H D v ideo (requires f ullsystem r esources)●20+A udio i nterfaces 32-bit @384 k Hz f s,w ith T ime D ivisionMultiplexing (TDM)s upport●SPDIF i nput a nd o utput●Audio R eturn C hannel (ARC)o n H DMIMIPI-DSI D isplay I nterface:●MIPI-DSI 4c hannels s upporting o ne d isplay,r esolution u p t o1920 x1080 a t 60 H z●LCDIF d isplay c ontroller●Output c an b e L CDIF o utput o r D C d isplay c ontroller o utput Audio ●1x S PDIF i nput a nd o utput●2x s ynchronous a udio i nterface (SAI)m odules s upporting I2S,A C97,TDM,a nd c odec/DSP i nterfaces●1x S AI f or 8T x c hannels f or H DMI o utput a udio●1x S PDIF i nput f or H DMI A RC i nputCamera ●2x M IPI-CSI2 c amera i nputs (4-lane e ach)Security ●Resource D omain C ontroller (RDC)s upports f our d omains a nd u p t oeight r egions●Arm T rustZone (TZ)a rchitecture●On-chip R AM (OCRAM)s ecure r egion p rotection u sing O CRAMcontroller●High A ssurance B oot (HAB)●Cryptographic a cceleration a nd a ssurance (CAAM)m odule●Secure n on-volatile s torage (SNVS):S ecure r eal-time c lock (RTC)●Secure J TAG c ontroller (SJC)Edge T PU c oprocessor ●ASIC d esigned b y G oogle t hat p rovides h igh p erformance M Linferencing f or T ensorFlow L ite m odels●Uses P CIe G en2 x1 a nd I2C/GPIO t o i nterface w ith t he i MX 8M S oC● 4 t rillion o perations p er s econd (TOPS)● 2 T OPS p er w attRandom a ccess m emory (SDRAM) ●1,2,o r 4G B L PDDR4 S DRAM (4-channel,32-bit b us w idth)●1600 M Hz m aximum D DR c lock●Interfaces d irectly t o t he i MX 8M b uild-in D DR c ontrollerFlash m emory (eMMC) ●8 G B e MMC (K LMBG4GEND-B031 )f or t he 1a nd 2G B R AM m odelsor 16 G B e MMC (EMMC16G-TB29-PZ90)f or t he 4G B R AM m odel●8-bits M MC m ode●Conforms t o J EDEC v ersion 5.0 a nd 5.1Expandable flash s upport ●Meets S D/SDIO 3.0 s tandard●Runs a t 4-bits S DIO m ode●Supports s ystem b oot f rom S D c ardEthernet ●10/100/1000 M bps E thernet /IEEE 802.3 n etworks ●Reduced g igabit m edia -independent i nterface (RGMII )Wi -FiMurata L BEE5U91CQ m odule : ●Wi -Fi 2x2 M IMO (802.11a /b /g /n /ac 2.4/5 G Hz ) ●Supports P CIe h ost i nterface f or W -LAN BluetoothMurata L BEE5U91CQ m odule : ●Bluetooth 4.2 (supports B luetooth l ow -energy ) ●Supports U ART i nterfaceCryptographic c oprocessorMicrochip A TECC608A c ryptographic c oprocessor : ●Asymmetric (public /private ) k ey c ryptographic s ignature s olutionbased o n E lliptic C urve C ryptography a nd E CDSA s ignature protocolsBaseboard c onnectors 3x 100-pin c onnectors (Hirose D F40C -100DP -0.4V )1.1 B lock d iagramsFigures 1a nd 2i llustrate t he c ore c omponents o n t he S oM a nd S oC.Figure 1. B lock d iagram o f t he S oM c omponentsFigure 2.B lock d iagram o f i MX 8M S oC c omponents,p rovided b y N XP (some I/O s ignals o n t he S oC a re c onsumed o n t he SoM,s o r efer t o t able 1f or a vailability)2 M echanical d imensionsTable 2. S oM m echanical d imensionsFigure 3 i llustrates a ll o f t he S oM 's d imensions . F or a t op -down v iew o f t he b aseboard c onnector l ocations a nd c omponent height r estrictions , s ee t he B aseboard d eveloper g uide .Figure 3. S oM d imensions (in m illimeters )3 S ystem p owerThe S oM r equires 5 V a s p ower i nput (at V SYS _5V ). T he S oM t hen g enerates t he l ocal v oltage r ails f or a ll S oM c omponents through o n -board P MICs .Table 3. S oM p ower r equirementsMeasurement ValueSize 48 x 40 x 5.11 m m Weight13 gPower i nputVoltage Main p ower s upply (VSYS _5V ) 5 V ± 5%Caution: D o n ot c onnect t he 1.8/3.3 V p ower o utput p ins t o a ny h igh c urrent d evices o r y ou m ight b rownout t he s ystem . These p ower l ines a re s hared w ith i nternal S oM c ircuits , s o t here i s n o s afe l imit f or a h igh c urrent d evice , b ut y ou c an safely u se t hem f or l ow c urrent t asks s uch a s f or a l evel s hifter o r p ull -up /down . Caution: D o n ot c onnect a ny o f t he 3.3 V I /O p ins t o a d evice t hat d raws m ore t han ~82 m A o f p ower o r y ou w ill brownout t he s ystem .3.1 P ower s ignalsEven t hough t here a re m ultiple p ower s ignals d e fined i n t he b oard -to -board c onnectors , o nly t he V SYS _5V a nd g round connections a re r equired . A ll o thers a re o ptional .Table 4. P ower a nd r eset p in s ignals Note: M ake s ure t o r oute a ll t he V SYS _5V a nd G ND p ins , a nd a dd d ecoupling (bypass ) c apacitors b etween V SYS _5V and G ND n ear t he m ating c onnector p ins . Name Type Connector Pins Voltage Description VSYS _5V Power J1312 93, 94, 95, 96, 97, 98, 99, 100 5 V Main 5 V p ower i nput t o S oM .Must b e c onnected . GND Power J1312 9, 10, 65, 66, 71, 72, 77, 78, 83,84 Common g round . Must b e c onnected . GNDPowerJ13111, 2, 7, 8, 13, 14, 19, 20, 25, 26, 31, 32, 37, 38, 43, 44, 49, 50, 55, 56, 61, 62, 67, 68, 73, 74, 79, 80, 86, 89, 90, 94, 99, 100Common g round . Must b e c onnected .GND Power J1310 1, 2, 7, 25, 39, 40, 42, 44, 45, 46, 50, 51, 56, 57, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 80Common g round . Must b e c onnected .DCDC _3V3 Power J1310 84, 86, 88, 903.3 V3.3 V o utput f rom S oM . C an b e l eft floating i f n ot u sed . N ot f or high -current u sage ; c an b e u sed t o pull -up G PIO . VDD _3V3 Power J1310 94, 96, 98 100 3.3 V3.3 V o utput f rom S oM . C an b e l eft floating i f n ot u sed . N ot f or high -current u sage ; c an b e u sed t o pull -up G PIO . VDDA _1V8 Power J1310 91, 93, 95, 97, 99 1.8 V1.8 V o utput f rom S oM . C an b e l eft floating i f n ot u sed . N ot f or high -current u sage ; c an b e u sed t o pull -up G PIO . POR _B Output J1310 79 3.3 V"Power _On _Reset " s ignal f rom i MX 8M P MIC t o r eset t he S oC (active -low o pen -drain o utput ). Available t o e nable s equencing . PWRON _B Input J1312 86 3.3 V"Power _On " (active -low i nput ). Triggers a r eset o f t he i MX 8M PMIC p ower c ycle . Pull -up i n S oM . SYS _nRST Input J1312 63 3.3 VSystem r eset (active -low i nput ). Recommended f or r eset b utton o n baseboard . Pull -up i n S oM .3.2 P ower c onsumptionThe p ower c onsumption n umbers l isted i n t his s ection a re b ased o n a h igh p erformance t est t hat i ncludes t he f ollowing :●GPU : 3D r endering ●CPU : 2 o f 4 c ores 100% l oaded ●Active W i -Fi d ownload ●7" H DMI d isplay o n ●DDR : 800 M Hz ●Edge T PU r unning M obileNet V 1 a t 500 M Hz ●Fan i ntermittently o nTable 5 l ists t he p ower d raw m easurements d uring d i fferent o perational t ests b oth f or b oth t he S oM , a nd f or t he D ev B oard baseboard a nd S oM w orking t ogether .Table 5. S oM p ower d raw m easurements * T ested w ith C oral D ev B oard —performance o n y our c ustom b aseboard m ay v ary .During t he h igh p erformance t est , t he t op p ower -consuming c omponents (top h eat s ources ) a re a s i ndicated i n figure 4.Figure 4. P ower d raw a nd o rdinate l ocations (in m illimeters ) o f t op p ower c omponents d uring h igh p erformance t estCaution: Y ou m ust p rovide a c ooling s olution t o e nsure t he S oM s urface m aintains a n o perational t emperature a s speci fied i n t he E nvironmental r eliability s ection . U nlike t he C oral D ev B oard , t he s tandalone S oM d oes n ot i nclude a cooling s olution (the S oM c omponents a re c overed o nly w ith a n E MI s hield ). Operational t est SoM p ower System p ower (SoM + D ev B oard b aseboard)* Idle2.6 W 4.0 W Idle w ith H DMI d isplay o n3.0 W4.3 W High p erformance6.2 W8.5 W3.3 E dge T PU p ower c haracteristicsThe c urrent d rawn b y t he E dge T PU i s h ighly v ariable a nd d epends o n t he m odel b eing e xecuted . A lthough t he a verage current d rawn b y t he E dge T PU m ay b e l ess t han 500 m A , i t c an r epeatedly a nd r apidly s pike u p t o 3 A , d epending o n t he model y ou 're r unning . T hese s pikes a lso o ccur s uddenly : e ven a s imple m odel c an g enerate c urrent t ransients i n e xcess o f 1 A /μs , w hich c an l ast s everal t ens o f m icroseconds . The E dge T PU d issipates p ower r oughly p roportional t o i ts c omputational l oad . T he r esulting h eat i n t he E dge T PU d ie m ust be s afely a nd r eliably c onducted a way t o a void e xcessive d ie t emperatures t hat c an a ffect p erformance a nd r eliability . The E dge T PU ’s j unction t emperature T j m ust s tay b elow t he m aximum o perating s peci fication :●Maximum E dge T PU j unction t emperature T j : 115 °CFor i nformation a bout t hermal m anagement s trategies f or t he E dge T PU , s ee s ection 7.6 .Warning: E xceeding t he m aximum t emperature c an r esult i n p ermanent d amage t o t he E dge T PU a nd s urrounding components , a nd c an p ossibly c ause fire a nd s erious d amage , i njury , o r d eath .4 B oot m odeUse t he B OOT _MODE [1:0] p ins t o c on figure t he S oM b oot m ode s etting a s i ndicated i n t he f ollowing t ables .Table 6. B oot m ode p in s ignalsTable 7. B oot m ode p in s ettings The b oot c on figuration i s s peci fied b y t he i MX 8M S oC , s o f or m ore d etails , r efer t o t he i MX 8M S oC d ocumentation .5 P eripheral i nterfacesThe f ollowing i nterfaces a re a vailable f rom t he S oM , t hrough t he t hree 100-pin b oard -to -board c onnectors . This s ection i s o rganized b ased o n t he d efault p in f unctions w hen r unning t he M endel o perating s ystem . F or i nformation about a lternative p in f unctions y ou m ay e nable w ith y our o wn d evice t ree o verlay , s ee t he i MX 8M S oC d ocumentation .NameType Connector Pins Voltage DescriptionBOOT _MODE0 Input J1312 64 3.3 V SoC B OOT _MODE0 s ignal (can b e s et b yswitch o r p in -strap o n b aseboard ) BOOT _MODE1InputJ1312623.3 VSoC B OOT _MODE1 s ignal (can b e s et b y switch o r p in -strap o n b aseboard )BOOT_MODE[1:0] b its Boot t ype00 Boot f rom f uses (default b ehavior ) 01 Serial d ownloader 10 Internal b oot 11ReservedNote: I f B OOT _MODE [1:0] i s "10" (internal b oot ), t hen G PIO p ins S AI1_RX [7:0] a nd S AI1_TX [7:0] a re u sed t o e nable b oot con figuration o verrides (such a s w hether t o b oot f rom e MMC o r S D c ard ) b y l atching t hem t o t he B OOT _CFG [15:0] b its i n the S oC . F or f urther d etails , s uch a s i nformation a bout G PIO b oot o verrides a nd b oot f uses , s ee t he i MX 8M S oC documentation . Note: A ll I /O p ins h ave a 90 k p ull -down r esistor i n t he S oC t hat a re u sed b y d efault d uring b ootup , w hich y ou c an recon figure w ith a d evice t ree o verlay a fter b ootup . H owever , s ome p ins (such a s I 2C , s ome S AI , a nd s ome S D2 p ins ) also h ave p ull -up r esistors i nside t he S oM , a s n oted i n t he f ollowing t ables , w hich y ou c annot r econ figure w ith a d evice tree o verlay . Caution: D o n ot c onnect a ny o f t he 3.3 V I /O p ins t o a d evice t hat d raws m ore t han ~82 m A o f p ower o r y ou w ill brownout t he s ystem .5.1 M IPI c amera (CSI)There a re t wo c hannels f or M IPI c amera s erial i nterface (CSI -2), e ach w ith f our l anes a nd a m aximum b it r ate o f 1.5 G bps .Table 8. C SI c hannel 1 p insTable 9. C SI c hannel 2 p ins5.2 M IPI d isplay (DSI)The f our -lane M IPI d isplay s erial i nterface (DSI ) o ffers t he f ollowing f eatures :●Resolution u p t o 1920 x 1080 a t 60 H z ●LCDIF d isplay c ontroller ●Maximum b it r ate o f 1.5 G bpsTable 10. D SI p insNameType Connector Pins Voltage DescriptionMIPI _CSI1_CLK _P /N Input J1311 18/16 0.2-1.2 V MIPI C SI1 c lock (positive /negative ) MIPI _CSI1_D0_P /N Input J1311 12/100.2-1.2 VMIPI C SI1 d ata (positive /negative ) MIPI _CSI1_D1_P /N Input J1311 23/21 0.2-1.2 V MIPI C SI1 d ata (positive /negative ) MIPI _CSI1_D2_P /N Input J1311 6/40.2-1.2 VMIPI C SI1 d ata (positive /negative ) MIPI _CSI1_D3_P /N Input J131129/27 0.2-1.2 VMIPI C SI1 d ata (positive /negative )NameType Connector PinsVoltageDescriptionMIPI _CSI2_CLK _P /N Input J1311 36/34 0.2-1.2 V MIPI C SI2 c lock (positive /negative ) MIPI _CSI2_D0_P /N Input J1311 35/33 0.2-1.2 V MIPI C SI2 d ata (positive /negative ) MIPI _CSI2_D1_P /N Input J1311 30/28 0.2-1.2 V MIPI C SI2 d ata (positive /negative ) MIPI _CSI2_D2_P /N Input J1311 24/22 0.2-1.2 V MIPI C SI2 d ata (positive /negative ) MIPI _CSI2_D3_P /N Input J131141/39 0.2-1.2 VMIPI C SI2 d ata (positive /negative )NameTypeConnectorPinsVoltageDescriptionMIPI _DSI1_CLK _P /N Output J1311 59/57 0.2-1.2 V MIPI D SI c lock (positive /negative ) MIPI _DSI1_D0_P /N Output J1311 47/45 0.2-1.2 V MIPI D SI d ata (positive /negative ) MIPI _DSI1_D1_P /N Output J1311 54/52 0.2-1.2 V MIPI D SI d ata (positive /negative ) MIPI _DSI1_D2_P /N Output J1311 42/40 0.2-1.2 V MIPI D SI d ata (positive /negative ) MIPI _DSI1_D3_P /N Output J131148/46 0.2-1.2 VMIPI D SI d ata (positive /negative )5.3 H DMIThe H igh -De finition M ultimedia I nterface (HDMI ) c onnection p rovides t he f ollowing f eatures :●HDMI 2.0a s upporting o ne d isplay u p t o 1080p ●Upscale a nd d ownscale b etween 4K a nd H D v ideo (requires f ull s ystem r esources ) ●20+ A udio i nterfaces 32-bit @ 384 k Hz f s , w ith T ime D ivision M ultiplexing (TDM ) s upport ●SPDIF i nput a nd o utput ●Audio R eturn C hannel (ARC ) o n H DMITable 11. H DMI p ins5.4 E thernetThe E thernet M edia A ccess C ontroller (MAC ) s upports 10/100/1000 M bps E thernet /IEEE 802.3 n etworks w ith r educed gigabit m edia -independent i nterface (RGMII ). R equires a n E thernet P HY o n t he b aseboard .Table 12. E thernet p ins NameTypeConnector PinsVoltage Description HDMI _REFCLKP /NOutput J131058/603.3 VHDMI r eference c lock (27 M Hz ) (positive /negative ).Required f or b ootup , e ven i f y ou d on 't u se H DMI . For d etail , s ee t he r eference d esign s chematic . HDMI _CLKP /N Output J1312 68/70 3.3 V HDMI c lock (positive /negative ) HDMI _TX0_P /N Output J1312 75/73 3.3 V HDMI t ransmit (positive /negative ) HDMI _TX1_P /N Output J1312 79/81 3.3 V HDMI t ransmit (positive /negative ) HDMI _TX2_P /N Output J1312 76/74 3.3 V HDMI t ransmit (positive /negative ) HDMI _AUX _P /N Output J1312 82/80 3.3 V HDMI A UX (positive /negative ) HDMI _HPD Output J1312 89 3.3 V HDMI H ot P lug D etectHDMI _DDC _SDA Output J1312 85 3.3 V HDMI D isplay D ata C hannel d ata HDMI _DDC _SCL Output J1312 87 3.3 V HDMI D isplay D ata C hannel c lock HDMI _CEC Output J1312913.3 VHDMI C onsumer E lectronic C ontrolName Type Connector Pins Voltage Description ENET _RD0 Input J1310 33 1.8 V RGMII r eceive f rom P HY ENET _RD1 Input J1310 35 1.8 V RGMII r eceive f rom P HY ENET _RD2 Input J1310 31 1.8 V RGMII r eceive f rom P HY ENET _RD3 Input J1310 37 1.8 V RGMII r eceive f rom P HY ENET _RX _CTL Input J1310 29 1.8 V RGMII r eceive f rom P HY ENET _RXCInputJ1310271.8 VRGMII r eceive f rom P HY5.5 P CIeThe S oC i ncludes P CIE1 a nd P CIE2 l ines t hat a re r outed t o t he b aseboard c onnectors , b ut y ou s hould n ot n eed t o c onnect these a nd y ou s hould n ot r emap t hese w ith y our o wn d evice t ree b ecause b oth a re u sed o n t he S oM f or W i -Fi (PCIE1) a nd the E dge T PU (PCIE2).5.6 U SBThere a re t wo U SB c ontrollers a nd c orresponding P HYs o n t he S oM . E ach U SB i nstance c ontains U SB 3.0 (USB 3.1 G en 1) core , w hich c an o perate i n b oth U SB 3.0 a nd 2.0 m ode .Table 13. U SB c hannel 1 p insENET _TD0 Output J1310 19 1.8 V RGMII t ransmit t o P HY ENET _TD1 Output J1310 21 1.8 V RGMII t ransmit t o P HY ENET _TD2 Output J1310 17 1.8 V RGMII t ransmit t o P HY ENET _TD3 Output J1310 15 1.8 V RGMII t ransmit t o P HY ENET _TX _CTL Output J1310 13 1.8 V RGMII t ransmit t o P HY ENET _TXC Output J1310 23 1.8 V RGMII t ransmit t o P HY ENET _MDC Output J1310 11 1.8 V RGMII c lock f or P HY ENET _MDIO Output J1310 9 1.8 V RGMII M DIO d ata f or P HY ENET _nRST (GPIO1_IO09) Output J1312 43 3.3 V PHY r eset ENET _nINT (GPIO1_IO11) Input J1312 39 3.3 V PHY i nterrupt ENET _WoL (GPIO1_IO10) InputJ131241 3.3 V PHY W ake -on -LanCLKO _25M (GPIO1_IO15) Output J1310543.3 VOptional 25 M hz c lock t o P HYName Type Connector PinsVoltage DescriptionUSB1_DP /N I /OJ131151/53 3.3 V USB 2.0 (positive /negative ) USB1_TXP /N Output J1311 58/60 1.8 V USB 3.0 t ransmit (positive /negative ) USB1_RXP /N Input J1311 64/66 1.8 V USB 3.0 r eceive (positive /negative ) USB1_VBUS Input J1311 82/84 5 V VBUS d etect (same a t b oth p ins ) USB1_ID InputJ1311763.3 VUSB I DTable 14. U SB c hannel 2 p ins5.7 D igital a udio (SAI)The S AI m odule p rovides a s ynchronous a udio i nterface (SAI ) t hat s upports f ull d uplex s erial i nterfaces w ith f rame synchronization , s uch a s I 2S , A C97, T DM , a nd c odec /DSP i nterfaces .Table 15. S AI 1 s ignals Name Type Connector PinsVoltage DescriptionUSB2_DP /N I /OJ131163/65 3.3 V USB 2.0 (positive /negative ) USB2_TXP /N Output J1311 69/71 1.8 V USB 3.0 t ransmit (positive /negative ) USB2_RXP /N Input J1311 70/72 1.8 V USB 3.0 r eceive (positive /negative ) USB2_VBUS Input J1311 75/77 5 V VBUS d etect (same a t b oth p ins ) USB2_ID InputJ1311883.3 VUSB I DNote: I f b ooting t he S oM i n e FUSE m ode (default b ehavior ), a ll S AI p ins a re a vailable d uring b oot . H owever , w hen u sing the o ther b oot m odes , p ins S AI1_RX [7:0] a nd S AI1_TX [7:0] a re u sed t o e nable b oot c on figuration o verrides b y l atching them t o t he B OOT _CFG [15:0] b its i n t he S oC —that i s , o nly u ntil b oot c ompletes . T he S oM u ses i nternal p in s trap (pull -up and p ull -down ) r esistors t o s elect t he d i fferent b oot c on figuration , s o y ou s hould b e c areful i f y ou a dd a ny p ull -up /down resistors f or t hese p ins o n y our b aseboard . F or d etails , s ee t he i MX 8M S oC d ocumentation . Name Type Connector Pins Voltage Description SAI1_MCLK I /O J1312 26 3.3 V Audio m aster c lock SAI1_RXC Input J1312 17 3.3 V Receive b it c lock SAI1_RXFS Input J1312 19 3.3 V Receive f rame s yncSAI1_RXD0InputJ1312333.3 VReceive c hannel .Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD1 Input J1312 35 3.3 VReceive c hannel . Pull -up i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD2 Input J1312 27 3.3 VReceive c hannel . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD3 Input J1312 31 3.3 VReceive c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD4 Input J1312 29 3.3 VReceive c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above .SAI1_RXD5InputJ1312213.3 VReceive c hannel .Pull -up i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD6 Input J1312 25 3.3 VReceive c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_RXD7 Input J1312 23 3.3 VReceive c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXC Output J1312 40 3.3 V Transmit b it c lock . SAI1_TXFS Output J1312 46 3.3 V Transmit f rame s ync .SAI1_TXD0Output J1312443.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD1 Output J1312 42 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD2 Output J1312 30 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD3 Output J1312 36 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD4 Output J1312 38 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD5 Output J1312 34 3.3 VTransmit c hannel . Pull -up i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD6 Output J1312 28 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above . SAI1_TXD7 Output J1312 32 3.3 VTransmit c hannel . Pull -down i n S oM : 10k O hm . Reserved d uring b oot , e xcept i n e FUSE m ode . S ee n ote above .Table 16. S AI 2 s ignals5.8 S ony/Philips a udio (SPDIF)Sony /Philips D igital I nterface (SPDIF ) i s a s tandard a udio file t ransfer f ormat t hat s upports T ransmitter a nd R eceiver functionality . R efer t o N XP i MX 8M d ocumentation f or a dditional d etails .Table 17. S PDIF p in s ignalsName TypeConnectorPins Voltage Description SAI2_TXD Output J1312 14 3.3 V Transmit c hannel SAI2_RXD InputJ131220 3.3 V Receive c hannel SAI2_TXC Output J1312 18 3.3 V Transmit b it c lock SAI2_TXFS Output J1312 16 3.3 V Transmit f rame s ync SAI2_MCLK I /O J1312 12 3.3 V Audio m aster c lock SAI2_RXFS Input J1312 24 3.3 V Receive f rame s ync SAI2_RXC InputJ1312233.3 VReceive b it c lockNote: T he S oC i ncludes S AI3 l ines , b ut m ost o f t hese a re u sed b y t he S oM f or W i -Fi , s o y ou s hould n ot r emap t hese w ith your d evice t ree . O nly S AI3_RXC a nd S AI3_RXFS a re p rovided b y t he S oM b aseboard c onnectors a nd a vailable f or u se as G PIO . The S oC a lso i ncludes S AI5 l ines t hat a re a ll p rovided b y t he S oM c onnectors , b ut t hree o f t hem a re p in -strapped i nside the S oM (SAI5_RXD1, S AI5_RXD3, a nd S AI5_RXFS ), a nd t heir l evel i s l atched b y t he U -Boot b ootloader t o d etermine t he SoM S KU (LPDDR4 m emory s ize ). W e r ecommend t hat y ou d o n ot u se t hese t hree p ins f or a ny o ther p urpose a nd d o not c onnect t hem. T he r emaining S AI5 p ins (SAI5_MCLK , S AI5_RXC , S AI5_RXD0, a nd S AI5_RXD2) a re a vailable f or u se as G PIO . NameTypeConnectorPins Voltage Description SPDIF _EXT _CLK Output J1311 92 3.3 V External c lock s ignal SPDIF _TX Output J1311 96 3.3 V Transmit d ata c hannel SPDIF _RX InputJ1311983.3 VReceive d ata c hannel。

IAC-IMX8MM-Kit 功能说明与测试手册版本号：V2.02021年04月浙江启扬智能科技有限公司版权所有QIYANG TECHNOLOGY Co., LtdCopyright Reserved版本更新记录有任何技术问题或需要帮助，请联系：*********************** 第3页 共41页 购买产品，请联系销售：********************更多信息请访问： 目 录目 录 ............................................................................................................................................. 3 阅读前须知：本手册主要介绍接口功能测试 ............................................................................... 4 一、前言 . (4)公司简介 ................................................................................................................................... 4 一、准备工作 ................................................................................................................................... 5 二、主板测试 ................................................................................................................................... 6 2.1、蜂鸣器测试 ...................................................................................................................... 6 2.2、时钟测试 .......................................................................................................................... 7 2.3、看门狗测试 ...................................................................................................................... 9 2.4、CAN 测试 ...................................................................................................................... 10 2.5、GPIO 测试 ..................................................................................................................... 12 2.6、显示测试 (15)2.6.1 hdmi 显示 (15)2.6.2 mipi-dsi 显示 .......................................................................................................... 16 2.6.3 lvds 显示 ................................................................................................................ 18 2.7、触摸测试 ........................................................................................................................ 19 2.8、USB 测试 ....................................................................................................................... 20 2.9、WIFI 测试 ...................................................................................................................... 22 2.10、蓝牙测试 ...................................................................................................................... 24 2.11、4G 测试 ........................................................................................................................ 28 2.12、串口测试 ...................................................................................................................... 30 2.13、摄像头测试 .................................................................................................................. 33 2.14、音频测试 ...................................................................................................................... 34 2.15、SD 卡测试 .................................................................................................................... 35 2.16、网口测试 ...................................................................................................................... 36 2.17、屏背光测试 .................................................................................................................. 39 三、测试小结 (40)有任何技术问题或需要帮助，请联系：*********************** 第4页 共41页 购买产品，请联系销售：********************更多信息请访问： 阅读前须知：本手册主要介绍接口功能测试一、前言公司简介浙江启扬智能科技有限公司2007年成立于杭州， 是一家专注于ARM 嵌入式产品研发、生产与销售的国家高新技术企业。

恩智浦半导体数据手册：技术数据文件编号：IMXBMMCEC第0.2版，2019年4月MIMX8MM6DVTLZAAMIMX8MM4DVTLZAAMIMX8MM2DVTLZAAMIMX8MM5DVTLZAAMIMX8MM3DVTLZAAMIMX8MM1DVTLZAA适用于消费电子产品的i.MX 8M Mini应用处理器数据手册封装信息塑料封装FCBGA 14 x 14 mm，0.5 mm间距订购信息参见第6页的表21 i.MX 8M Mini简介i.MX 8M Mini应用处理器是能够带来最新视频和音频体验的恩智浦产品，具有最先进的特定媒体功能，采用高性能处理技术，同时优化了功耗。

i.MX 8M Mini系列处理器采用先进的四核Arm® Cortex®-A53内核，运行速度高达1.8 GHz。

一个通用型Cortex®-M4 400 MHz内核处理器用于低功耗处理。

DRAM控制器支持32位/16位LPDDR4、DDR4和DDR3L存储器。

可提供多种音频接口，包括I2S、AC97、TDM和S/PDIF。

提供许多其他接口用于连接外围设备，如USB、PCIe和以太网。

1. i.MX 8M Mini简介 (1)1.1. 功能框图 (5)1.2. 订购信息 (6)2. 模块列表 (8)2.1. 未使用的输入/输出的推荐连接 (12)i.MX 8M Mini简介表1. 特性i.MX 8M Mini简介表1. 特性（续）i.MX 8M Mini简介表1. 特性（续）注意实际功能集取决于产品型号（如表2所述）。

某些特定产品型号可能并未启用某些功能，如显示器和摄像头接口以及连接接口。

i.MX 8M Mini简介1.1 功能框图图1显示了i.MX 8M Mini应用处理器系统的功能模块。

图1. i.MX 8M Mini系统功能框图i.MX 8M Mini简介1.2 订购信息表2所示为本数据手册中包含的可订购样品型号的示例。

图书基本信息书名：《飞思卡尔8位单片机实用教程》13位ISBN编号：978712108999210位ISBN编号：7121089998出版时间：2009-6出版社：曾周末、李刚、陈世利、 周鑫玲 电子工业出版社 (2009-06出版)页数：222版权说明：本站所提供下载的PDF图书仅提供预览和简介以及在线试读，请支持正版图书。

更多资源请访问：前言飞思卡尔原是全球领先的半导体公司，为汽车、消费电子、工业控制、网络和无线市场设计并制造嵌入式半导体产品。

飞思卡尔系列单片机由于其低成本和高性能的特点越来越受到用户的青睐。

本书介绍的MC9S08QG8单片机采用高性能、低功耗HCS208飞思卡尔8位微控制器为内核，是一款集成度很高、功能丰富、适用于各种应用的低价位单片机。

本书将给大家介绍它的一些主要功能及特性，包括灵活多样的低功耗模式、3.3V电压下的Flash编程、片内调试仿真器、高速ADC、IC总线、片内比较器等。

本书共12章，深入浅出地从一般单片机的基础知识人手，引出飞思卡尔8位单片机基础知识、最小系统设计，进而有步骤地、详略得当地介绍飞思卡尔8位单片机的寄存器与片内存储器、指令系统与汇编程序设计、中断系统等基本功能，并在之后的章节中，详细而又有针对性地一一介绍了集成在这款单片机内部的其他功能模块，比如定时器和比较器、异步串行通信、SPI、IC、模／数转换等功能模块。

本书还介绍了飞思卡尔单片机与MCS51单片机的区别，学过5l单片机的人会很快掌握其要点。

在本书最后一章里，有针对性地介绍了S08系列单片机c语言编程，并详细介绍了Code Warrior IDE调试软件的使用方法。

本书给出的所有例题都在实验板上运行验证过。

总之，本书力求通过最简洁的语言和表述方式、最通俗易懂的应用举例，向广大读者全面地介绍MC9S080G8单片机的功能及特性，以求能够为大专院校的学生及各相关领域的工作者提供一些帮助。

参加本书编写的还有天津大学精仪学院的薛彬、汤其剑、刘世廷、高雅彪、叶德超、黄邦奎、孙晔等研究生。

© 2018 NXP B.V.i.MX 8M EVK Board Hardware User's Guide1.IntroductionThis document is the hardware User’s Guide for the i.MX 8M Evaluation Kit (EVK) based on the NXP Semiconductor’s i.MX 8MDQLQ Applications Processor. This board is fully supported by NXPSemiconductor. This manual includes system setup and debugging, and provides detailed information on the overall design and usage of the EVK board from a hardware system perspective.1.1. Board overviewThe EVK board is a platform designed to showcase themost commonly used features of the i.MX 8MDQLQ Applications Processor in a small, low cost package. The i.MX 8M EVK board is an entry level development board, which gives the developer the option ofbecoming familiar with the processor before investing a large amount of resources in more specific designs. Table 1 lists the features of the i.MX 8M EVK board.NXP Semiconductors Document Number: IMX8MDQLQEVKHUGUser's GuideRev. 0, 01/2018Contents1.Introduction ........................................................................ 11.1. Board overview ....................................................... 1 1.2. Board contents ........................................................ 2 1.3. Board revision history ............................................. 2 2.Specifications ..................................................................... 32.1. Processor ................................................................. 4 2.2. Boot mode operations and selections ...................... 4 2.3. Power tree ............................................................... 6 2.4. LPDDR4 DRAM memory ...................................... 8 2.5. SD card slot (J1601) ............................................... 8 2.6. eMMC memory (U601) .......................................... 9 2.7. Ethernet connector (J1201) ..................................... 9 2.8. USB connector (J901, J903) ................................... 9 2.9. Audio input/output (J1101) ..................................... 9 2.10. UART connector (J1701) ........................................ 9 2.11. JTAG connector (J401) ......................................... 10 2.12. Extension port (J1801) .......................................... 10 2.13. MIPI-CSI/MIPI-DSI connector (J1501, J1502, J1503) 102.14. User interface buttons ........................................... 11 2.15. WiFi/BT (U1301/J1401) ....................................... 12 2.16. User interface LED indicators ............................... 12 2.17. HDMI connector (J1001) ...................................... 12 3.PCB information .............................................................. 13 3.1. EVK design files (13)IntroductionTable 1. Board featuresProcessor NXP Applications Processor MIMX8MQ6DVAJZAADRAM memory Micron 3 GB LPDDR4 MT53B768M32D4NQ-062 WT:B Mass storage Micron 16 GB eMMC5.0 MTFC16GAKAECN-2M WTMicron 32 MB QSPI NOR MT25QL256ABA1EW9MicroSD card connector SD3.0 supportedPower NXP PMIC PF4210 + Discrete DCDC/LDODisplay interface HDMI 2.0a ConnectorDSI interface (Mini-SAS connector)Ethernet 1 GB Ethernet with RJ45 connectorUSB x1 USB (2.0/3.0) Type-C connector x1 USB (2.0/3.0) host connectorAudio connectors 3.5 mm Stereo Headphone outputDebug connectors JTAG (10-PIN header) MicroUSB for UART debugCamera CSI interface (Mini-SAS connector)WiFi/Bluetooth x1 on board WiFi/BT module x1 M.2 slot (KEY-E type)Buttons ONOFF, RESETLED Indicators Power status, UARTExpansion Port FPC connector (SAI ports)PCB 3.937-inch x 3.937-inch (10 cm x 10 cm), 10-layer board1.2. Board contentsThe i.MX 8M EVK contains the following items:•i.MX 8M EVK board•USB Cable (x1 Standard USB TYPE-A to MicroUSB TYPE-B connector; x1 Standard USB TYPE-A to USB TYPE-C connector)•12V/5.0A Power Supply•Quick Start Guide1.3. Board revision history•Rev A0/A1•Rev B1/B2•Rev B3The board assembly version will be printed on a label, usually attached to the bottom side. The assembly version will be the letter designation following the schematic revision: 700-29615 REV _.2. SpecificationsThis section provides the detailed information about the electrical design and practical considerations that go into the EVK board. Figure 1 describes each block in the high-level block diagram of the EVK board.Figure 1. MCIMX8M-EVK block diagramFigure 2 shows the overview of the i.MX 8M EVK board.SpecificationsFigure 2. i.MX 8M EVK board overview2.1. ProcessorThe i.MX 8MDQLQ processors represent NXP Semiconductor’s latest achievement in integrated multimedia-focused products offering high performance processing with a high degree of functional integration, targeted towards the growing market of connected devices. The i.MX 8MDQLQ processor features NXP’s advanced implementation of the Quad ARM Cortex®-A53+ ARM Cortex®-M4 core, which operates at speeds up to 1.5 GHz. i.MX 8MDQLQ includes integrated power management module that reduces the complexity of external power supply and simplifies the power sequencing. Each processor provides a 32-bit DDR3/LVDDR3/DDR4/LPDDR4 memory interface and other interfaces for connecting peripherals, such as HDMI, LCD, WLAN, Bluetooth™, GPS and camera sensors.For more detailed information about the processor, please refer to the datasheet and reference manual on /i.MX8M.2.2. Boot mode operations and selectionsThe i.MX 8MDQLQ Applications Processor can be the boot configuration selected on SW802 or by the boot configuration stored on internal eFUSE. Alternatively, the i.MX 8MDQLQ can download a program image from a USB connection when configured in serial downloader mode. The method used to determine where the processor finds its boot information is from two dedicated BOOT MODE pins. Table 2 shows the values used in the two methods.Figure 3. Boot modeTable 2. Boot mode pin settingsBOOT_MODE1 BOOT_MODE 0 Boot source0 0 Boot from fuses0 1 Serial downloader1 0 Internal boot1 1 ReservedIt is important for the developer to remember that these two pins are tied to the BOOT modules, therefore, on i.MX 8M EVK board, use a dual-switch (SW802) to select the input voltage of these two pins, 0 or 3.3 V. If the developer wants to boot the program Image from the Fuses Mode, the position of the switch 1 and 2 must be set to OFF, it is the same principle to choose the Serial Downloader Module or Internal Boot Module to load bootable code into the processor.If the method of determining the bootable source code is selected to be from the hardware, then the developer must set the switch S802:MODE0 to OFF, MODE1 to ON, and the four i.MX 8MDQLQ pins must be set on the EVK board as Table 3 and Figure 4.Table 3. Boot mode settingBOOT configuration SW801Boot from EMMC 0010Boot from SD2 1100SpecificationsFigure 4. Boot mode settingOn the i.MX 8M EVK board, the default boot mode is from eMMC device. There is one SD connector on the board. The board will check the eMMC connector first and then the SD connector. If you put the boot card into SD connector, and set the boot configuration as “BOOT from SD2”, the board will boot from the SD by default.NOTEFor more information about the boot module, such as the meaning ofevery bit of the Boot Switch, please refer to i.MX 8MDQLQ ReferenceManual on /i.MX8M.2.3. Power treeThere is a +12 V external wall power supply that needs to be connected to the i.MX 8M EVK board at connector J902. The other powers from internal adapters, on the EVK board, use discrete device to power the system. Figure 5 shows the power tree.Figure 5. Power tree diagramIn Figure 5, the developer can get all the voltage supply rails used on the EVK board. When some modules are not working, the developer needs to test whether the voltage of this module is correct. Table 4 lists the power rails on the board.SpecificationsTable 4. Power railsmScale850SRC TYPE Value SEQ PWR rail1 NVCC_SNVS 3.32 VDD_SNVS 0.9RTC_RESET_B3 VDD_SOC/VDDA_0P9 DC/DC BUCK 0.94 VDD_ARM DC/DC BUCK 0.9/1.04 VDD_GPU PMIC PF4210 0.9/1.04 VDD_VPU PMIC PF4210 0.9/1.04 VDD_DRAM PMIC PF4210 1.05 VDDA_1P8_xxx PMIC PF4210 1.85 VDDA_DRAM PMIC PF4210 1.86 NVCC_3V3 DC/DC BUCK 3.36 NVCC_1V8 PMIC PF4210 1.86 NVCC_DRAM PMIC PF4210 1.1/1.2/1.357 NVCC_SD2 LDO 1.8/3.38 1.8V PHY PMIC PF4210 1.88 0.9V PHY PMIC PF4210 0.98 3.3V PHY PMIC PF4210 3.3POR_BNOTEIf an alternate power supply is used (not the original power supply), itshould be no more than 20 V; otherwise the board will not work.2.4. LPDDR4 DRAM memoryThe i.MX 8M EVK board has one 768 Meg × 32 (4 channels × 16 I/O) LPDDR4 SDRAM chip (MT53B768M32D4NQ-062 WT:B) for a total of 3 GB RAM memory.In the physical layout, the LPDDR4 chip is placed on the TOP side, the data traces are not necessarily connected to the LPDDR4 chips in sequential order, but for ease of routing, are connected as best determined by the layout and other critical traces.The DRAM_VREF can be created by a simple voltage divider using 1.5 K Ohm 1% resistors and 0.1uF capacitors for stability. The relatively smaller-value resistors provide enough current to maintain a steady mid‐point voltage. The calibration resistors used by the LPDDR4 chips and processor are 240 Ohm 1% resistors.2.5. SD card slot (J1601)There is one MicroSD card connectors (J1601) on the i.MX 8M EVK board. J1601 on the i.MX 8M EVK board is the TF slot for SD2 interface. By default, this MicroSD connector supports one 4-bitSD3.0 card or MMC card.2.6. eMMC memory (U601)The eMMC interface is connected to uSDHC1 of i.MX 8M. It can support eMMC 5.0, eMMC and hinge type. MicroSD socket are co-layout, and the eMMC device is populated by default on the EVK board. To boot from eMMC, you need to change the Boot-mode switch (SW801) settings as shown in Table 3.2.7. Ethernet connector (J1201)There is one gigabit Ethernet module on the i.MX 8MDQLQ processor. The developer can use the ENET connector to send/receive the ENET signals. The Ethernet subsystem of the i.MX 8M EVK board is provided by the Qualcomm AR8031 Ethernet Transceiver (U1201). The Ethernet Transceiver (or PHY) receives standard RGMII Ethernet signals from the MAC-NET core of the i.MX 8MDQLQ Applications Processor. The processor takes care of all Ethernet protocols at the MAC layer and above. The PHY is only responsible for the Link Layer formatting. The PHY receives the clock signal from the ENET_TXC pin of i.MX 8MDQLQ processor.When the developer uses the i.MX 8M EVK board for the first time, he must set the MAC address for the EVK board. The MAC address is printed on the connector very clearly, and the developer just needs to set MAC address same as it.2.8. USB connector (J901, J903)The i.MX 8MDQLQ Applications Processors contain two USB 2.0/3.0 OTG controllers, with two integrated USB PHY. On the EVK board, one is used for USB host port and the other for the USB TYPE-C port.2.9. Audio input/output (J1101)The main Audio DAC used on the EVK board is CIRRUS LOGIC Low Power, high quality Stereo DAC, WM8524. The digital interface between i.MX 8MDQLQ and WM8524 includes three signals: SYNC_CLK, BCLK, and DACDAT. The i.MX 8MDQLQ also provides the MCLK to WM8960.i.MX 8M EVK includes one headphone interface (J1101). J1101 is a 3.5 mm 4-pole (or TRRS) phone jack.2.10. UART connector (J1701)The i.MX 8MDQLQ Applications Processor has four independent UART Ports (UART1 – UART4). Usually the developer can use a DB9 connector and a level shifter such as MAX3232 to complete the UART debug circuit. Nowadays, many computers may not have a RS-232 DB9 connector, so on the EVK board, SILICON LABS’s CP2105, there is a USB to Serial UART IC to cover the UART signal to the USB signal.SpecificationsOn the EVK board, UART1_TXD & UART1_RXD are used to output serial debugging information for A53-core. UART2_TXD & UART2_RXD are used to output serial debugging information for M4-core. No RTS or CTS signals are sent from the Processor to the Debug connector as these signals are ignored by most applications. The required terminal settings to receive debug information during the boot cycle are as shown in Table 5.Table 5. Terminal setting parametersData Rate 115,200 BaudData bits 8Parity NoneStop bits 12.11. JTAG connector (J401)The i.MX 8MDQLQ Applications Processor accepts five JATG signals from an attached debugging device on dedicated pins. A sixth pin on the processor accepts a board HW configuration input, specific to the EVK board only. The five JTAG signals used by the processor are:•JTAG_TCK TAP Clock•JTAG_TMS TAP Machine State•JTAG_TDI TAP Data In•JTAG_TDO TAP Data Out•JTAG_nTRST TAP Reset Request (Active Low)2.12. Extension port (J1801)One Expansion port (J1801) is provided on the EVK board to generate audio card connector, and the developer can use the processor to perform audio features development.2.13. MIPI-CSI/MIPI-DSI connector (J1501, J1502, J1503)The i.MX 8MDQLQ processor supports dual MIPI-CSI and single MIPI-DSI. The connectors are designed to support camera and LCD. The connectors are as shown in Figure 6.Figure 6. MIPI-DSI/CSI connector2.14. User interface buttonsThere are two user interface buttons on the EVK board.2.14.1. Power button (SW1701)The chip supports the use of a button input signal to request main SoC power state changes (i.e. ON or OFF) from the PMU.ON/OFF can be configured as debounce, OFF-to-ON time, and max timeout. The debounce and OFF-to-ON time can be configured as 0, 50, 100 and 500 ms. Debounce is used to generate the power-off interrupt. In the ON state, if ON/OFF button is held longer than the debounce time, the power-off interrupt is generated. OFF-to-ON time supports the time it takes to request power-on after a button has been held longer than the configured time. In the OFF state, if ON/OFF button is held longer than the OFF-to-ON time, the state will transit from OFF to ON. Max timeout can be configured as 5 s, 10 s, 15 s and disable. Max timeout can also be the time for requesting power down after ON/OFF button has been held for the defined time.PCB information2.14.2. Reset button (SW1702)In the ON state, holding the RESET button (SW1702) will force to reset the power rails except the VDD_SNVS on the i.MX 8M EVK board. The i.MX 8MDQLQ applications processor will be immediately turned off and reinitiate a boot cycle from the OFF state.2.15. WiFi/BT (U1301/J1401)The MCIMX8M EVK board has two ways to support WiFi/BT function:1.Chip on board WiFi: LBEE5U91CQ-TEMP;2.M.2 WiFi/BT card.Both ways share the same UART interface for BT function, so the BT function cannot be used at the same time. For WiFi, there are two standalone PCIe interfaces for this purpose, and WiFi function can be used at the same time.2.16. User interface LED indicatorsThere are two LED indicators on the board. These LEDs have the following functions: •Main Power Supply (D1601)—Green – CPU is running on OD mode.—Red – WALL_12V_DC_JACK is provided and SW701 is powered on.—OFF – The board is powered off.•UART (D1702/D1703)—Green light flashing – The UART data transmitted to PC.—Orange light flashing – The UART data received from PC.2.17. HDMI connector (J1001)The i.MX 8M EVK board has a Type-A HDMI connector that can playback 4K video.3. PCB informationThe overall dimensions of the i.MX 8M EVK board PCB are shown in Figure 3. The EVK board is made with standard 10-layer technology. The material used was FR-4, and the PCB stack-up information is shown in Table 6.Table 6. Board stack up informationLayer Description Coppoer (Oz.) Dielectric thickness (mil)1 Signal 0.333Dielectric TU768P:2.741mil2 GND 1Dielectric TU768P:3.94mil3 Power 1Dielectric TU768P:4.409mil4 Signal 1Dielectric TU768P:3.94mil5 GND 1 3.0Dielectric TU768P:4.491mil6 Signal 1Dielectric TU768P:3.94mil7 GND 1Dielectric TU768P:4.465mil8 Signal 1Dielectric TU768P:3.94mil9 GND 1Dielectric TU768P:2.743mil10 Signal 0.3333.1. EVK design filesYou can download the schematics, layout file, gerber files, and BOM from /i.MX8M.NOTEThe CPU dies when the temperature is over 95°C due to some use cases. Itis strongly recommended to install fans on the heatsink to avoid anypotential damages to the PCBA. You can get fans from/i.MX8M.Document Number: IMX8MDQLQEVKHUGRev. 0 1/2018How to Reach Us: Home Page: / Web Support:/supportInformation in this document is provided solely to enable system and softwareimplementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical”parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /SalesTermsandConditions .NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo are the trademarks of NXP B.V. All other product or service names are the property of their respective owners.Arm, the Arm logo, and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2018 NXP B.V.。

恩智浦半导体数据手册：技术数据文件编号：IMX8MDQLQIEC 第1版，2018年10月恩智浦保留根据需要更改生产规格细节的权利，以改进其产品设计。

MIMX8MQ7CVAHZAAMIMX8MQ6CVAHZAAMIMX8MD7CVAHZAAMIMX8MD6CVAHZAAMIMX8MQ5CVAHZAAMIMX8MQ7CVAHZABMIMX8MQ6CVAHZABMIMX8MD7CVAHZABMIMX8MD6CVAHZABMIMX8MQ5CVAHZAB面向工业产品的i.MX 8MDual / 8M QuadLite / 8MQuad应用处理器数据手册封装信息塑料封装FBGA 17 x 17 mm，0.65 mm间距订购信息参见第6页的表21 i.MX 8M Dual / 8M QuadLite /8MQuad简介i.MX 8M Dual / 8M QuadLite / 8M Quad处理器是恩智浦面向联网音频流/视频流设备、接缝/成像设备以及要求高性能、低功耗处理器的各种设备市场推出的最新产品。

i.MX 8M Dual / 8M QuadLite/8M Quad处理器采用先进的四核Arm® Cortex®-A53内核，运行速度高达1.3 GHz。

通用Cortex®-M4内核处理器用于低功耗处理。

DRAM控制器支持32位/16位LPDDR4、DDR4和DDR3L存储器。

还有许多其他接口可用于连接各种外围设备，如WLAN、蓝牙、GPS、显示器和摄像头传感器等。

i.MX 8M Quad和i.MX 8M Dual处理器具有硬件加速功能，可实现高达4K的视频播放，并可驱动高达60 fps的视频输出。

虽然i.MX 8M QuadLite处理器并未搭载用于视频解码的硬件加速功能，但允许在需要之时使用软件解码器进行视频播放。

1. i.MX 8M Dual / 8M QuadLite /8M Quad简介 (1)1.1. 功能框图 (5)1.2. 订购信息 (6)i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性面向工业产品的i.MX 8M Dual / 8M QuadLite / 8M Quad应用处理器数据手册，第1版，2018年10月i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性（续）面向工业产品的i.MX 8M Dual / 8M QuadLite / 8M Quad应用处理器数据手册，第1版，2018年10月i.MX 8M Dual / 8M QuadLite /8M Quad简介表1. 特性（续）注意实际功能集取决于产品型号(如表2所述)。

atmega8原理及应用手册ATmega8是一款8位微控制器，由Atmel公司生产。

它是AVR系列微控制器的一部分，具有高性能、低功耗和易于编程的特点。

下面是关于ATmega8原理及应用手册的详细介绍：1. ATmega8原理：ATmega8采用了基于Harvard架构的8位RISC（精简指令集计算机）架构。

它具有32KB的闪存程序存储器，1KB的EEPROM数据存储器和2KB的SRAM数据存储器。

它还具有23个可编程I/O引脚，包括8个模拟输入引脚和15个数字I/O引脚。

ATmega8还支持多种通信接口，如UART（串行通信）、SPI（串行外设接口）和I2C（双向串行总线）。

2. ATmega8应用手册：ATmega8应用手册提供了关于ATmega8微控制器的详细信息，包括芯片的功能、引脚配置、时钟设置、编程和调试方法等。

手册通常包括以下内容：- 芯片功能：介绍ATmega8的主要功能和特性，如时钟源选择、中断控制、定时器/计数器、PWM（脉宽调制）等。

- 引脚配置：列出了每个引脚的功能和用途，包括I/O引脚、复位引脚、电源引脚等。

- 时钟设置：描述了如何配置和使用ATmega8的时钟源，包括外部晶体振荡器、内部RC振荡器和外部时钟输入。

- 编程方法：介绍了如何使用编程器和开发环境（如AVR Studio）对ATmega8进行程序编写、下载和调试。

- 调试方法：提供了一些调试技巧和方法，以帮助开发人员解决在ATmega8上开发过程中可能遇到的问题。

此外，ATmega8应用手册还可能包括电气特性、时序图、寄存器描述、指令集、示例电路和代码等内容，以帮助开发人员更好地理解和应用ATmega8微控制器。

总之，ATmega8原理及应用手册提供了关于ATmega8微控制器的详尽信息，帮助开发人员了解其功能和特性，并指导他们在实际应用中正确地配置和使用ATmega8。

i.MX8QuadMax定义顶级车载信息娱乐新体验继电器ART公司以制造信息娱乐系统而闻名，服务于世界上最具创新精神的知名汽车公司，他们正在采用恩智浦业界领先的i.MX 8QuadMax 应用处理器，设计用于信息娱乐系统的ARTIST 8开发平台。

该信息娱乐系统提供包括智能手机集成在内的车载娱乐功能，操作简单且安全。

乘员可以随意控制多媒体，获取离线互联内容，管理汽车舒适功能。

支持ARTIST 8信息娱乐系统的i.MX 8QuadMax预计将纳入2021年汽车生产计划。

ART首席执行官Francesco Ortix表示：“多年以来，ART灵活运用恩智浦i.MX应用处理器产品组合，不断完善自己的信息娱乐系统，很高兴看到i.MX 8QuadMax处理器能够采用单个处理器支持多个汽车领域，不但减轻了车重，有助于符合燃油效率标准，而且将无缝信息娱乐功能带入人们的生活。

早在发现i.MX 8QuadMax的潜力之初，我们就一直使用恩智浦芯片，力求在互联汽车市场开辟创新之路。

我们是一家高度技术化的公司，恩智浦i.MX 8QuadMax与我们的信息娱乐系统愿景完美互补。

”i.MX 8QuadMax具有安全域分区功能，通过四块呈现独立内容的高清屏幕或4K屏幕提供多显示屏汽车应用，帮助聪明的驾驶员优化信息娱乐体验。

凭借独特的硬件分区架构和功能，可以在没有管理程序的情况下运行多个操作系统，确保其他eCockpit子系统(包括安全关键型显示器)正常运行。

此外，最新的i.MX 8处理器集成了高级安全技术和标准，包括加密引导、椭圆曲线加密和安全密钥存储，并且支持AES、SHE及其他汽车安全标准——全部整合到单个AEC-Q100 3级认证设备中。

i.MX 8QuadMax集成了两个Arm Cortex-A72内核、四个Cortex-A53内核、两个Cortex-M4F内核和两个GC7000XS/VX GPU，包括HiFi 4 DSP，支持LPDDR4内存和带音视频桥接(AVB)功能的双Gb以太网。