附件7：华南理工大学广州学院
本科生毕业设计（论文）翻译
英文原文名Analog and Digital
中文译名模拟电子和数字电子
学院电子信息工程
专业班级09电信2班
学生姓名许龙铭
学生学号200930062417
指导教师缪文南
填表日期2013.4.25
二〇一三年四月
英文原文版出处：第四届无线通信，网络和移动计算国际会议
译文成绩：指导教师（导师组）签名：
译文：
模拟电子和数字电子
理想运算放大器和实际限制
为了讨论运算放大器的理想参数，我们必须首先定义一些指标项，然后对这些指标项讲述我们所认为的理想值。第一眼看运算放大器的性能指标表，感觉好像列出了大量的数值，有些是陌生的单位，有些是相关的，经常使那些对运放不熟悉的人感到迷惑。对于这种情况我们的方法是花上必要的时间有系统的按照列出的次序阅读并理解每一个定义。如果没有对每一项性能指标有一个真正的评价，设计人员必将失败。目标是能够依据公布的数据设计电路，并确认构建的样机将具有预计的功能。对于线性电路而言，它们与现在的复杂逻辑电路结构相比看起来较为简单，（因而在设计中）太容易忽视具体的性能参数了，而这些参数可极大地削弱预期性能。
现在让我们来看一个简单但很引人注意的例子。考虑对于一个在50kHz频率上电压增益为10的放大器驱动10k 负载时的要求。选择一个普通的带有内部频率补偿的低价运放，它在闭环增益为10时具有所要求的带宽，并且看起来满足了价格要求。器件连接后，发现有正确地增益。但是它只能产生几伏的电压变化范围，然而数据却清楚地显示输出应该能驱动达到电源电压范围以内2到3伏。设计人员忽视了最大输出电压变化范围是受频率严格限制的，而且最大低频输出变化范围大约在10 kHz受到限制。当然，事实上这个信息也在数据表上，但是它的实用性并没有受到重视。这种问题经常发生在那些缺乏经验的设计人员身上。所以这个例子的寓意十分明显：在开始设计之前总要花上必要的时间来描写全部的工作要求。关注性能指标的详情总是有益的。建议下面列出的具体的性能指标应该考虑：
1. 在温度，时间和供给电压下的闭环增益的精确性和稳定性
2. 电源要求，电源和负载阻抗，功率消耗
3. 输入误差电压和偏置电流，输入输出电阻，随着时间和温度的漂移
4. 频率响应，相位偏移，输出变化范围，瞬态响应，电压转换速率，频率稳定性，
电容性负载驱动，过载恢复
5. 线性，失真和噪声
6. 输入，输出或电源保护要求，输入电压范围，共模抑制
7. 外部补偿调整要求
不是所有的指标项都是有关的，但要记住最初就考虑它们会更好，而不要被迫返工。所有参数可以大范围变化
不要忽略这样一个事实。有多少次是在用典型值设计好电路后发现（该电路）只是因为使用的器件不典型而不能工作？这就提出一个棘手的问题：在设计中何时应该使用典型值，何时应该使用最不利值？这是经验丰富的设计人员也必须进行的判断。显然，如果某些性能要求是强制性的，则一定要用最不利情况下的数值。然而在许多情况下某一规定性能是否可以取得将在易实现性，重要性，经济性之间取得折中。
不超指标设计或超安全标准设计
最后，我们将受制于价格因素，因为杀鸡用牛刀实在是没有意义的。简单极为重要，因为用较少元器件实现（的电路）总是更便宜也更可靠。
作为最不利情况设计的例子，考虑一个低增益直流传感器放大器，要求将电压源输出的10mV信号放大，产生1V的输出，在0~70?C范围内达到±1%的精度。注意，性能要求是±1%的精度。这就是指输出必须在0~70?C温度范围内控制在1 V ±10 mV的限度内。第一步，当然是考虑前面的列表，并决定其中哪些参数是有关的。对这样（非常有限）的参数，两项最重要的指标是电压偏移和对于温度的增益稳定性。我们假设所有的起始误差可以忽略不计（这在实际中是几乎不可能的）。经验丰富的设计人员会知道大多数运放具有极大的开环增益，经常远大于10000。闭环增益±1%的变化意味着环路增益（将在下面说明）的变化在闭环增益为100时应该小于±100%。很明显这将十分容易实现，设计人员会立刻知道计算中他可以使用开环增益的典型值。但是，补偿电压偏移却有所不同。许多运放技术指标仅仅给出补偿电压偏移的典型值，这很可能会在5 V/?C的数量级，而未给出任何器件可以达到的最大值30 V/?C。如果我们碰巧使用的是一个有最不利偏移的器件，那么放大器随温度而产生的误差可为2.1 mV，占所有误差源所产生的总的允许误差的相当大一部分。
这就是我们可以肯定可使用开环增益典型值的情况，不过最大漂移很可能导致相当大的误差。在仔细的设计中这种判定是必要的，而且理解厂商的数据要更加仔细。这种考虑必须推广到前面列出的所有详细资料，除了最不利值通常是不会注明的。经常发现（技术规格表上）给出的值并非是经过100％测试的。例如，采用统计测试可以保证90％的器件的性能在给定范围之内。对于某些用户可能很不方便，他们依赖于技术指标所给出的性能，而随后发现却有“另外”10% 的器件被用在了他们的电路中。
数据寄存器和计数器
数据寄存器
数据寄存器是寄存器中最简单的类型，它可以用来暂时存放数据的一个“字”。其最简单的形式是由共用一个时钟的一组N 个D触发器组成。N比特数据字中的所有位数通过N条数据总线连接数据寄存器。图1.1显示了一个由四个D触发器实现的四位数据寄存器。由于所有触发器同时改变状态，所以这种数据寄存器称为是同步器件。
移位寄存器
用于计算机和许多其它类型逻辑电路的另一种普通寄存器是移位寄存器。它就是一组触发器（通常是D锁存器或RS触发器）联在一起，使其中一个触发器的输出成为下一个的输入，依此形成一串。它称为移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器移动一位。图1.2显示了一个由D触发器实现的四位移位寄存器。
在第一个时钟脉冲的前沿，“DATA”输入端的信号被锁存在第一个触发器中。在下一个时钟脉冲的前沿，第一个触发器的内容被存放到第二个触发器中，而出现在“DATA”输入端的信号则存放在第一个触发器中，依此类推。由于每次有一位数据进入，因此被称为串行输入移位寄存器。由于仅有一个输出，每次从移位寄存器输出1比特数据，因此也称为串行输出移位寄存器。（移位寄存器根据它们的输入输出方式命名，不是串行的就是并行的）。通过预置和清除触发器输入端可以提供并行输入。触发器的并行加载可以是同步的（也就是由时钟脉冲发生），或者异步的（不依赖于时钟脉冲），取决于移位寄存器的设计。如图1.3从每个触发器的输出端可以获得并行输出。
计算机与外设之间的通信一般都是串行的，而计算机内部的计算通常都是用并行逻辑电路来执行的。移位寄存器可以将信息从串行形式转换成并行形式，反之亦然。根据所要求的复杂程度，可以利用许多不同种类的移位寄存器。
计数器——二进制数字的加权编码
在某种意义上，移位寄存器可以看作是一种基于一元数字系统的计数器。可惜的是一个一元计数器在计数范围内对于每一个数字需要一个触发器。然而，一个二进制计数器只需要一个触发器就可以进行N位数据计算。一个简单的二进制加权计数器可用T触发器来构建。触发器依次相连，使一个触发器的输出作为下一个的时钟，依此类推。这样，触发器在链中的位置决定了它的权重，即对于二进制计数器而言就是它所对应的2的幂。如图1.4显示了一个由T触发器组成的三比特（模八）二进制计数器，图1.5是此电路的时序图。
注意，一组接在Q0, Q1, Q2上的灯泡将以二进制（模8）形式显示第一个脉冲以来已完成的完整时钟脉冲数。根据需要很多T触发器组合起来构成许多位数的计数器。
注意在这种计数器中，每一个触发器在前一个触发器送来的脉冲下降沿改变状态。因此将略有时延，这是由一个触发器改变状态到下一个触发器改变状态之间的传播延迟造成
的，即状态变化像波纹一样传过计数器，因而这些计数器被称为波纹计数器。就像波纹进位加法器一样，传播延时会对大数值计数器造成严重影响。
可以通过制作或购买单片芯片计数器来实现计数器的递增计数、递减计数或者预置任何你想要的数字。一个计数器也可以构造出二—十进制、十二进制或者任何进制数的计数器。
一个倒计数计数器可以通过将Q输出连接到前一级计数器的时钟输入来实现。利用预置和清零端，通过用与门将每一个T触发器的输出与另一个逻辑电平作逻辑运算（比方说0为倒计数，1为正计数），则可构成可预置的可逆二进制计数器。图1.6显示了一个没有预置和清零功能的可逆计数器。
同步计数器
以上介绍的是异步计数器，这样叫是因为他们的状态随前一级的状态变化而变化，而非同时变化。一个触发器的输出是下一个的输入，因而状态的变化以波动形式通过各个触发器，所需时间与计数器的长度成正比。可以利用JK触发器来设计同步计数器，所有触发器同时改变状态，即时钟脉冲将同时送给每一级JK触发器。这很容易做到，对于二进制计数器，只要所有前面的数字都是1，任何给定的数字都会改变它的值（从1变为0，或者从0变为1）。一个倒计数定时器可通过将Q输出端通过与门连接到J和K端实现。也可以设置预置和清零功能，像前一种一样，计数器也可以做成可编程的。
同步计数器的时序图类似于异步（波纹）计数器，除了波动时间现在为零以及所有计数器的时钟同时输入之外。对于同步计数器而言，在时钟上升沿触发比在下降沿触发更为常见。
锁相特性
相位检测器将一个周期输入信号的相位与压控振荡器的相位进行比较。相位检测器的输出是它两个输入信号之间相位差的度量。差值电压由环路滤波后，再加到压控振荡器上。压控振荡器的控制电压使频率朝着减小输入信号与本振之间相位差的方向改变。
当锁相环处于锁定状态时，控制电压使压控振荡器的频率正好等于输入信号频率的平均值。对于输入信号的每一周期，振荡器输出也变化一周，且仅仅变化一周。锁相环的一个显而易见的应用是自动频率控制（AFC）。用这种方法可以获得完美的频率控制，而传统的自动频率控制技术不可避免地存在某些频率误差。
为了保持锁定环路所需的控制电压，通常要求相位检测器有一个非零的输出，所以环路是在有一些相位误差条件下工作的。不过实际上对于一个设计良好的环路这种误差很小。
一个稍微不同的解释可提供理解环路工作原理的更好说明。让我们假定输入信号的相位或频率上携带了信息，并且此信号不可避免地受到加性噪声地干扰。锁相接收机的作用是重建原信号而尽可能地去除噪声。
为了重建原始信号，接收机使用一个输出频率与预计信号频率非常接近的本机振荡器。本机振荡和输入信号的波形由相位检测器比较，其误差输出表示瞬时相位差。为了抑制噪声，误差在一定的时间间隔内被平均，将此平均值用于建立振荡器的频率。
如果原信号状态良好（频率稳定），本机振荡器只需要极少信息就能实现跟踪，此信息可通过长时间的平均得到，从而消除可能很强的噪声。环路输入是含噪声的信号，而压控振荡器输出却是一个纯净的输入信号（的复本）。所以，有理由认为环路是一种传输信号并抑制噪声的滤波器。
环路滤波器有两个重要的特性：其一是带宽可以非常窄，其二是滤波器能自动跟踪信号频率。自动跟踪和窄带的特点说明了锁相接收机的主要用途。窄带能够抑制大量的噪声，难怪锁相环路常用来恢复深深地淹没在噪声中的信号。
历史与应用
关于锁相的早期论述（思想）是Bellescize于1932年提出的，并在处理无线电信号同步接收中得到应用。20世纪20年代开始使用超外差接收机，但人们一直努力寻求更简单的接收技术。一种方法就是同步接收机或零差接收机。这种接收机本质上只是由一个本机振荡器，一个混频器和一个音频放大器组成。为了正常工作，必须调节振荡器使其输出频率与输入的信号载波频率完全一致，于是载波被变换成0Hz的“中频”。混频器输出含有解调出来的，由信号边带携带的信息。干扰与本地振荡器不同步，因此由干扰信号引起的混频器输出是一个拍音，可用音频滤波器加以抑制。
对于同步接收，本振的正确调谐至关重要，任何一点频率误差都将严重损坏信号。此外，本振的相位必须与接收的载波相位一致，其间的误差限于周期的很小一部分。就是说，本振与输入信号之间必须实现相位锁定。
由于各种原因简单的同步接收机从未广泛应用过。现在锁相接收机几乎无例外地运用超外差原理，并趋于高度复杂化。锁相接收机最重要的应用之一是接收来自遥远的宇宙飞行器的极微弱信号。锁相技术的首次广泛使用是在电视接收机中的行和帧的同步扫描。与视频信号一起传送的脉冲发出电视图像每一行的开始信号和隔行扫描的半帧开始信号。作为一种非常粗糙的重建电视显象管扫描光栅的方法，这些脉冲可以剥离出来单独用于触发一对单扫描发生器。
一个较为复杂的途径是利用一对自由振荡的张弛振荡器驱动扫描发生器。用这种方法，即使失去同步（消失），扫描还是存在的。
将振荡器的自由振荡频率设置得略低于水平和垂直（扫描）脉冲频率，剥离出来的脉冲用于提前触发振荡器从而使振荡器与行频和半帧频同步（由于美国电视在交替的垂直扫描时进行隔行交织，所以是半帧频）。
在噪声不存在的情况下这种方案可提供良好的同步，这就完全可以了。不幸的是噪声总是存在的，并且任何触发电路对噪声都是特别敏感的。在极端情况下触发扫描将完全失效，尽管在这样的信噪比条件下电视图像虽然较差却还能辩认。
在不是极端恶劣的条件下，噪声将造成起始时间抖动和偶尔的误触发。行抖动将降低行清晰度,并使得垂直线条呈现锯齿状。严重的水平误触发通常会造成画面出现狭窄的水平黑带。
帧扫描抖动会引起图像的垂直滚动。另外，相继半帧之间的隔行扫描行还会相对移动，使图像进一步恶（退）化。
将两个振荡器与剥离出来的同步脉冲锁相可大大减小噪声起伏。锁相技术靠检查各振荡器和许多同步脉冲之间的相位关系来调节振荡频率，使得平均相位偏差很小，而不是仅用一个脉冲进行触发。由于锁相同步器检测许多脉冲，因此它不会被偶发的破坏同步器触发的大幅度脉冲噪声所干扰。目前电视接收机中使用的飞轮同步器实际上就是锁相环路。使用飞轮一词是因为此电路能够跟踪增加的噪声或微弱信号的周期。通过锁相可以获得同步性能的重大改进。
在彩色电视接收机中色同步信号是由锁相环路同步的。
宇宙飞行的需要强烈地刺激了锁相技术的应用。锁相的空间应用是随着早期美国人造卫星的发射而开始的。这些飞行体携带低功率（10毫瓦）的连续波发射机，相应的接收信号很微弱。由于多普勒频移和发射振荡器的频率漂移，接收信号的精确频率难以确定。在最初使用的108MHz频率上，多普勒频移可在±3kHz范围内。
因此使用普通的固定调谐接收机时，带宽至少应为6kHz，然而信号本身却只占非常窄的频谱，大约在6Hz带宽内。
接收机中的噪声功率与带宽成正比，所以如果使用传统的技术，就不得不接受1000倍（30dB）噪声的代价。随着技术的进步这些数字变得更加惊人。发射频率上升到了S波段，使多普勒频移范围达到±75kHz，而接收机带宽则已减小到3Hz。这样一来常规技术的代价就将是47dB左右。这是无法接受的，也就是要使用窄带的锁相跟踪接收机的原因所在。
窄带滤波器能抑制噪声，但是如果滤波器被固定，则信号将几乎总是落在通带之外。一个可用的窄带滤波器必须有跟踪信号的能力。锁相环路既提供了窄带，又提供了所需的跟踪能力。而且，非常窄的带宽也能方便地获得（对于空间应用典型的是３到1000Hz）。如果需要的话，还能容易地改变带宽。
对于多普勒信号，用于确定飞船速度的信息是多普勒频移。锁相接收机很适合用于多普勒恢复，因为当锁相环路锁定时不存在频率误差。
其它应用
以下的应用阐述了目前锁相技术的一些应用，这些应用将在本书其他章节进一步讨论。
1.跟踪运动飞船的一种方法涉及到将相干信号发射到飞船上，将信号频率偏移并转
发回地面。飞船上的相干应答器必须如此工作以使输入和输出频率严格地成m/n
的比例关系，此处m和n都是整数。锁相技术经常被用来建立相干性。
2.锁相环可用作频率解调器，锁相环在其中比传统的鉴频器具有更优越的性能。
3.带有噪声的振荡器可被包围在环路内，并使之锁定在一个纯净的信号上。如果环
路具有大的带宽，振荡器检测出自已的噪声，其输出被大大净化。
4.用锁相环路可构成频率倍乘器和分频器。
5.数字传输的同步通常应用锁相技术实现。
6.频率合成器可方便地用锁相环路构成。
Analog and Digital
Ideal Operational Amplifiers and Practical Limitations In order to discuss the ideal parameters of operational amplifiers, we must first define the
terms, and then go on to describe what we regard as the ideal values for those terms. At first
sight, the specification sheet for an operational amplifier seems to list a large number of values, some in strange units, some interrelated, and often confusing to those unfamiliar with the subject. The approach to such a situation is to be methodical, and take the necessary time to read and understand each definition in the order that it is listed. Without a real appreciation of what each means, the designer is doomed to failure. The objective is to be able to design a circuit from the basis of the published data, and know that it will function as predicted when the prototype is constructed.1It is all too easy with linear circuits, which appear relatively simple when compared with today?s complex logic arrangements, to ignore detailed performance parameters which can drastically reduce the expected performance.
Let us take a very simple but striking example. Consider a requirement for an amplifier
having a voltage gain of 10 at 50 kHz driving into a 10 k load. A common low-cost, internally
frequency-compensated op amp is chosen; it has the required bandwidth at a closed-loop gain of
10, and it would seem to meet the bill. The device is connected, and it is found to have the
correct gain. But it will only produce a few volts output swing when the data clearly shows that
the output should be capable of driving to within two or three volts of the supply rails. The
designer has forgotten that the maximum output voltage swing is severely limited by frequency,
and that the maximum low-frequency output swing becomes limited at about 10 kHz. Of course,
the information is in fact on the data sheet, but its relevance has not been appreciated. This sort
of problem occurs regularly for the inexperienced designer. So the moral is clear: always take
the necessary time to write down the full operating requirements before attempting a design.
Attention to the detail of the performance specification will always be beneficial. It is suggested
the following list of performance details be considered:
1. Closed loop gain accuracy, stability with temperature, time and supply voltage
2. Power supply requirements, source and load impedances, power dissipation
3. Input error voltages and bias currents. Input and output resistance, drift with time and
temperature
4. Frequency response, phase shift, output swing, transient response, slew rate, frequency
stability, capacitive load driving, overload recovery
5. Linearity, distortion and noise
6. Input, output or supply protection required. Input voltage range, common-mode rejection
7. External offset trimming requirement
Not all of these terms will be relevant, but it is useful to remember that it is better to consider them initially rather than to be forced into retrospective modifications.
All parameters are subject to wide variations
Never forget this fact. How many times has a circuit been designed using typical values,
only to find that the circuit does not work because the device used is not typical? The above statement thus poses a tricky question: when should typical values and when should worst-case values be used in the design? This is where the judgment of the experienced designer must be brought to bear. Clearly, if certain performance requirements are mandatory, then worst-case values must be used. In many cases, however, the desirability of a certain defined performance will be a compromise between ease of implementation, degree of importance, and economic considerations.
Do not over-specify or over-design
In the end, we are all controlled by cost, and it is really pointless taking a sledgehammer to crack a nut, Simplicity is of the essence since the low parts count implementation is invariably cheaper and more reliable.
As an example of this judgment about worst-case design, consider a low-gain DC transducer amplifier required to amplify 10 mV from a voltage source to produce an output of .l V with an accuracy of ±1% over a temperature range of 0~70?C. Notice that the specification calls for an accuracy of ±1%. This implies that the output should be 1 V ±10 mV from 0 ~ 70?C. The first step is, of course, to consider our list above, and decide which of the many parameters are relevant. Two of the most important to this (very limited) specification are offset voltage drift and gain stability with temperature. We will assume that all initial errors are negligible (rarely the case in practice). The experienced designer would know that most op amps have a very large open-loop gain, usually very much greater than 10000. A closed-loop gain change of ±1% implies that the loop gain (as explained later) should change by less than ±100% for a closed-loop gain of 100. This is clearly so easily fulfilled that the designer knows immediately that he can use typical open-loop gain values in his calculations. However, offset voltage drift is another matter. Many op amp specifications include only typical values for offset voltage drift; this may well be in the order of 5 μV/?C, with an unquoted maximum for any device of 30 μV/?C. If by chance we use a device which has this worst-case drift, then the amplifier error could be 30×70=2100 μV=2.1 mV over temperature, which is a significant proportion of our total allowable error from all sources.
Here is a case, then, where one can be confident that the typical value of open-loop gain can be used, but where the maximum value of drift may well cause significant errors. This sort of judgment is essential in careful design, and great care is required in interpreting manufacturers? data. This consideration must be extended to all the details listed above apart from the fact that worst-case values are often not quoted. It is often found that values given are not 100% tested. Statistical testing is employed which, for example, guarantees that 90% of all devices fall within the range specified. It could be very inconvenient for the user who relies on the specified performance and then finds that he has several of the …other? 10% actually plugged into his circuit.
Data Registers and Counters
Data register
The simplest type of register is a data register, which is used for the temporary storage of a “word” of data. In its simplest form, it consists of a set of N D flip-flops, all sharing a common
clock. All of the digits in the N bit data word are connected to the data register by an N-line “data bus”. Figure 1.1 shows a 4 bit data register, implemented with four D flip-flops. The data register is said to be a synchronous device, because all the flip-flops change state at the same time.
Shift registers
Another common form of register used in computers and in many other types of logic circuits is a shift register. It is simply a set of flip-flops (usually D latches or RS flip-flops) connected together so that the output of one becomes the input of the next, and so on in series. It is called a shift register because the data is shifted through the register by one bit position on each clock pulse. Figure 1.2 shows a 4 bit shift register, implemented with D flip-flops.
On the leading edge of the first clock pulse, the signal on the DATA input is latched in the first flip-flop. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-flop, and the signal which is present at the DATA input is stored in the first flip-flop, etc. Because the data is entered one bit at a time, this called a serial-in shift register. Since there is only one output, and data leaves the shift register one bit at a time, then it is also a serial out shift register. (Shift registers are named by their method of input and output; either serial or parallel.) Parallel input can be provided through the use of the preset and clear inputs to the flip-flop. The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. Parallel output can be obtained from the outputs of each flip-flop as shown in Figure 1.3.
Communication between a computer and a peripheral device is usually done serially, while computation in the computer itself is usually performed with parallel logic circuitry. A shift register can be used to convert information from serial form to parallel form, and vice versa. Many different kinds of shift registers are available, depending upon the degree of sophistication required.
Counters — weighted coding of binary numbers
In a sense, a shift register can be considered a counter based on the unary number system. Unfortunately, a unary counter would require a flip-flop for each number in the counting range.
A binary weighted counter, however, requires only flip-flops to count to N. A simple binary weighted counter can be made using T flip-flops. The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for a binary counter, the “power of two” it corresponds to. A 3-bit (modulo 8) binary counter could be configured with T flip-flops as shown in Figure 1.4. A timing diagram corresponding to this circuit is shown in Figure 1.5.
Note that a set of lights attached to O0, O1, O2would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. As many T flip-flops as required could be combined to make a counter with a large number of digits.
Note that in this counter, each flip-flops changes state on the falling edge of the pulse from the previous flip-flop. Therefore there will be a slight time delay, due to the propagation delay of the flip-flops between the time one flip-flop changes state and the time the next one changes state, i.e., the change of state ripples through the counter, and these counters are therefore called ripple counters. As in the case of a ripple carry adder, the propagation delay can become
significant for large counters.
It is possible to make, or buy in a single chip, counters which will count up, count down, and which can be preset to any desired number. Counters can also be constructed which count in BCD and base 12 or any other number base.
A count down counter can be made by connecting the Q output to the clock input in the previous counter. By the use of preset and clear inputs, and by gating the output of each T flip- flop with another logic level using AND gates (say logic 0 for counting down, logic 1 for counting up), then a presetable up-down binary counter can be constructed. Figure 1.6 shows an up-down counter, without preset or clear.
Synchronous counters
The counters shown previously have been “asynchronous counters”; so called because the flip-flops do not all change state at the same time, but change as a result of a previous output. The output of one flip-flop is the input to the next; the state changes consequently “ripple through” the flip-flops, requiring a time proportional to the length of the counter. It is possible to design synchronous counters, using JK flip-flops, where all flip-flops change state at the same time; i.e., the clock pulse is presented to each JK flip-flop at the same time. This can be easily done by nothing that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1. A count down timer can be made by connecting the Q output to the J and K, through the AND gates. Preset and clear could also be provided, and the counter could be made “programmable” as in the previous case.
The timing diagram is similar to that shown for the asynchronous (ripple) counters, except that the ripple time is now zero; all counters clock at the same time. It is common for synchronous counters to trigger on the positive edge of the clock, rather than the trailing edge.
Nature of Phase Lock
The phase detector compares the phase of a periodic input signal against the phase of the VCO. Output of PD is a measure of the phase difference between its two inputs. The difference voltage is then filtered by the loop filter and applied to the VCO. Control voltage on the VCO changes the frequency in a direction that reduces the phase difference between the input signal and the local oscillator.
When the loop is locked, the control voltage is such that the frequency of the VCO is exactly equal to the average frequency of the input signal. For each cycle of input there is one, and only one, cycle of oscillator output. One obvious application of phase lock is in automatic frequency control (AFC). Perfect frequency control can be achieved by this method, whereas conventional AFC techniques necessarily entail some frequency error.
To maintain the control voltage needed for lock it is generally necessary to have a nonzero output from the phase detector. Consequently, the loop operates with some phase error present. As a practical matter, however, this error tends to be small in a well-designed loop.
A slightly different explanation may provide a better understanding of loop operation. Let us suppose that the incoming signal carries information in its phase or frequency; this signal is inevitably corrupted by additive noise. The task of a phase lock receiver is to reproduce the original signal while removing as much of the noise as possible.
To reproduce the signal the receiver makes use of a local oscillator whose frequency is very close to that expected in the signal. Local oscillator and incoming signal waveforms are compared with one another by a phase detector whose error output indicates instantaneous phase difference. To suppress noise the error is averaged over some length of time, and the average is used to establish frequency of the oscillator.
If the original signal is well behaved (stable in frequency), the local oscillator will need very little information to be able to track, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large. The input to the loop is a noisy signal, whereas the output of the VCO is a cleaned-up version of the input. It is reasonable, therefore, to consider the loop as a kind of filter that passes signals and rejects noise.
Two important characteristics of the filter are that the bandwidth can be very small and that the filter automatically tracks the signal frequency. These features, automatic tracking and narrow bandwidth, account for the major uses of phase lock receivers. Narrow bandwidth is capable of rejecting large amounts of noise; it is not at all unusual for a PLL to recover a signal deeply embedded in noise.
History and application
An early description of phase lock was published by de Bellescize in 1932 and treated the synchronous reception of radio signals. Superheterodyne receivers had come into use during the 1920s, but there was a continual search for a simpler technique; one approach investigated was the synchronous, or homodyne, receiver. In essence, this receiver consists of nothing but a local oscillator, a mixer, and an audio amplifier. To operate, the oscillator must be adjusted to exactly the same frequency as the carrier of the incoming signal, which is then converted to an intermediate frequency of exactly 0 Hz. Output of the mixer contains demodulated information that is carried as sidebands by the signal. Interference will not be synchronous with the local oscillator, and therefore mixer output caused by an interfering signal is a beat-note that can be suppressed by audio filtering.
Correct tuning of the local oscillator is essential to synchronous reception; any frequency error whatsoever will hopelessly garble the information. Furthermore, phase of the local oscillator must agree, within a fairly small fraction of a cycle, with the received carrier phase. In other words, the local oscillator must be phase locked to the incoming signal.
For various reasons the simple synchronous receiver has never been used extensively. Present-day phase lock receivers almost invariably use the superheterodyne principle and tend to be highly complex. One of their most important applications is in the reception of the very weak signals from distant spacecraft. The first widespread use of phase lock was in the synchronization of horizontal and vertical scan in television receivers. The start of each line and the start of each interlaced half-frame of a television picture are signaled by a pulse transmitted with the video information. As a very crude approach to reconstructing a scan raster on the TV tube, these pulses can be stripped off and individually utilized to trigger a pair of single sweep generators.
A slightly more sophisticated approach uses a pair of free-running relaxation oscillators to drive the sweep generators. In this way sweep is present even if synchronization is absent.
Free-running frequencies of the oscillators are set slightly below the horizontal and vertical pulse rates, and the stripped pulses are used to trigger the oscillators prematurely and thus to synchronize them to the line and half-frame rates (half-frame because United States television interlaces the lines on alternate vertical scans).
In the absence of noise this scheme can provide good synchronization and is entirely adequate. Unfortunately, noise is rarely absent, and any triggering circuit is particularly susceptible to it. As an extreme, triggered scan will completely fail at a signal-to-noise ratio that still provides a recognizable, though inferior, picture.
Under less extreme conditions noise causes starting-time jitter and occasional misfiring far out of phase. Horizontal jitter reduces horizontal resolution and causes vertical lines to have a ragged appearance. Severe horizontal misfiring usually causes a narrow horizontal black streak to appear.
Vertical jitter causes an apparent vertical movement of the picture. Also, the interlaced lines of successive half-frames would so move with respect to one another that further picture degradation would result.
Noise fluctuation can be vastly reduced by phase locking the two oscillators to the stripped sync pulses. Instead of triggering on each pulse a phase-lock technique examines the relative phase between each oscillator and many of its sync pulses and adjusts oscillator frequency so that the average phase discrepancy is small.Because it looks at many pulses, a phase lock synchronizer is not confused by occasional large noise pulses that disrupt a triggered synchronizer. The flywheel synchronizers in present day TV receivers are really phase-locked loops. The name “flywheel”is used because the circuit is able to coast through periods of increased noise or weak signal. Substantial improvement in synchronizing performance is obtained by phase-lock.
In a color television receiver, the color burst is synchronized by a phase-lock loop.
Space flight requirements inspired intensive application of phase lock methods. Space use of phase lock began with the launching of the first American artificial satellites. These vehicles carried low-power (10 mW) CW transmitters; received signals were correspondingly weak. Because of Doppler shift and drift of the transmitting oscillator, there was considerable uncertainty about the exact frequency of the received signal. At the 108 MHz frequency originally used, the Doppler shift could range over a ±3 kHz interval.
With an ordinary, fixed-tuned receiver, bandwidth would therefore have to be at least 6 kHz, if not more. However, the signal itself occupies a very narrow spectrum and can be contained in something like a 6 Hz bandwidth.
Noise power in the receiver is directly proportional to bandwidth. Therefore, if conventional techniques were used, a noise penalty of 1000 times (30 dB) would have to be accepted. The numbers have become even more spectacular as technology has progressed; transmission frequencies have moved up to S-band, making the Doppler range some ±75 kHz, whereas receiver bandwidths as small as 3 Hz have been achieved. The penalty for conventional techniques would thus be about 47 dB. Such penalties are intolerable and that is why narrowband, phase-locked, tracking receivers are used.
Noise can be rejected by a narrowband filter, but if the filter is fixed the signal almost never will be within the pass-band. For a narrow filter to be usable it must be capable of tracking the signal. A phase-locked loop is capable of providing both the narrow bandwidth and the tracking that are needed. Moreover, extremely narrow bandwidths can be conveniently obtained (3 to 1000 Hz are typical for space applications); if necessary, bandwidth is easily changed.
For a Doppler signal the information needed to determine vehicle velocity is the Doppler shift. A phase-lock receiver is well adapted to Doppler recovery, for it has no frequency error when locked.
Other applications
The following applications, further discussed elsewhere in the book, represent some of the current uses of phase-lock.
1. One method of tracking moving vehicles involves transmitting a coherent signal to the
vehicle, offsetting the signal frequency, and re-transmitting back to the ground. The coherent transponder in the vehicle must operate so that the input and output frequencies are exactly related in the ratio m/n, where m and n are integers. Phase-lock techniques are often used to establish coherence.
2. A phase-locked loop can be used as a frequency demodulator, in which it has superior
performance to a conventional discriminator.
3. Noisy oscillators can be enclosed in a loop and locked to a clean signal. If the loop has a
wide bandwidth, the oscillator tracks out its own noise and its output is greatly cleaned up.
4. Frequency multipliers and dividers can be built by using PLLs.
5. Synchronization of digital transmission is typically obtained by phase-lock methods.
6. Frequency synthesizers are conveniently built by phase-lock loops.