LV51134T-TLM-E;中文规格书,Datasheet资料

LV1017Overview The LV1017 is a passive decoder for Dolby surround systems.Features• Original A/D, D/A converter • Wide dynamic range • Virtual surround function• Rear stereo, pseudo-multi-tap function • Surround trim (Ls, Rs) external input• Built-in Lch, Rch, Lsch, Rsch output switching function • Reduced external component countSpecificationsMaximum Ratings at Ta = 25°CParameter SymbolConditionsRatings UnitMaximum power supply voltage V CC max12VAllowable power dissipation Pd max Ta ≤ 70°C 450mW Operating temperature Topr -20 to +70°C Storage temperatureTstg-40 to +125°COperating Conditions at Ta = 25°CParameter SymbolConditionsRatings UnitRecommended operating voltage V CC9V Allowable operating voltage range 1 V CC range1 When Dolby surround is ON8 to 10V Allowable operating voltage range 2 V CC range2 When Dolby Pro Logic surround is ON 8.5 to 10V Dolby levelV O Dolby300mVrmsInput "H" level voltage V IH3.5 to 5.5V Input "L" level voltageV IL0 to 1.0VBi-CMOS ICPassive Decoder forDolby Surround SystemsElectrical Characteristics at Ta = 25°C, V CC = 9V V IN = 300mV = 0dB, h = 1kHz, Dolby passive modeRatingsUnit Parameter Symbol Conditionsmin typ maxsignal 15 24 36mA Current consumption I CCO No[LS, RSch]SH1S V CC = 8.5V, DIST < 3%, S-IN 15 dB Signal handlingSH2S V CC = 8V, DIST < 3%, L-R-IN 10 dBS/N SNS CCIR/ARM, Rg = 10k 65 75 dB Output level variation VOS -3 0 +3dB Distortion factor THDS 0.1 0.7% [Lch]Signal handling SH1L V CC = 8.5V, DIST < 3% 15 dBS/N SNL CCIR/ARM, Rg = 10k 80 90 dB Output level variation VOL -2 0 +2dB Distortion factor THDL 0.01 0.05% [Rch]Signal handling SH1R V CC = 8.5V, DIST < 3% 15 dBS/N SNR CCIR/ARM, Rg = 10k 80 90 dB Output level variation VOR -2 0 +2dB Distortion factor THDR 0.01 0.05%When s trim is -15dB STRIM1 When setting -15dB -16 -15 -14dB When s trim is -31dB STRIM2 When setting -31dB -33 -31 -29dB1kHz -1.5 0 +1.5dBDec1 0dB,1kHz -24 -22.5 +21dBDec2 -20dB,5kHz -1.5 0 +1.5dBDec3 0dB,NR frequency characteristicDec4 -20dB,5kHz -23.3 -21.8 +20.3dB5kHz -46.8 -45.3 +43.8dBDec5 -40dB,Package Dimensionsunit : mm。

LM98555LM98555 CCD DriverLiterature Number: SNAS290CLM98555 CCD DriverGeneral DescriptionThe LM98555 is a highly integrated driver circuit intended for CCD driving applications. It combines 25 drivers of varying drive strengths into one chip to provide a complete CCD driv-ing solution. Due to this one-chip integration, optimal skew control is achieved for this demanding application. Features■All CCD drivers integrated into one package■High strength drivers designed specifically for CCD loads ■Ability to scale clock driver strength■Skew specifications guaranteed■Separate input and output power supplies ■CMOS process technology■64-pin TSSOP package with extended power handling capabilityKey SpecificationsSupply Voltage Inputs 3.0 to 5.5VDrivers 4.5 to 5.8V Maximum Output Skew Between P1Aand P2Aoutputs0.5 nsMaximum PowerHandling2.0WFunctional Description20126401FIGURE 1. Functional Block DiagramTRI-STATE® is a registered trademark of National Semiconductor Corporation.© 2007 National Semiconductor 98555 CCD DriverCommercial Temperature RangeNS PackageLM98555CCMH64-Pin Exposed Pad TSSOPConnection Diagram20126402FIGURE 2. TSSOP Package Pinout 2L MSymbol Pin Type DescriptionDriver inputsP2BIN8Input CMOS logic input for the P2B driver.RSIN9Input CMOS logic input for the RS driver.CPIN10Input CMOS logic input for the CP driver.P1AIN15Input CMOS logic input for the P1A ganged (8) driver set.P2AIN18Input CMOS logic input for the P2A ganged (8) driver set.SHIN21Input CMOS logic input for the SH ganged (3) driver set.AFEIN22Input CMOS logic input for the AFE driver.MCLIN23Input CMOS logic input for the MCL driver.SHDIN24Input CMOS logic input for the SHD driver.Driver OutputsSHDOUT28Output; Low-Strength Driver output for the SHDINinput signal.MCLOUT30Output; Low-Strength Driver output for the MCLINinput signal.AFEOUT31Output; Low-Strength Driver output for the AFEINinput signal.CPOUT2Output; Low-Strength Driver output for the CPINinput signal. Typically used to drive the Clamp Gate input of the CCD.RSOUT3Output; Low-Strength Driver output for the RSINinput signal. Typically used to drive the Reset Gate input of the CCD.P2BOUT5Output; Low-Strength Driver output for the P2BINinput signal.P2AOUT047Output; TRI-STATE®; High-Strength Ganged driver outputs for the P2AINinput. Typically the user may join together these outputs to drive the φ2 clock input of the CCD. Some of these outputs may be disabled using the EN(1:0) inputs - see the Functional Description section.P2AOUT146P2AOUT243P2AOUT342P2AOUT439P2AOUT538P2AOUT635P2AOUT734P1AOUT050Output; TRI-STATE; High-Strength Ganged driver outputs for the P1AINinput. Typically the user may join together these outputs to drive the φ1 clock input of the CCD. Some of these outputs may be disabled using the EN(1:0) inputs - see the Functional Description section.P1AOUT151P1AOUT254P1AOUT355P1AOUT458P1AOUT559P1AOUT662P1AOUT763SHOUT026Output; Low-Strength Ganged driver outputs for the SHINinput signal. Typically used to drive the Shift Gate input of the CCD.SHOUT127SHOUT26Logic InputsEN011Input Driver enable control. Some of the P1A and P2A drivers can be disabled usingthese inputs. See the Functional Description section.EN112555Power & Ground Pins V DDI141620PowerV DD for pre-drivers.V DDO17293237404549535760PowerV DD for final-stage driver.GND I131719Ground Ground connection for all circuitry other than the Final-Stage Drivers.GND O425333641444852566164Ground Ground connection for the Final-Stage Drivers. 4L MIf Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage−0.5V to 6.2V Package Power Rating at 25°C(Note 2) 2.0 Watts Voltage on Any Input or Output Pin−0.5V to VDD+0.5V DC Input Current at Any Pin25 mA DC Package Input Current50 mA Storage Temperature−65°C to +150°C Lead temperature (Soldering, 10 sec.)300°C ESD SusceptibilityHuman Body Model2000V Machine Model200V Operating ConditionsSupply VoltageVDDI+3.0V to +5.5V Supply VoltageVDDO+4.5V to +5.8VSupply Sequencing(Note 3)VDDI < VDDO+0.2VAmbient Temperature (TA)0 to 70°C Operating Frequency30 MHz Power Dissipation (Note 4) 2.0W Package Thermal Resistances PackageθJ-A(Note 5)θJ-PAD(Thermal Pad) 64-Lead ExposedPad TSSOP36.8°C / W 6.2°C / WDC Electrical CharacteristicsThe following specifications apply for GND = 0V, VDDI = 3.3V, VDDO= 5.0V, unless noted otherwise. Boldface limits apply forT A = TMINto TMAX; all other limits TA= 25°CSymbol Parameter Conditions Min Typical Max UnitsI I Logic 1 Input Current VI= VDDI-10.0041µALogic 0 Input Current VI= GNDI-10.0061µAV IT Input Threshold VDDI= 3.3V 1.41 1.57 1.75VInput Threshold VDDI= 5.0V 2.48VInput Threshold Hysteresis VDDI= 3.3V-7211100mVΔV IT Input Threshold Variation Between P1A, P2A inputs-100100mVROOutput Impedance P1A and P2AOutputs ILOAD= 525 mA6.19.9ΩRO= (VDDO- VO)/IOHorRO= VO/IOLROOutput Impedance All OtherOutputs ILOAD= 280 mA10.217.4ΩRO= (VDDO- VO)/IOHorRO= VO/IOL555The following specifications apply for GND = 0V, V DDI = 3.3V, V DDO = 5.0V, unless noted otherwise. Boldface limits apply for T A = T MIN to T MAX ; all other limits T A = 25°C Symbol ParameterConditionsMin Typical Max Unit PHL Prop Delay: High-to-Low P1A and P2A Outputs C L = 220 pF, R L = 10Ω(Note 6)3.064.66.55nst PHLProp Delay: High-to-Low CP, RS, P2B Outputs C L = 82 pF, R L = 10Ω(Note 6)(Note 8)4.1nst PLH Prop Delay: Low-to-High P1A and P2A Outputs C L = 220 pF, R L = 10Ω(Note 7)3.384.96.68nst PLHProp Delay: Low-to-High CP, RS, P2B Outputs C L = 82 pF, R L = 10Ω(Note 7)(Note 8)4.2nst SKEWProp Delay Skew High-to-Low Between any P1A or P2A Outputs on a Single UnitC L = 220 pF, R L = 10Ω109387psProp Delay Skew Low-to-High157490Important Note: Not all drivers can be loaded to the highest specified load at the same time without violating the maximum power dissipation limit. The syst design must guarantee that the maximum power dissipation specification is never exceeded.Note 1:Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devic should be operated at these limits.Note 2:Package power rating assumes the exposed thermal pad is soldered to the printed circuit board as recommended, with significant heat spreading provid by vias to internal or bottom heat dissipation planes or pad. If this is not the case, then the package power rating should be reduced. See the Thermal Guidelin in the applications section for more information.Note 3:When powering up and down, transient voltage levels on V DDI must be lower than (V DDO + 0.2V)Note 4:This is the power dissipated on-chip due to all currents flowing through the device - both DC and AC. This operating condition will be violated if all dri outputs are fully loaded and operating at the same time at the rated F MAX . The system design must constrain the chip's operating conditions (loads, power supp number of parallel drivers enabled, frequency of operation) to make certain that this limit is never exceeded.Note 5:Package thermal resistance for junction to ambient is based on a 5.5 inch by 3 inch, 4 layer printed circuit board, with thermal vias connecting the he sinking pad to a full internal ground plane. Tests were done in still air, with a power dissipation of 2.0 W, at an ambient temperature of 22°C.Note 6:Propagation Delay High-to-Low with output low trigger voltage at V DDO *0.75.Note 7:Propagation Delay Low-to-High with output high trigger voltage at V DDO *0.25.Note 8:Typical values determined from characterization testing only. Not production tested or guaranteed.Test Conditions20126403FIGURE 3. AC Test Conditions 6L MThe LM98555 is a fully integrated clock driver/buffer for high speed CCD applications. It provides high performance low impedance drivers, with optimized low skew performance of the P1 and P2 outputs. Enable inputs allow use of two, four,six, or all eight P1 and P2 drivers to optimize the amount of drive for the application. The 64 pin thermally enhanced TSSOP provides excellent power handling through the use of an exposed heat transfer pad on the underside of the pack-age.THERMAL GUIDELINESThe LM98555's maximum power dissipation limit, shown in the Operating Conditions section, must be strictly adhered to.The product's multiple high-strength drivers, with their ability to drive a wide-range of loads, make it possible to be within spec on each output and yet violate the aggregate maximum power dissipation limit for the total product. Special caution must be paid to this by limiting the chip's operating conditions (loads, power supply, number of parallel drivers enabled, fre-quency of operation) to make certain that the maximum power dissipation limit is never exceeded.Thermal characterization of the device has been done to pro-vide reference points under specific conditions. θ junction to ambient was measured using a 5.5 inch by 3 inch, 4 layer PCB. The thermal contact pad on the board was connected using vias to a full ground plane on one of the internal layers.The recommended thermal pad is shown in Figure 4.20126406FIGURE 4. Exposed Pad Land PatternThe vias shown provide a path for heat to flow from the pad to a heat sinking or dissipating area of the printed circuit board. The following figures show several typical examples of how this can be done, and illustrate how heat is conducted away from the IC to larger areas where it is dissipated.20126407FIGURE 5. 4 Layer PCB - Example 120126409FIGURE 6. 4 Layer PCB - Example 220126408FIGURE 7. 2 Layer PCB555mal pad to this ground plane with vias will usually provide adequate heat management. In 2 layer boards, it is important to provide a large heat spreading pad on the opposite side of the board. The vias will provide a good thermal connection between the pad under the IC, and the heat spreading pad on the bottom of the board. Thermal modelling can be done using the θ junction to pad information provided, to calculate the required area of copper based on the ambient temperature of the system, and the calculated amount of thermal dissipation in the LM98555.POWER DISSIPATIONThe amount of power dissipated in the device can be deter-mined by considering the following factors:•Power dissipated delivering energy to the load capacitance•Power dissipated delivering energy to parasitic capacitance•Power dissipated due to leakage in the ICThe amount of power dissipated due to leakage is very small in this CMOS device. Most of the power will be due to the load capacitance being switched, with a small additional amount caused by the parasitic capacitance of the output circuitry,output pins, and PCB traces. A typical parasitic capacitance would be on the order of 5 pF. Since the load capacitance will be on the order of 100 pF or more, this usually dominates the power dissipation calculation. The following equation can be used to calculate the power dissipation due to capacitive switching of the loads:P = Sum[Output Frequency x Load Capacitance x Output Voltage Squared] (summed for all outputs)INPUT SIGNALSCare should be taken to match the trace lengths between timing signals that require low skew. Usually, the P1A and P2A signals will be the most critical. In some applications, the timing of P2B with respect to P1A and P2A can also be im-portant, and that input trace should also be carefully de-signed.Trace shape and width should also be carefully controlled.The trace geometry will determine the characteristic impedance of each trace. The impedance should be set to give reasonable immunity to noise coupling into the trace.With a known trace impedance, the signals can be terminated using a series resistor at the source that is equal to the char-acteristic impedance. This will provide a signal with minimum overshoot and ringing, and will contribute to better perfor-mance of the final signal reaching the CCD.OUTPUT CONNECTIONS AND LOADING EXAMPLES The LM98555 can be used with a wide variety of different CCD sensors. The P1Aoutx and P2Aoutx outputs can be se-lectively enabled to provide 2, 4, 6, or 8 drivers. This allows the available drive strength to be optimized for the sensor and application. Connecting multiple outputs together in parallel as shown in the typical application circuit provides lower drive impedance as needed to suit the load being driven. When driving smaller loads, lower switching noise will be generated if the minimum necessary outputs are enabled and used.The output signal traces should also be designed for a known impedance. Source terminating resistors should be used in series with each output to provide good matching to the trace characteristic impedance. The resistors should be located asbe combined after the termination resistors. This will provi the best summing of adjacent outputs. The combined sign should then pass through an EMI type ferrite bead. This co ponent can be selected to change the bandwidth or shape the clocking signal to achieve the best CCD transfer efficie cy.Several other techniques will also help maintain signal quali and minimize timing differences between critical signals. Vi should not be used for critical timing signals. These can a impedance discontinuities that will affect the waveform qu ity. Traces should have gradual bends and avoid sha changes in direction that can also introduce impedance d continuities.SELECTIVE DRIVER ENABLINGWith the Enable pins, the user has the capability to enab only the drivers that are required for the application, th eliminating unnecessary outputs switching. The following ble shows the details.EN1EN0Driver-set State00P1Aout(1:0) and P2Aout(1:0) are enabled; a others disabled.01P1Aout(3:0) and P2Aout(3:0) are enabled; a others disabled.10P1Aout(5:0) and P2Aout(5:0) are enabled; a others disabled.11All P1Aout and P2Aout drivers are enabled.Note: The disabled drivers' outputs are in TRI-STATE.POWER SUPPLY SEQUENCINGDuring device power-up and power-down, V DDI must be ma tained less than (V DDO + 0.2V) to prevent excessive curre flow through the internal ESD protection circuitry. Since mo applications will involve 3V on V DDI and 5V on V DDO , this c be easily met. If this voltage relationship cannot be met, th the DC pin and package limits for input current must be ma tained by controlling the source impedance of the V DDI suppPOWER AND GROUND - PLANES VERSUS BUSES The best performance will be achieved by using planes rath than traces for power and ground. Planes provide lower ele trical and thermal impedance. Ground bounce and ringing a reduced, electromagnetic emissions are minimized and t best thermal performance will be realized.A single common ground plane should be used for all pow and signal domains.Another circuit board layer can be used to provide power the various circuitry. Different power buses can be provid by isolated planes within this layer of the circuit board.EMI MANAGEMENTGood EMI control will be achieved by addressing the followi items:•Provide proper source termination of output signals •Limit length of output traces•Ensure adequate power supply decoupling•Provide power and ground planes as much as possible •Provide common ground plane for all signals, especiall between LM98555 outputs and load CCD•Enable and use the minimum number of outputs neede 8L M64-TSSOPNS Package Number MXD64A 555分销商库存信息:NATIONAL-SEMICONDUCTORLM98555CCMH/NOPB LM98555CCMHX/NOPB。

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LM78LXX系列三端正稳压器一般描述 LM78LXX系列三端正向稳压器是可用几个固定的输出电压使他们在广泛的应用中 有用.当用作齐纳二极管/电阻组合替代，LM78LXX usu-盟友导致有效的输出阻抗改善两个数量级以及更低的静态电流.这 些监管机构可以提供当地的卡规，消除与单点规则相关的分配问题 - 灰.可用电压允许LM78LXX用于逻辑系统，仪器仪 表，HiFi等固态电子设备. LM78LXX采用塑料TO-92（Z）封装，塑料SO-8（M）封装和芯片尺寸封装 （8-Bump micro SMD）采用美国国家半导体的微型SMD封装技术.如果有足够的散热片，肝脏100毫安输出电流.电流限制包括在内将峰 值输出电流限制在安全值.安全区域pro-提供对输出晶体管的检测以限制内部功耗.如果内部功耗变得太大高散热提供， 热关断CIR - cuit接管防止IC过热.特征 ? LM78L05采用微型SMD封装 ? 输出电压容差 在整个温度 范围内的 ± 5％范围 ?输 出电流100毫安 ?内部热过载保护 ?输出晶体管安全区域保护 ?内部短路电流限制 ?提供塑料TO-92和塑料SO-8低轮廓包 ?没 有外部元件 ?输出电压为5.0V，6.2V，8.2V，9.0V，12V，15V连接图 SO-8塑料（M） （窄体） DS007744-2顶视图 8凹凸 微型SMD DS007744-24顶视图 （凹凸面朝下） （TO-92）塑料包装（Z） DS007744-3底视图微型SMD标记方向 DS007744-33顶视图 可用性和规格.功耗（注5）内部限制输入电压 35V储存温度 -65?C至+150?C工作结温 SO-8 0?C至125?C微型SMD -40?C至 85?C焊接信息红外或对流（20秒） 235C波峰焊接（10秒） 260?C（提前期） ESD敏感度（注2）千伏 LM78LXX电气特性 标准字体的限制是T J =25?C，粗体字ap- SO-8封装的工作温度范围为0?C至125?C，微型SMD封装的工作温度范围为-40?C 至85?C.限制由产品保证，使用标准的统计质量控制（SQC）方法进行测试或相关技术.除非另有说明：I ? = 40毫安，C I =0.33μF，C0 =0.1μF. LM78L05除非另有规定，V IN = 10V符号参数条件敏典型马克斯单位 V ?输出电压 4.8五 5.2 V 7V ≤V IN≤20V 1毫安 ≤我 O≤40 mA （注3） 4.75 5.25 1毫安 ≤我 O≤70 mA （注3） 4.75 5.25 ΔV ?线路调整 7V ≤V IN≤20V 18 75毫伏 8V ≤V IN≤20V 10 54 ΔV ?负载调节 1毫安 ≤我 O≤100 mA 20 60 1毫安 ≤我 O≤40 mA五三十一世 Q 静态电流 3五 ΔI Q静态电流变化 8V ≤V IN≤20V 1.0 1毫安 ≤我 O≤40 mA 0.1 V ?输出噪声电压 f = 10Hz至100kHz （注 4） 40 μV波纹拒绝 f = 120Hz 8V ≤V IN≤16V 47 62 D b一世 PK峰值输出电流 140嘛平均输出电压温度系数一世 O = 5mA -0.65毫伏/℃ V IN （小）输入电压的小值保持线路规定所需 6.7 7 V θ JA热阻 （8凹凸微型SMD） 230.9 C / W LM78L62AC除非另有规定，V IN = 12V符号参数条件敏典型马克斯单位 V ?输出电压 5.95 .2 6.45 V 8.5V ≤V IN≤20V 1毫 安 ≤我 O≤40 mA （注3） 5.9 6.5 1毫安 ≤我 O≤70 mA （注3） 5.9 6

Wirewound Resistors, Precision Power, Low Value,Commercial, Military, MIL-PRF-49465 Type RLV , Axial LeadLVRVishay Dale For technical questions, contact: ww2aresistors@Document Number: 30206152Revision: 29-Feb-08FEATURES•Ideal for all types of current sensing applications including switching and linear power supplies,instruments and power amplifiers•Proprietary processing technique produces extremely low resistance values •Excellent load life stability •Low temperature coefficient •Low inductance•Cooler operation for high power to size ratioNotes(1)Resistance is measured 3/8" [9.52 mm] from the body of the resistor, or at 1.183" [30.05 mm], 1.315" [33.40 mm], 1.675" [42.545 mm] or 2.575" [65.405 mm] spacing for the LVR01, LVR03, LVR05 and LVR10 respectively(2)Standard resistance values are 0.01 Ω, 0.015 Ω, 0.02 Ω, 0.025 Ω, 0.03 Ω, 0.033 Ω, 0.04 Ω, 0.05 Ω, 0.051 Ω, 0.06 Ω, 0.068 Ω, 0.07 Ω, 0.08 Ω,0.09 Ω and 0.1 Ω with 1 % tolerance. Other resistance values may be available upon request* Pb containing terminations are not RoHS compliant, exemptions may apply STANDARD ELECTRICAL SPECIFICATIONSGLOBAL MODEL HISTORICAL MODEL MIL-PRF-49465TYPE POWER RATING P 25 °C W RESISTANCE RANGE Ω (1)± 1 %, ± 3 %, ± 5 %, ± 10 %TECHNOLOGYLVR01LVR-1-10.01 - 0.1 (2)Metal Strip LVR03LVR-3-30.005 - 0.2Metal Strip LVR03...26LVR-3-26RLV30 (M4946506)30.01 - 0.2Metal Strip LVR05LVR-5-50.005 - 0.3Metal Strip LVR05...26LVR-5-26RLV31 (M4946507)50.01 - 0.3Metal Strip LVR10LVR-10-100.01 - 0.8Coil Spacewound TECHNICAL SPECIFICATIONSPARAMETERUNIT LVR01LVR03LVR05LVR10Rated Power at + 25 °CW 13510Operating Temperature Range °C - 65 to + 175- 65 to + 275Dielectric Withstanding Voltage V AC 1000100010001000Insulation Resistance Ω10 000 M Ω minimum dryShort Time Overload- 5 x rated power for 5 s 10 x rated power for 5 sTerminal Strength (minimum)lb 5101010Temperature Coefficient ppm/°C See TCR vs. Resistance Value chartMaximum Working Voltage V (P x R )1/2Weight (maximum)g22511GLOBAL PART NUMBER INFORMATIONNew Global Part Numbering: LVR055L000FS73 (preferred part number format)GLOBAL MODELVALUETOLERANCE PACKAGINGSPECIAL LVR01LVR03LVR05LVR10R = Decimal L = m Ω(values < 0.010 Ω)R1500 = 0.15 Ω7L000 = 0.007 ΩD = ± 0.5 %F = ± 1.0 %G = ± 2.0 %H = ± 3.0 %J = ± 5.0 %K = ± 10.0 %E12 = Lead (Pb)-free bulkE03 = Lead (Pb)-free lacer pack (LVR10)E70 = Lead (Pb)-free, tape/reel 1000 pieces (LVR01, 03)E73 = Lead (Pb)-free, tape/reel 500 pieces (Dash Number)(up to 3 digits)From 1 - 999as applicableB12 = Tin/lead bulkL03 = Tin/lead lacer pack (LVR10)S70 = Tin/lead, tape/reel 1000 pieces (LVR01, 03)S73 = Tin/lead, tape/reel 500 piecesHistorical Part Number Example: LVR-50.005 Ω 1 %S73 (will continue to be accepted for tin/lead product only)LVR-50.005 Ω1 %S73HISTORICAL MODELRESISTANCE VALUETOLERANCE CODEPACKAGING V R 055L000F S73LLVRWirewound Resistors, Precision Power, Low Value,Commercial, Military, MIL-PRF-49465 Type RLV, Axial LeadVishay DaleDocument Number: 30206For technical questions, contact: ww2aresistors@Revision: 29-Feb-08153DIMENSIONS in inches [millimeters]Note(1) On some standard reel pack methods, the leads may be trimmed to a shorter length than shownMATERIAL SPECIFICATIONSElement: Self-supporting nickel-chrome alloy (LVR10 also utilizes manganin)Encapsulation: High temperature mold compound Terminals: Tinned copperPart Marking: DALE, model, wattage, value, tolerance,date codeThe improved TCR characteristics of these LVR models from - 55 °C to + 125 °C (reference to + 25 °C) are as follows:MODEL DIMENSIONS in inches [millimeters]A ± 0.010 [0.254]B ± 0.010 [0.254]C± 0.002 [0.051]LVR010.427 [10.85]0.115 [2.92]0.020 [0.508]LVR030.560 [14.22]0.205 [5.21]0.032 [0.813]LVR050.925 [23.50]0.330 [8.38]0.040 [1.02]LVR101.828 [46.43]0.392 [9.96]0.040 [1.02]PERFORMANCETESTCONDITIONS OF TESTTEST LIMITS Thermal Shock - 65 °C to + 125 °C, 5 cycles, 15 min at each extrem± (0.2 % + 0.0005 Ω) ΔR Short Time Overload 5 x rated power (LVR01, 03, 05), 10 x rated power (LVR10) for 5 s ± (0.5 % + 0.0005 Ω) ΔR Low Temperature Storage - 65 °C for 24 h± (0.2 % + 0.0005 Ω) ΔR High T emperature Exposure 250 h at + 275 °C (+ 175 °C for LVR01)± (2.0 % + 0.0005 Ω) ΔR Dielectric Withstanding Voltage 1000 V rms , 1 min± (0.1 % + 0.0005 Ω) ΔR Insulation Resistance MIL-STD-202 Method 302, 100 V1000 M Ω minimum Moisture Resistance MIL-STD-202 Method 106, 100 7b not applicable ± (0.2 % + 0.0005 Ω) ΔR Shock, Specified Pulse MIL-STD-202 Method 213, 100 g's for 6 ms, 10 shocks± (0.1 % + 0.0005 Ω) ΔR Vibration, High Frequency Frequency varied 10 to 2000 Hz, 20 g peak, 2 directions 6 h each ± (0.1 % + 0.0005 Ω) ΔR Load Life 2000 h at rated power, + 25 °C, 1.5 h “ON”, 0.5 h “OFF”± (2.0 % + 0.0005 Ω) ΔRSolderability ANSI J-STD-00295 % coverage Bias Humidity+ 85 °C, 85 % RH, 10 % bias, 1000 h± (1.0 % + 0.0005 Ω) ΔRDocument Number: 91000Revision: 18-Jul-081DisclaimerLegal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。