DAC6573IPWG4中文资料

STM32F10xxx参考手册 参考手册 小，中和大容量的STM32F101xx, STM32F102xx和STM32F103xx ARM内核32位高性能微控制器 导言 本参考手册针对应用开发，提供关于如何使用小容量、中容量和大容量的STM32F101xx、STM32F102xx或者STM32F103xx微控制器的存储器和外设的详细信息。在本参考手册中STM32F101xx、STM32F102xx和STM32F103xx被统称为STM32F10xxx。 STM32F10xxx系列拥有不同的存储器容量，封装和外设配置。 关于订货编号、电气和物理性能参数，请参考STM32F101xx、STM32F102xx和STM32F103xx的数据手册。 关于芯片内部闪存的编程，擦除和保护操作，请参考STM32F10xxx闪存编程手册。 关于ARM Cortex™-M3内核的具体信息，请参考Cortex™-M3技术参考手册。 相关文档 ● Cortex™-M3技术参考手册，可按下述链接下载： /help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf 下述文档可在ST网站下载(/mcu/)： ● STM32F101xx、STM32F102xx和STM32F103xx的数据手册。 ● STM32F10xxx闪存编程手册。 * 感谢南京万利提供原始翻译文档 参照2008年12月 RM0008 Reference Manual 英文第7版 本译文仅供参考，如有翻译错误，请以英文原稿为准。请读者随时注意在ST网站下载更新版本 目录 STM32F10xxx参考手册

2/524 参照2008年12月 RM0008 Reference Manual 英文第7版 本译文仅供参考，如有翻译错误，请以英文原稿为准。请读者随时注意在ST网站下载更新版本 目录 1 文中的缩写 16 1.1 寄存器描述表中使用的缩写列表 16 1.2 术语表 16 1.3 可用的外设 16 2 存储器和总线构架 17 2.1 系统构架 17 2.2 存储器组织 18 2.3 存储器映像 19 2.3.1 嵌入式SRAM 20 2.3.2 位段 20 2.3.3 嵌入式闪存 21 2.4 启动配置 23 3 CRC计算单元(CRC) 25 3.1 CRC简介 25 3.2 CRC主要特性 25 3.3 CRC功能描述 25 3.4 CRC寄存器 26 3.4.1 数据寄存器(CRC_DR) 26 3.4.2 独立数据寄存器(CRC_IDR) 26 3.4.3 控制寄存器(CRC_CR) 27 3.4.4 CRC寄存器映像 27 4 电源控制(PWR) 28 4.1 电源 28 4.1.1 独立的A/D转换器供电和参考电压 28 4.1.2 电池备份区域 29 4.1.3 电压调节器 29 4.2 电源管理器 29 4.2.1 上电复位(POR)和掉电复位(PDR) 29 4.2.2 可编程电压监测器(PVD) 30 4.3 低功耗模式 30 4.3.1 降低系统时钟 31 4.3.2 外部时钟的控制 31 4.3.3 睡眠模式 31 4.3.4 停止模式 32 4.3.5 待机模式 33 4.3.6 低功耗模式下的自动唤醒(AWU) 34 4.4 电源控制寄存器 35 4.4.1 电源控制寄存器(PWR_CR) 35 4.4.2 电源控制/状态寄存器 36 4.4.3 PWR寄存器地址映像 37 5 备份寄存器(BKP) 38 5.1 BKP简介 38 5.2 BKP特性 38

D2253UK

Prelim. 9/00Semelab plc.Telephone +44(0)1455 556565. Fax +44(0)1455 552612.E-mail: sales@Website: PDPower DissipationBVDSSDrain – Source Breakdown Voltage *BVGSSGate – Source Breakdown Voltage *ID(sat)Drain Current *TstgStorage TemperatureTjMaximum Operating Junction Temperature15W40V±20V2A–65 to 150°C200°CMECHANICAL DATAGOLD METALLISED

MULTI-PURPOSE SILICON

DMOS RF FET

5W – 12.5V – 1GHz

PUSH–PULL

FEATURES

•SIMPLIFIED AMPLIFIER DESIGN

•SUITABLE FOR BROAD BAND APPLICATIONS

•VERY LOW Crss•SIMPLE BIAS CIRCUITS

•LOW NOISE

• HIGH GAIN – 10 dB MINIMUM

ABSOLUTE MAXIMUM RATINGS (Tcase= 25°C unlessotherwise stated)APPLICATIONS

•VHF/UHF COMMUNICATIONSfrom 1MHz to 1 GHzMETAL GATE RF SILICON FETTetraFET

* Per SidePIN 1 Source (Common)PIN 2 Drain 1PIN 3 Drain 2PIN 4 Source (Common)PIN 5 Source (Common)PIN 6 Gate 2PIN 7 Gate 1PIN 8 Source (Common)DBC4 Package

Appendix

Appendix1-Rev1.1

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Arria II Device Architecture

■Diagnostic features

■Serial loopback from the transmitter serializer to the receiver CDR for

transceiver physical coding sublayer (PCS) and PMA diagnostics

■Parallel loopback from the transmitter PCS to the receiver PCS with built-in self

test (BIST) pattern generator and verifier

■Reverse serial loopback pre- and post-CDR to transmitter buffer for physical

link diagnostics

■Loopback master and slave capability in PCIe hard IP blocks

■Support for protocol features such as MSB-to-LSB transmission in a

SONET/SDH configuration and spread-spectrum clocking in a PCIe

configuration

Table1–5 lists common protocols and the ArriaII dedicated circuitry and features for

implementing these protocols.

1For other protocols supported by ArriaII devices, such as SONET/SDH, SDI, SATA

and SRIO, refer to the Transceiver Architecture in Arria II Devices chapter.Table1–5.Sample of Supported Protocols and Feature Descriptions for Arria II DevicesSupported ProtocolsFeature Descriptions