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DAC121S101WGRQV中文资料

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August 14, 2008 DAC121S101QML12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail OutputGeneral DescriptionThe DAC121S101 is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) that can op-erate from a single +2.7 V to 5.5 V supply and consumes just 177 µA of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface op-erates at clock rates up to 20 MHz over the specified supply voltage range and is compatible with standard SPI™, QSPI, MICROWIRE and DSP interfaces.The supply voltage for the DAC121S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.The low power consumption and small packages of the DAC121S101 make it an excellent choice for use in battery operated equipment.The DAC121S101 operates over the extended temperature range of -55°C to +125°C.Features■Guaranteed Monotonicity■Low Power Operation■Rail-to-Rail Voltage Output■Power-on Reset to Zero Volts Output■SYNC Interrupt Facility■Wide power supply range (+2.7 V to +5.5 V)■Small Packages■Power Down FeatureKey Specifications■Resolution12 bits ■DNL+0.21, -0.10 LSB (typ)■Output Settling Time12.5 µs (typ)■Zero Code Error 2.1 mV (typ)■Full-Scale Error−0.04 %FS (typ)■Power Dissipation—Normal Mode0.52 mW (3.6 V) / 1.19 mW (5.5 V) typ —Pwr DownMode0.014 µW (3.6 V) / 0.033 µW (5.5 V) typ ■Total Ionizing Dose100 krad(Si)■Single Event Latch-up120 MeV-cm2/mg Applications■Battery-Powered Instruments■Digital Gain and Offset Adjustment■Programmable Voltage & Current Sources■Programmable AttenuatorsOrdering InformationNS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION DAC121S101WGMLS WG10A10LD Ceramic SOICDAC121S101WGRQV(Note 11)TBD WG10A10LD Ceramic SOICSPI™ is a trademark of Motorola, Inc.© 2008 National Semiconductor DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail OutputConnection Diagrams10LD Ceramic SOIC30018001Top ViewSee NS Package Number WG10ABlock Diagram30018003 2D A C 121S 101Q M LAbsolute Maximum Ratings(Notes 1, 2)Supply Voltage, VA6.5 VVoltage on any Input Pin−0.3 V to (VA+ 0.3 V) Input Current at Any Pin (Note 3)10 mA Maximum Output Current (Note 10)10 mAVOUTPin in Powerdown Mode 1.0 mA Package Input Current (Note 3)20 mAPower Dissipation at TA= 25°C See (Note 4) Maximum Junction Temperature175°C Lead TemperatureCeramic SOIC(Soldering 10 Seconds)260°C Storage Temperature−65°C to +150°C Package Weight (Typical)Ceramic SOIC220 mg ESD Tolerance (Note 5)Class 3A (5000 V)Operating Ratings (Notes 1, 2)Operating Temperature Range−55°C to +125°C Supply Voltage, VA+2.7 V to 5.5 VAny Input Voltage (Note 6)−0.1 V to (VA+ 0.1 V) Output Load0 to 1500 pF SCLK Frequency Up to 20 MHz Package Thermal ResistancePackageθJA(Still Air)θJC10-lead Ceramic SOICPackage on 2 layer, 1oz.PCB214°C/W25.7°C/WQuality Conformance InspectionMIL-STD-883, Method 5005 - Group ASubgroup Description Temp (° C)1Static tests at+252Static tests at+1253Static tests at-554Dynamic tests at+255Dynamic tests at+1256Dynamic tests at-557Functional tests at+258A Functional tests at+1258B Functional tests at-559Switching tests at+2510Switching tests at+12511Switching tests at-5512Setting time at+2513Setting time at+12514Setting time at-55DAC121S101QMLDAC121S101 Electrical Characteristics DC ParametersThe following specifications apply for V A = +2.7 V to +5.5 V, R L = ∞, C L = 200 pF to GND, f SCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ T A ≤ T MAX : all other limits T A = 25°C, unless otherwise specified.SymbolParameterConditionsNotesTypical (Note 8)MinMaxUnitsSub-groupsSTATIC PERFORMANCEResolution (Note 9) 12 Bits Monotonicity(Note 9) 12 Bits INL Integral Non-Linearity Over Decimal codes 48 to 4047 ±2.75−8.08.0LSB 1, 2, 3DNL Differential Non-Linearity V A = 2.7 V to 5.5 V +0.21 +1.0LSB 1, 2, 3−0.10−0.7 LSB 1, 2, 3ZE Zero Code Error I OUT = 0 +2.12 +15mV 1, 2, 3FSE Full-Scale Error I OUT = 0−0.04 −1.0%FSR 1, 2, 3GE Gain ErrorAll ones Loaded to DAC register −0.11 ±1.0%FSR 1, 2, 3ZCED Zero Code Error Drift (Note 9)−20µV/°C TC GEGain Error TempcoV A = 3 V (Note 9)−0.7 ppm/°C V A = 5 V−1.0ppm/°COUTPUT CHARACTERISTICSIPD SINKVout Pin in Powerdown ModeAll PD Modes (Note 9) 1.0mAOutput Voltage Range(Note 9) 0V A V ZCO Zero Code OutputV A = 3 V, I OUT = 10 µA2.0 6mV 1, 2, 3V A = 3 V, I OUT = 100 µA 4 10mV 1, 2, 3V A = 5 V, I OUT = 10 µA 2 8mV 1, 2, 3V A = 5 V, I OUT = 100 µA 4 9mV 1, 2, 3FSO Full Scale OutputV A = 3 V, I OUT = 10 µA 2.997 2.990 V 1, 2, 3V A = 3 V, I OUT = 100 µA 2.991 2.985 V 1, 2, 3V A = 5 V, I OUT = 10 µA 4.994 4.985 V 1, 2, 3V A = 5 V, I OUT = 100 µA 4.992 4.985 V 1, 2, 3 Maximum Load CapacitanceR L = ∞(Note 9)1500 pF R L = 2 k Ω1500 pFDC Output Impedance816Ω1, 2, 3 4D A C 121S 101Q M LDC Parameters (Continued)The following specifications apply for V A = +2.7 V to +5.5 V, R L = ∞, C L = 200 pF to GND, f SCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ T A ≤ T MAX : all other limits T A = 25°C, unless otherwise specified.Symbol ParameterConditionsNotesTypical (Note 8)MinMaxUnitsSub-groupsLOGIC INPUTI IN Input Current 6−200+200nA 1, 2, 3V IL Input Low Voltage V A = 5 V0.8V 1, 2, 3V A = 3 V0.5V 1, 2, 3V IH Input High Voltage V A = 5 V 2.4 V 1, 2, 3V A = 3 V 2.1 V 1, 2, 3C INInput Capacitance(Note 9)5pFPOWER REQUIREMENTSI ASupply Current (output unloaded)Normal Mode f SCLK = 20 MHz 5.5 V 216 270µA 1, 2, 33.6 V 145 200µA 1, 2, 3Normal Mode f SCLK = 10 MHz5.5 V 185 230µA 1, 2, 33.6 V 132 175µA 1, 2, 3Normal Mode f SCLK = 0 5.5 V 150 190µA 1, 2, 33.6 V 115 160µA 1, 2, 3All PD Modes,f SCLK = 20 MHz 5.5 V 22 60µA 1, 2, 33.6 V 12 30µA 1, 2, 3All PD Modes,f SCLK = 10 MHz 5.5 V 12 40µA 1, 2, 33.6 V 6 20µA 1, 2, 3All PD Modes,f SCLK = 0 5.5 V .006 1.0µA 1, 2, 33.6 V .004 1.0µA 1, 2, 3P CPower Consumption (output unloaded)Normal Mode f SCLK = 20 MHz 5.5 V (Note 9) 1.19 1.49mW 3.6 V 0.52 .72mW Normal Mode f SCLK = 10 MHz5.5 V (Note 9) 1.02 1.27mW 3.6 V 0.47 .63mW Normal Modef SCLK = 0 5.5 V (Note 9)0.82 1.05mW 3.6 V 0.41 .58mW All PD Modes,f SCLK = 20 MHz 5.5 V (Note 9)0.12 .33mW 3.6 V 0.07 .11mW All PD Modes,f SCLK = 10 MHz 5.5 V (Note 9)0.04 .22mW 3.6 V 0.02 .08mW All PD Modes,f SCLK = 05.5 V (Note 9)0.033 5.5µW 3.6 V0.014 3.6µW I OUT / I APower EfficiencyI LOAD = 2 mA(Note 9)91 % 94%DAC121S101QMLAC and Timing CharacteristicsThe following specifications apply for V A = +2.7 V to +5.5 V, R L = ∞, C L = 200 pF to GND, f SCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for T MIN ≤ T A ≤ T MAX : all other limits T A = 25°C, unless otherwise specified.Symbol ParameterConductionsNotes Typical (Note 8)Min Max Units Sub-groupsf SCLKSCLK Frequency(Note 9) 20MHz t sOutput Voltage Settling TimeFF0 to 00F codechange, R L = ∞C L ≤ 200 pF12.5 15µs 9, 10, 11C L = 500 pF12.5 15µs 9, 10, 1100Fh to FF0h code change, R L = ∞C L ≤ 200 pF 12.5 15µs 9, 10, 11C L = 500 pF12.5 15µs 9, 10, 11SR Output Slew Rate(Note 9)1 V/µs Glitch Impulse Code change from 800h to 7FFh (Note 9)12 nV-sec Digital Feedthrough (Note 9)0.5 nV-sec t WU Wake-Up Time V A = 5 V (Note 9).65 µs V A = 3 V 1.1 µs 1/f SCLK SCLK Cycle Time 50 ns 9, 10, 11t H SCLK High time 10 20ns 9, 10, 11t L SCLK Low Time10 20ns 9, 10, 11t SUCL Set-up Time SYNC to SCLKRising Edge−18−21 ns 9, 10, 11t SUD Data Set-Up Time 5 6ns 9, 10, 11t DHD Data Hold Time3 4.5ns 9, 10, 11t CS SCLK fall to rise of SYNC V A = 5.5 V 6 10ns 9, 10, 11V A = 2.7 V 11 18ns 9, 10, 11t SYNCSYNC High TimeV A = 5.5 V 33 37ns 9, 10, 11V A = 2.7 V3436ns9, 10, 11 6D A C 121S 101Q M LRadiation Electrical Characteristics (Note 11)The following specifications apply for VA = +2.7 V to +5.5 V, RL= ∞, C L = 200 pF to GND, f SCLK = 20 MHz, input code range 48 to4047.Symbol Parameter Conditions Notes Typical(Note 8)Min Max UnitsSub-groupsPOWER REQUIREMENTSI A Supply Current (outputunloaded)Normal ModefSCLK= 20 MHz5.5 V216325µA13.6 V145250µA1Normal ModefSCLK= 10 MHz5.5 V185300µA13.6 V132225µA1Normal ModefSCLK= 05.5 V150275µA13.6 V115200µA1All PD Modes,fSCLK= 20 MHz5.5 V22125µA13.6 V12100µA1All PD Modes,fSCLK= 10 MHz5.5 V12115µA13.6 V695µA1All PD Modes,fSCLK= 05.5 V.006100µA13.6 V.004100µA1Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note 2:All voltages are measured with respect to GND = 0 V, unless otherwise specifiedNote 3:When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA ), the current at that pin should be limited to 10mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.Note 4:The absolute maximum junction temperature (TJ max) for this device is 175°C. The maximum allowable power dissipation is dictated by TJmax, thejunction-to-ambient thermal resistance (θJA ), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The valuesfor maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.Note 5:Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.Note 6:The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VAis 2.7 VDC, ensure that−100 mV ≤ input voltages ≤2.8 V DC to ensure accurate conversions.30018004Note 7:To guarantee accuracy, it is required that VAbe well bypassed.Note 8:Typical figures are at TJ= 25°C, and represent most likely parametric norms.Note 9:This parameter is guaranteed by design and/or characterization and is not tested in production.Note 10:Maximum Output Current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 Ω, (360 Ω at VDD= 3.6V).Note 11:Pre and post irradiation limits are identical to those listed in the “DC Parameters” and “AC and Timing Characteristics” tables, except as listed in the “Radiation Electrical Characteristics” table. When performing post irradiation electrical measurements for any RHA level, TA= +25°C. DAC121S101QMLSpecification DefinitionsDIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB,which is V REF / 4096 = V A / 4096.DIGITAL FEEDTHROUGH is a measure of the energy inject-ed into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of V A x 4095 / 4096.GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.GLITCH IMPULSE is the energy injected into the analog out-put when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds.INTEGRAL NON-LINEARITY (INL) is a measure of the de-viation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables.LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-est value or weight of all bits in a word. This value isLSB = V REF / 2nwhere V REF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC121S101.MAXIMUM LOAD CAPACITANCE is the maximum capaci-tance that can be driven by the DAC with output stability maintained.MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases.MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of V A .POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output cur-rents is the power consumed by the device without a load.SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated.WAKE-UP TIME is the time for the output to exit power-down mode. This is the time measured from the falling edge of 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. 8D A C 121S 101Q M LTransfer Characteristic30018005FIGURE 1. Input / Output Transfer CharacteristicTiming Diagram30018006FIGURE 2. DAC121S101 Timing DAC121S101QMLTypical Performance Characteristicsf SCLK = 20 MHz, T A = 25C, Input Code Range 48 to 4047, unlessotherwise statedDNL at V A = 2.7V30018052DNL at V A = 5.5V30018053INL at V A = 2.7V 30018054INL at V A = 5.5V30018055DNL vs. V A 30018022INL vs. V A30018023 10D A C 121S 101Q M L2.7V DNL vs. f SCLK30018050 5.5V DNL vs. f SCLK300180512.7V DNL vs. Clock Duty Cycle 30018056 5.5V DNL vs. Clock Duty Cycle300180572.7V DNL vs. Temperature 30018026 5.5V DNL vs. Temperature30018027DAC121S101QML2.7V INL vs. f SCLK30018028 5.5V INL vs. f SCLK300180292.7V INL vs. Clock Duty Cycle 30018030 5.5V INL vs. Clock Duty Cycle300180312.7V INL vs. Temperature 30018032 5.5V INL vs. Temperature30018033 12D A C 121S 101Q M LZero Code Error vs. fSCLK30018034Zero Code Error vs. Temperature30018036Full-Scale Error vs. fSCLK30018037Full-Scale Error vs. Temperature30018039Supply Current vs. VA30018044Supply Current vs. Temperature30018045DAC121S101QML5V Glitch Response30018046Power-On Reset300180473V Wake-Up Time 300180485V Wake-Up Time30018049 14D A C 121S 101Q M L1.0 Functional Description1.1 DAC SECTIONThe DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of:V OUT = V A x (D / 4096)where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value be-tween 0 and 4095.1.2 RESISTOR STRINGThe simplified resistor string is shown in Figure 3. Conceptu-ally, this string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration guarantees that the DAC is monotonic.30018007FIGURE 3. DAC Resistor String1.3 OUTPUT AMPLIFIERThe output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to V A . All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V A , in this case). For this reason,linearity is specified over less than the full output range of the DAC. The output capabilities of the amplifier are described in the Electrical Tables.1.4 SERIAL INTERFACEThe three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagram for information on a write sequence.A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high. In eithercase, it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can initiate the next write cycle.Since the SYNC and D IN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption.1.5 INPUT SHIFT REGISTERThe input shift register, Figure 4, has sixteen bits. The first two bits are "don't cares" and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2.30018008FIGURE 4. Input Register ContentsNormally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the output voltage.1.6 POWER-ON RESETThe power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC.1.7 POWER-DOWN MODESThe DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register.TABLE 1. Modes of OperationDB13DB12 Operating Mode 00Normal Operation01Power-Down with 5k Ω to GND 10Power-Down with 100k Ω to GND 11Power-Down with Hi-ZWhen both DB13 and DB12 are 0, the device operates nor-mally. For the other three possible combinations of these bits the supply current drops to its power-down level and the out-put is pulled down with either a 5k Ω or a 100k Ω resistor, or is in a high impedance state, as described in Table 1.The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC register are unaffected when in power-down, so when coming out of pow-er down the output voltage returns to the same voltage it was before entering power down. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and D IN idled low.15DAC121S101QML2.0 Applications InformationThe simplicity of the DAC121S101 implies ease of use. How-ever, it is important to recognize that any data converter thatutilizes its supply voltage as its reference voltage will haveessentially zero PSRR (Power Supply Rejection Ratio).Therefore, it is necessary to provide a noise-free supply volt-age to the device.2.1 DSP/MICROPROCESSOR INTERFACINGInterfacing the DAC121S101 to microprocessors and DSPsis quite simple. The following guidelines are offered to hastenthe design process.2.1.1 ADSP-2101/ADSP2103 InterfacingFigure 5 shows a serial interface between the DAC121S101and the ADSP-2101/ADSP2103. The DSP should be set tooperate in the SPORT Transmit Alternate Framing Mode. It isprogrammed through the SPORT control register and shouldbe configured for Internal Clock Operation, Active Low Fram-ing and 16-bit Word Length. Transmission is started by writinga word to the Tx register after the SPORT mode has beenenabled.30018009FIGURE 5. ADSP-2101/2103 Interface2.1.2 80C51/80L51 InterfaceA serial interface between the DAC121S101 and the80C51/80L51 microcontroller is shown in Figure 6. TheSYNC signal comes from a bit-programmable pin on the mi-crocontroller. The example shown here uses port line P3.3.This line is taken low when data is to transmitted to theDAC121S101. Since the 80C51/80L51 transmits 8-bit bytes,only eight falling clock edges occur in the transmit cycle. Toload data into the DAC, the P3.3 line must be left low after thefirst eight bits are transmitted. A second write cycle is initiatedto transmit the second byte of data, after which port line P3.3is brought high. The 80C51/80L51 transmit routine must rec-ognize that the 80C51/80L51 transmits data with the LSB firstwhile the DAC121S101 requires data with the MSB first.30018010FIGURE 6. 80C51/80L51 Interface2.1.3 68HC11 InterfaceA serial interface between the DAC121S101 and the 68HC11microcontroller is shown in Figure 7. The SYNC line of theDAC121S101 is driven from a port line (PC7 in the figure),similar to the 80C51/80L51.The 68HC11 should be configured with its CPOL bit as a zeroand its CPHA bit as a one. This configuration causes data onthe MOSI output to be valid on the falling edge of SCLK. PC7is taken low to transmit data to the DAC. The 68HC11 trans-mits data in 8-bit bytes with eight falling clock edges. Data istransmitted with the MSB first. PC7 must remain low after thefirst eight bits are transferred. A second write cycle is initiatedto transmit the second byte of data to the DAC, after whichPC7 should be raised to end the write sequence.30018011FIGURE 7. 68HC11 Interface2.1.4 Microwire InterfaceFigure 8 shows an interface between a Microwire compatibledevice and the DAC121S101. Data is clocked out on the risingedges of the SCLK signal.30018012FIGURE 8. Microwire Interface2.2 USING REFERENCES AS POWER SUPPLIESRecall the need for a quiet supply source for devices that usetheir power supply voltage as a reference voltage.Since the DAC121S101 consumes very little power, a refer-ence source may be used as the supply voltage. The advan-tages of using a reference source over a voltage regulator areaccuracy and stability. Some low noise regulators can also beused for the power supply of the DAC121S101. Listed beloware a few power supply options for the DAC121S101.2.2.1 LM4130The LM4130 reference, with its 0.05% accuracy over tem-perature, is a good choice as a power source for theDAC121S101. Its primary disadvantage is the lack of 3 V and5 V versions. However, the 4.096 V version is useful if a 0 to4.095 V output range is desirable or acceptable. Bypassingthe LM4130 VIN pin with a 0.1 µF capacitor and the VOUTpin with a 2.2 µF capacitor will improve stability and reduceoutput noise. The LM4130 comes in a space-saving 5-pinSOT23.30018013FIGURE 9. The LM4130 as a power supply 16DAC121S11QML2.2.2 LM4050Available with accuracy of 0.44%, the LM4050 shunt refer-ence is also a good choice as a power regulator for the DAC121S101. It does not come in a 3 Volt version, but 4.096V and 5 V versions are available. It comes in a space-saving 3-pin SOT23.30018014FIGURE 10. The LM4050 as a power supplyThe minimum resistor value in the circuit of Figure 10 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum,the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC121S101 draws zero current. The maximum resistor value must allow the LM4050to draw more than its minimum current for regulation plus the maximum DAC121S101 current in full operation. The condi-tions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC121S101draws its maximum current. These conditions can be sum-marized asR(min) = ( V IN (max) − V Z (min) / (I A (min) + I Z (max))andR(max) = ( V IN (min) − V Z (max) / (I A (max) + I Z (min) )where V Z (min) and V Z (max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature, I Z (max) is the maximum allowable current through the LM4050,I Z (min) is the minimum current required by the LM4050 for proper regulation, I A (max) is the maximum DAC121S101 sup-ply current, and I A (min) is the minimum DAC121S101 supply current.2.2.3 LP3985The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC121S101. It comes in 3.0V, 3.3V and 5V versions, among others, and sports a low 30 µV noise specification at low fre-quencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applica-tions. The LP3985 comes in a space-saving 5-pin SOT23 and 5-bump micro SMD packages.30018015FIGURE 11. Using the LP3985 regulatorAn input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic ca-pacitor with an ESR requirement of 5m Ω to 500m Ω is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation.2.2.4 LP2980The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others.30018016FIGURE 12. Using the LP2980 regulatorLike any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet.Surface-mount solid tantalum capacitors offer a good combi-nation of small size and ESR. Ceramic capacitors are attrac-tive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low tem-peratures.2.3 BIPOLAR OPERATIONThe DAC121S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 13. This circuit will provide an output voltage range of ±5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.DAC121S101QML。

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数据手册中文版

数据手册中文版

14位, 165M SPA（采样率）DAC（数模转换器）特性：●单电源供电+5V或+3V●高SFDR （无杂散动态范围）: 在100MSPS 64dBc时20MHz输出●低干扰: 3PV -S●低功耗: 170MW （+5 V时）应用●通讯传输通道WLL , 蜂窝基站数字微波链路电缆调制解调器●波形产生直接数字频率合成器（DDS ）任意波形发生器（ARB ）●医疗/超声●高速仪表和控制●视频, 数字电视说明：DAC904是一款高速数模转换器, 14位分辨率, 引脚兼容DAC908、DAC900、DAC902, 分别提供8-, 10-, 12-位分辨率选择。

该系列DAC支持的所有型号更新率超过165MSPS, 具有优良的动态性能。

DAC904先进分割架构的优化为单音和多频音信号提供高无杂散动态范围（SFDR）, 特别是用于通信系统的发送信号电路时。

DAC904具有高阻抗（200KΩ）的电流输出, 标称范围为20mA和一个最多为1.25V的输出。

差分输出允许两个差分或单端模拟信号的接口。

电流输出的匹配保证在差分结构中杰出的动态性能, 它可以与变压器配合使用。

运用一个小的几何CMOS工艺, 单片DAC904可以用在+2.7 V至+5.5 V宽的单电源范围内操作。

其低功耗特性允许它使用在便携式和电池供电系统情况下。

可通过减少输出电流与调整满量程选项实现进一步优化。

DAC904不断运转时, 掉电模式导致其待机功率仅为为45mW 。

DAC904带有一个集成的1.24V带隙基准和边沿触发输入锁存器, 提供完整的转换器解决方案。

+3 V和+5 V CMOS逻辑系列都可以接口到DAC904 。

DAC904的参考结构允许使用芯片上的参考, 或施加外部参考。

通过一个外部电阻, 满量程输出电流可以调整在2 - 20mA, 并保持其指定的动态性能。

DAC904采用SO -28和TSSOP -28封装。

绝对最大额定值+VA到AGND（模拟信号地）......-0.3V至+6V+VD到DGND（数字信号地）......-0.3V到+6VAGND到DGND......-0.3V到+0.3V+VA 到+VD......-6V到+6VCLK, PD到DGND......-0.3V到VD+0.3VD0-D13到DGND......-0.3V到VD+0.3VIOUT, I 到AGND......-1V到VA+0.3VBW,BYP到AGND......-0.3V到VA+0.3VREFIN ,FSA到AGND......-0.3V到VA+0.3VINT/EXT到AGND......-0.3V到VA+0.3V结温度. . . . . . . ＋１５０℃存储器温度. . . . . . ＋１２５℃防静电敏感度这种集成的电路可以被ESD（静电释放）损坏。

DAC解码器选购指南

DAC解码器选购指南

DAC解码器选购指南点评几款DIY的DAC解码器(增加常见dac指标大全)本帖最后由 love957 于 2021-5-13 14:42 编辑在80注册快二年，一直在此下些APE和高清，现在看看80玩DAC的人多了，一时兴起，信手涂鸦:近日时逢寒潮，不便外出之余，终于静下心来把手头的这几个dac装好。

没有多大的感觉，十多年玩pchifi，犹如弹指瞬间，从第一台用YMH724推挑战者一号开始，玩过创新AW64 SB CT 到XIFIDIY过玩过各版1305 1541dac等换过各种甲乙类，甲类，甚至专业类攻放有时在问自已，什么样的声音才是自己需要的，什么样的声音才是适合自已的,什么样的声音才是令自已感动的.初入发烧时，十多年前李楠的一对低频霸主，就觉得气势宏伟的低音是自己完美的追求，随后又被蔡大姐童丽的美妙的人声所征服，刚过而立之年，又觉得淡雅的声音，均衡的三段又正是自已此时静若止水的心境浅写意。

人生何其短。

浮生偷得半日闲.庸者不败最早听到扫把明版的1305是在去年东莞的聚会上，1305dac用9v电池供电，简单声好，是那次聚会的亮点,于是收了块玩玩,不听还好，一听1305DAC，此时我那些珍藏的ymh724 SBLOVE ct4630 xfi等等，全扔到床底下。

一年里明版的1305DAC不断的通过改进线路来改善声音，出了近六个版，我有幸装过他四个版的1305DAC，现在装的是1305终结版。

明版的1305DAC试听的最大特色在于耐听，属于那种不温不火从从容的风格。

玩尽明四个版的1305，有用过用12伏电瓶供电给1305DAC，为什么选用12伏（从台坏的UPS拆下来），因为我试过用9伏干电池和12伏电瓶及电脑开关电源及单12交流供电，个人感觉用9伏干电池供电声音过于柔和，懒洋洋的，单12交流供电像1305刚刚睡醒，声音过于阳刚，三端稳压热到烫手，电脑开关电源供电有噪音，声音干燥，还是12伏电瓶供电不温不火，刚柔并济，适合本人性恪：中庸。

ADC121S101_06中文资料

ADC121S101_06中文资料

ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D ConverterGeneral DescriptionThe ADC121S101is a low-power,single channel CMOS 12-bit analog-to-digital converter with a high-speed serial interface.Unlike the conventional practice of specifying per-formance at a single sample rate only,the ADC121S101is fully specified over a sample rate range of 500ksps to 1Msps.The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit.The output serial data is straight binary,and is compatible with several standards,such as SPI ™,QSPI ™,MICROWIRE,and many common DSP serial interfaces.The ADC121S101operates with a single supply that can range from +2.7V to +5.25V.Normal power consumption using a +3V or +5V supply is 2.0mW and 10mW,respec-tively.The power-down feature reduces the power consump-tion to as low as 2.6µW using a +5V supply.The ADC121S101is packaged in 6-lead LLP and SOT-23packages.Operation over the industrial temperature range of −40˚C to +125˚C is guaranteed.Featuresn Specified over a range of sample rates.n 6-lead LLP and SOT-23packages n Variable power managementn Single power supply with 2.7V -5.25V range nSPI ™/QSPI ™/MICROWIRE/DSP compatibleKey Specificationsn DNL +0.5/−0.3LSB (typ)n INL ±0.40LSB (typ)n SNR72.5dB (typ)nPower Consumption —3V Supply 2.0mW (typ)—5V Supply10mW (typ)Applicationsn Portable Systemsn Remote Data Acquisitionn Instrumentation and Control SystemsPin-Compatible Alternatives by Resolution and SpeedAll devices are fully pin and function compatible.ResolutionSpecified for Sample Rate Range of:50to 200ksps200to 500ksps 500ksps to 1Msps12-bit ADC121S021ADC121S051ADC121S10110-bit ADC101S021ADC101S051ADC101S1018-bitADC081S021ADC081S051ADC081S101Connection Diagram20145005Ordering InformationOrder Code Temperature Range Description Top Mark ADC121S101CISD −40˚C to +125˚C 6-Lead LLP PackageX1C ADC121S101CISDX −40˚C to +125˚C 6-Lead LLP Package,Tape &ReelX1C ADC121S101CIMF −40˚C to +125˚C 6-Lead SOT-23PackageX01C ADC121S101CIMF −40˚C to +125˚C6-Lead SOT-23Package,Tape &ReelX01CADC121S101EVALEvaluation BoardTRI-STATE ®is a trademark of National Semiconductor Corporation QSPI ™and SPI ™are trademarks of Motorola,Inc.April 2006ADC121S101Single Channel,0.5to 1Msps,12-Bit A/D Converter©2006National Semiconductor Corporation Block Diagram20145007Pin Descriptions and Equivalent CircuitsPin No.SymbolDescriptionANALOG I/O3V INAnalog input.This signal can range from 0V to V A .DIGITAL I/O4SCLK Digital clock input.This clock directly controls the conversion and readout processes.5SDATA Digital data output.The output samples are clocked out of this pin on falling edges of the SCLK pin.6CSChip select.On the falling edge of CS,a conversion process begins.POWER SUPPLY1V A Positive supply pin.This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1µF capacitor and a 0.1µF monolithic capacitor located within 1cm of the power pin.2GND The ground return for the supply and signals.PADGNDFor package suffix CISD(X)only,it is recommended that the center pad should be connected to ground.A D C 121S 101 2Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Analog Supply Voltage V A−0.3V to6.5V Voltage on Any Digital Pin to GND−0.3V to6.5V Voltage on Any Analog Pin to GND−0.3V to(V A+0.3V) Input Current at Any Pin(Note3)±10mA Package Input Current(Note3)±20mA Power Consumption at T A=25˚C See(Note4) ESD Susceptibility(Note5)Human Body Model Machine Model 3500V 300VJunction Temperature+150˚C Storage Temperature−65˚C to+150˚C Operating Ratings(Notes1,2)Operating Temperature Range−40˚C≤T A≤+125˚C V A Supply Voltage+2.7V to+5.25V Digital Input Pins Voltage Range(regardless of supply voltage)−0.3V to5.25V Analog Input Pins Voltage Range0V to V A Clock Frequency1MHz to20MHz Sample Rate up to1Msps Package Thermal ResistancePackageθJA6-lead LLP94˚C/W6-lead SOT-23265˚C/WSoldering process must comply with National Semiconduc-tor’s Reflow Temperature Profile specifications.Refer to /packaging.(Note6)ADC121S101Converter Electrical Characteristics(Notes7,9)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsSTATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes V A=+2.7v to+3.6V−40˚C≤T A≤125˚C12BitsINL Integral Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6VSOT-23+0.4±1.0LSB(max)-0.4LSB(min)LLP+0.4+1.0LSB(max)-0.4-1.2LSB(min)T A=125˚CV A=+2.7v to+3.6VSOT-23+1.0LSB(max)-1.1LSB(min)LLP+1.0LSB(max)-1.3LSB(min)DNL Differential Non-Linearity −40˚C≤T A≤+85˚CV A=+2.7V to+3.6V+0.5+1.0LSB(max)−0.3-0.9LSB(min) T A=125˚CV A=+2.7v to+3.6V±1.0LSB(max)V OFF Offset Error −40˚C≤T A≤125˚CV A=+2.7v to+3.6V±0.1±1.2LSB(max)LSB(min)GE Gain Error −40˚C≤T A≤125˚CV A=+2.7to+3.6VSOT-23±0.20±1.2LSB(max)LLP±0.20±1.5LSB(max)DYNAMIC CONVERTER CHARACTERISTICSSINAD Signal-to-Noise Plus Distortion Ratio V A=+2.7to5.25V−40˚C≤T A≤125˚Cf IN=100kHz,−0.02dBFS7270dB(min)SNR Signal-to-Noise Ratio V A=+2.7to5.25V−40˚C≤T A≤+85˚Cf IN=100kHz,−0.02dBFS72.570.8dB(min)V A=+2.7to5.25VT A=+125˚Cf IN=100kHz,−0.02dBFS70.6ADC121S101 3ADC121S101Converter Electrical Characteristics (Notes 7,9)(Continued)The following specifications apply for V A =+2.7V to 5.25V,GND =0V,f SCLK =10MHz to 20MHz,C L =15pF,f SAMPLE =500ksps to 1Msps,unless otherwise noted.Boldface limits apply for T A =-40˚C to +85˚C :all other limits T A =25˚C unless otherwise noted.SymbolParameterConditionsTypicalLimits (Note 9)UnitsDYNAMIC CONVERTER CHARACTERISTICS THD Total Harmonic Distortion V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS −80dB (max)SFDR Spurious-Free Dynamic Range V A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 82dB (min)ENOBEffective Number of BitsV A =+2.7to 5.25Vf IN =100kHz,−0.02dBFS 11.611.3Bits (min)IMDIntermodulation Distortion,Second Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB Intermodulation Distortion,Third Order TermsV A =+5.25Vf a =103.5kHz,f b =113.5kHz −78dB FPBW-3dB Full Power BandwidthV A =+5V 11MHz V A =+3V8MHz ANALOG INPUT CHARACTERISTICS V IN Input Range 0to V AVI DCL DC Leakage Current ±1µA (max)C INAInput CapacitanceTrack Mode 30pF Hold Mode 4pF DIGITAL INPUT CHARACTERISTICS V IH Input High Voltage V A =+5.25V 2.4V (min)V A =+3.6V 2.1V (min)V IL Input Low Voltage V A =+5V 0.8V (max)V A =+3V 0.4V (max)I IN Input CurrentV IN =0V or V A±0.1±1µA (max)C INDDigital Input Capacitance24pF (max)DIGITAL OUTPUT CHARACTERISTICS V OH Output High Voltage I SOURCE =200µA V A −0.07V A −0.2V (min)I SOURCE =1mA V A −0.1V V OL Output Low VoltageI SINK =200µA 0.030.4V (max)I SINK =1mA0.1VI OZH ,I OZL TRI-STATE ®Leakage Current ±0.1±10µA (max)C OUTTRI-STATE ®Output Capacitance 24pF (max)Output CodingStraight (Natural)BinaryPOWER SUPPLY CHARACTERISTICS V ASupply Voltage2.7V (min)5.25V (max)I ASupply Current,Normal Mode (Operational,CS low)V A =+5.25V,f SAMPLE =1Msps 2.0 3.2mA (max)V A =+3.6V,f SAMPLE =1Msps 0.6 1.5mA (max)Supply Current,Shutdown (CS high)f SCLK =0MHz,V A =+5V,f SAMPLE =0ksps500nA f SCLK =20MHz,V A =+5V,f SAMPLE =0ksps60µAA D C 121S 101 4ADC121S101Converter Electrical Characteristics(Notes7,9)(Continued)The following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10MHz to20MHz,C L=15pF,f SAMPLE=500ksps to1Msps,unless otherwise noted.Boldface limits apply for T A=-40˚C to+85˚C:all other limits T A= 25˚C unless otherwise noted.Symbol Parameter Conditions TypicalLimits(Note9)UnitsPOWER SUPPLY CHARACTERISTICSP D Power Consumption,Normal Mode(Operational,CS low)V A=+5V1016mW(max)V A=+3V 2.0 4.5mW(max)Power Consumption,Shutdown(CShigh)f SCLK=0MHz,V A=+5Vf SAMPLE=0ksps2.5µWf SCLK=20MHz,V A=+5V,f SAMPLE=0ksps300µWAC ELECTRICAL CHARACTERISTICSf SCLK Clock Frequency(Note8)10MHz(min) 20MHz(max)f S Sample Rate(Note8)500ksps(min) 1Msps(max)t CONV Conversion Time16SCLK cyclesDC SCLK Duty Cycle f SCLK=20MHz5040%(min) 60%(max)t ACQ Track/Hold Acquisition Time400ns(max) Throughput Time Acquisition Time+Conversion Time20SCLK cycles t QUIET(Note10)50ns(min) t AD Aperture Delay3nst AJ Aperture Jitter30ps ADC121S101Timing SpecificationsThe following specifications apply for V A=+2.7V to5.25V,GND=0V,f SCLK=10.0MHz to20.0MHz,C L=25pF,f SAMPLE=500ksps to1Msps,Boldface limits apply for T A=-40˚C to+85˚C;all other limits T A=25˚C.Symbol Parameter Conditions Typical Limits Units t CS Minimum CS Pulse Width10ns(min) t SU CS to SCLK Setup Time10ns(min)t EN Delay from CS Until SDATA TRI-STATE®Disabled(Note11)20ns(max)t ACC Data Access Time after SCLK Falling Edge(Note12)V A=+2.7to+3.640ns(max)V A=+4.75to+5.2520ns(max)t CL SCLK Low Pulse Width 0.4xt SCLKns(min)t CH SCLK High Pulse Width 0.4xt SCLKns(min)t H SCLK to Data Valid Hold Time V A=+2.7V to+3.6V7ns(min) V A=+4.75V to+5.25V5ns(min)t DIS SCLK Falling Edge to SDATA HighImpedance(Note13)V A=+2.7V to+3.6V25ns(max)6ns(min)V A=+4.75V to+5.25V25ns(max)5ns(min)t POWER-UP Power-Up Time from Full Power-Down1µs Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note2:All voltages are measured with respect to GND=0V,unless otherwise specified.ADC121S1015ADC121S101Timing Specifications(Continued)Note 3:When the input voltage at any pin exceeds the power supply (that is,V IN <GND or V IN >V A ),the current at that pin should be limited to 10mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10mA to two.The Absolute Maximum Rating specification does not apply to the V A pin.The current into the V A pin is limited by the Analog Supply Voltage specification.Note 4:The absolute maximum junction temperature (T J max)for this device is 150˚C.The maximum allowable power dissipation is dictated by T J max,the junction-to-ambient thermal resistance (θJA ),and the ambient temperature (T A ),and can be calculated using the formula P D max =(T J max −T A )/θJA .The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g.when input or output pins are driven beyond the power supply voltages,or the power supply polarity is reversed).Obviously,such conditions should always be avoided.Note 5:Human body model is 100pF capacitor discharged through a 1.5k Ωresistor.Machine model is 220pF discharged through zero ohms.Note 6:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 7:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 8:This is the frequency range over which the electrical performance is guaranteed.The device is functional over a wider range which is specified under Operating Ratings.Note 9:Data sheet min/max specification limits are guaranteed by design,test,or statistical analysis.Note 10:Minimum Quiet Time required by bus relinquish and the start of the next conversion.Note 11:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V.Note 12:Measured with the timing test circuit shown in Figure 1and defined as the time taken by the output signal to cross 1.0V or 2.0V.Note 13:t DIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1.The measured number is then adjusted to remove the effects of charging or discharging the output capacitance.This means that t DIS is the true bus relinquish time,independent of the bus loading.A D C 121S 101 6Timing Diagrams20145008FIGURE 1.Timing Test Circuit20145006FIGURE 2.ADC121S101Serial Timing DiagramADC121S1017Specification DefinitionsACQUISITION TIME is the time required to acquire the input voltage.That is,it is time required for the hold capacitor to charge up to the input voltage.APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion.APERTURE JITTER (APERTURE UNCERTAINTY)is the variation in aperture delay from sample to sample.Aperture jitter manifests itself as noise in the output.CONVERSION TIME is the time required,after the input voltage is acquired,for the ADC to convert the input voltage to a digital word.DIFFERENTIAL NON-LINEARITY (DNL)is the measure of the maximum deviation from the ideal step size of 1LSB.DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.The speci-fication here refers to the SCLK.EFFECTIVE NUMBER OF BITS (ENOB,or EFFECTIVE BITS)is another method of specifying Signal-to-Noise and Distortion or SINAD.ENOB is defined as (SINAD −1.76)/6.02and says that the converter is equiva-lent to a perfect ADC of this (ENOB)number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3dB below its low frequency value for a full scale input.GAIN ERROR is the deviation of the last code transition (111...110)to (111...111)from the ideal (V REF −1.5LSB),after adjusting for offset error.INTEGRAL NON-LINEARITY (INL)is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2LSB below the first code transition)through positive full scale (1⁄2LSB above the last code transition).The deviation of any given code from this straight line is measured from the center of that code value.INTERMODULATION DISTORTION (IMD)is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and thirdorder intermodulation products to the sum of the power in both of the original frequencies.IMD is usually expressed in dB.MISSING CODES are those output codes that will never appear at the ADC outputs.The ADC121S101is guaranteed not to have any missing codes.OFFSET ERROR is the deviation of the first code transition (000...000)to (000...001)from the ideal (i.e.GND +0.5LSB).SIGNAL TO NOISE RATIO (SNR)is the ratio,expressed in dB,of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency,not including harmonics or d.c.SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)Is the ratio,expressed in dB,of the rms value of the input signal to the rms value of all of the other spectral compo-nents below half the clock frequency,including harmonics but excluding d.c.SPURIOUS FREE DYNAMIC RANGE (SFDR)is the differ-ence,expressed in dB,between the desired signal ampli-tude to the amplitude of the peak spurious spectral compo-nent,where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.TOTAL HARMONIC DISTORTION (THD)is the ratio,ex-pressed in dB or dBc,of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output.THD is calcu-lated aswhere A f1is the RMS power of the input frequency at the output and A f2through A f6are the RMS power in the first 5harmonic frequencies.THROUGHPUT TIME is the minimum time required between the start of two successive conversion.It is the acquisition time plus the conversion time.A D C 121S 101 8Typical Performance CharacteristicsT A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN=100kHz unless otherwise stated.DNLf SCLK =10MHzINLf SCLK=10MHz2014502020145021DNLf SCLK =20MHz INLf SCLK =20MHz2014506020145061DNL vs.Clock Frequency INL vs.Clock Frequency2014506520145066ADC121S1019Typical Performance Characteristics T A =+25˚C,f SAMPLE =500ksps to 1Msps,f SCLK =10MHz to 20MHz,f IN =100kHz unless otherwise stated.(Continued)SNR vs.Clock FrequencySINAD vs.Clock Frequency2014506320145064SFDR vs.Clock Frequency THD vs.Clock Frequency2014506720145068Spectral Response,V A =5.25Vf SCLK =10MHz Spectral Response,V A =5.25Vf SCLK =20MHz2014506920145070A D C 121S 101 10ADC121S101Typical Performance Characteristics T=+25˚C,f SAMPLE=500ksps to1Msps,Af SCLK=10MHz to20MHz,f IN=100kHz unless otherwise stated.(Continued)Power Consumption vs.Throughput,f SCLK=20MHz Array 2014505511Applications Information1.0ADC121S101OPERATIONThe ADC121S101is a successive-approximation analog-to-digital converter designed around a charge-redistribution digital-to-analog converter core.Simplified schematics of the ADC121S101in both track and hold modes are shown in Figure 3and Figure 4,respectively.In Figure 3,the device is in track mode:switch SW1connects the sampling capacitor to the input,and SW2balances the comparator inputs.The device is in this state until CS is brought low,at which point the device moves to hold mode.Figure 4shows the device in hold mode:switch SW1con-nects the sampling capacitor to ground,maintaining the sampled voltage,and switch SW2unbalances the compara-tor.The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced.When the comparator is balanced,the digital word supplied to the DAC is the digital representation of the analog input voltage.The device moves from hold mode to track mode on the 13th rising edge of SCLK.2.0USING THE ADC121S101The serial interface timing diagram for the ADC121S101is shown in Figure 2.CS is chip select,which initiates conver-sions on the ADC121S101and frames the serial data trans-fers.SCLK (serial clock)controls both the conversion pro-cess and the timing of serial data.SDATA is the serial data out pin,where a conversion result is found as a serial data stream.Basic operation of the ADC121S101begins with CS going low,which initiates a conversion process and data transfer.Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS;for example,"the third falling edge of SCLK"shall refer to the third falling edge of SCLK after CS goes low.At the fall of CS,the SDATA pin comes out of TRI-STATE,and the converter moves from track mode to hold mode.The input signal is sampled and held for conversion on the fallingedge of CS.The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figure 2).The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK,or at the rising edge of CS,whichever occurs first.After a conversion is completed,the quiet time t QUIET must be satisfied before bringing CS low again to begin another conversion.Sixteen SCLK cycles are required to read a complete sample from the ADC121S101.The sample bits (including leading zeroes)are clocked out on falling edges of SCLK,and are intended to be clocked in by a receiver on subse-quent falling edges of SCLK.The ADC121S101will produce three leading zero bits on SDATA,followed by twelve data bits,most significant first.If CS goes low before the rising edge of SCLK,an additional (fourth)zero bit may be captured by the next falling edge of SCLK.20145009FIGURE 3.ADC121S101in Track Mode20145010FIGURE 4.ADC121S101in Hold ModeA D C 121S 101 12Applications Information(Continued)3.0ADC121S101TRANSFER FUNCTIONThe output format of the ADC121S101is straight binary.Code transitions occur midway between successive integer LSB values.The LSB width for the ADC121S101is V A /4096.The ideal transfer characteristic is shown in Figure 5.The transition from an output code of 000000000000to a code of 000000000001is at 1/2LSB,or a voltage of V A /8192.Other code transitions occur at steps of one LSB.4.0TYPICAL APPLICATION CIRCUITA typical application of the ADC121S101is shown in Figure 6.Power is provided in this example by the National Semiconductor LP2950low-dropout voltage regulator,avail-able in a variety of fixed and adjustable output voltages.The power supply pin is bypassed with a capacitor network lo-cated close to the ADC121S101.Because the reference for the ADC121S101is the supply voltage,any noise on the supply will degrade device noise performance.To keep noise off the supply,use a dedicated linear regulator for this de-vice,or provide sufficient decoupling from other circuitry to keep noise off the ADC121S101supply pin.Because of the ADC121S101’s low power requirements,it is also possible to use a precision reference as a power supply to maximize performance.The three-wire interface is shown connected to a microprocessor or DSP .5.0ANALOG INPUTSAn equivalent circuit for the ADC121S101’s input is shown in Figure 7.Diodes D1and D2provide ESD protection for the analog inputs.At no time should the analog input go beyond (V A +300mV)or (GND −300mV),as these ESD diodes will begin conducting,which could result in erratic operation.The capacitor C1in Figure 7has a typical value of 4pF,and is mainly the package pin capacitance.Resistor R1is the on resistance of the track /hold switch,and is typically 500ohms.Capacitor C2is the ADC121S101sampling capacitor and is typically 26pF.The ADC121S101will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.This is especially important when using the ADC121S101to sample AC signals.Also important when sampling dynamic signals is an anti-aliasing filter.6.0DIGITAL INPUTS AND OUTPUTSThe ADC121S101digital inputs (SCLK and CS)are not limited by the same maximum ratings as the analog inputs.The digital input pins are instead limited to +5.25V with respect to GND,regardless of V A ,the supply voltage.This allows the ADC121S101to be interfaced with a wide range of logic levels,independent of the supply voltage.7.0MODES OF OPERATIONThe ADC121S101has two possible modes of operation:normal mode,and shutdown mode.The ADC121S101en-ters normal mode (and a conversion process is begun)when CS is pulled low.The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low,or will stay in normal mode if CS remains low.Once in shutdown mode,the device will stay there until CS is brought low again.By varying the ratio of time spent in the normal and shutdown modes,a system may trade-off throughput for power consumption,with a sample rate as low as zero.7.1Normal ModeThe fastest possible throughput is obtained by leaving the ADC121S101in normal mode at all times,so there are no power-up delays.To keep the device in normal mode con-tinuously,CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).If CS is brought high after the 10th falling edge,but before the 16th falling edge,the device will remain in normal mode,but the current conversion will be aborted,and SDATA will return to TRI-STATE (truncating the output word).Sixteen SCLK cycles are required to read all of a conversion word from the device.After sixteen SCLK cycles have20145011FIGURE 5.Ideal Transfer Characteristic20145013FIGURE 6.Typical Application Circuit20145014FIGURE 7.Equivalent Input CircuitADC121S10113Applications Information(Continued)elapsed,CS may be idled either high or low until the next conversion.If CS is idled low,it must be brought high again before the start of the next conversion,which begins when CS is again brought low.After sixteen SCLK cycles,SDATA returns to TRI-STATE.Another conversion may be started,after t QUIET has elapsed,by bringing CS low again.7.2Shutdown ModeShutdown mode is appropriate for applications that either do not sample continuously,or it is acceptable to trade through-put for power consumption.When the ADC121S101is in shutdown mode,all of the analog circuitry is turned off.To enter shutdown mode,a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK,as shown in Figure 8.Once CS has been brought high in this manner,the device will enter shutdown mode;the current conversion will be aborted and SDATA will enter TRI-STATE.If CS is brought high before the second falling edge of SCLK,the device will not change mode;this is to avoid accidentally changing mode as a result of noise on the CS line.To exit shutdown mode,bring CS back low.Upon bringing CS low,the ADC121S101will begin powering up (power-up time is specified in the Timing Specifications table).This power-up delay results in the first conversion result being unusable.The second conversion performed after power-up,however,is valid,as shown in Figure 9.If CS is brought back high before the 10th falling edge of SCLK,the device will return to shutdown mode.This is done to avoid accidentally entering normal mode as a result of noise on the CS line.To exit shutdown mode and remain in normal mode,CS must be kept low until after the 10th falling edge of SCLK.The ADC121S101will be fully powered-up after 16SCLK cycles.8.0POWER MANAGEMENTThe ADC121S101takes time to power-up,either after first applying V A ,or after returning to normal mode from shut-down mode.This corresponds to one "dummy"conversion for any SCLK frequency within the specifications in this document.After this first dummy conversion,the ADC121S101will perform conversions properly.Note that the t QUIET time must still be included between the first dummy conversion and the second valid conversion.When the V A supply is first applied,the ADC121S101may power up in either of the two modes:normal or shutdown.As such,one dummy conversion should be performed after start-up,as described in the previous paragraph.The part may then be placed into either normal mode or the shutdown mode,as described in Sections 7.1and 7.2.When the ADC121S101is operated continuously in normal mode,the maximum throughput is f SCLK /20.Throughput may be traded for power consumption by running f SCLK at its maximum specified rate and performing fewer conversions per unit time,raising the ADC121S101CS line after the 10th and before the 15th fall of SCLK of each conversion.A plot of typical power consumption versus throughput is shown in the Typical Performance Curves section.To calculate the power consumption for a given throughput,multiply the frac-tion of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption.Note that the curve of power consumption vs.throughput is essentially linear.This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.20145016FIGURE 8.Entering Shutdown Mode20145017FIGURE 9.Entering Normal ModeA D C 121S 10114。

TLA-121双12英尺线阵扑音库扬声器用户指南说明书

TLA-121双12英尺线阵扑音库扬声器用户指南说明书

TLA-121Dual 12'' line array speakerUser Manual U M-T L A-121-20090311 v e r B11. 2. 3. 4. 5. 6. 7. 8. 9. 10. Read the instruction first before using this product.Pay attention to all warnings.Obey all operating instructions.Do not expose this product to rain or moisture.Do not block any ventilation openings. Install according to instructions .Do not install this product near any heat source, such as , heater, burner, or any other equipment with heat radiation .Only use spare parts by manufacturer.Pay attention to the safety symbol on the of the cover.manual Please keep this manual for future reference Clean this equipment with a dry cloth.manufacturer's a supplied the outside SAFETY INSTRUCTIONSPLEASE READ THIS MANUAL FIRSTThank you for a buying product. Read this manual first as it will help you operate the system properly. Please keep this manual for future reference.WARNING:This product must be installed by professionals. When using hanging brackets or rigging other than those supplied withthe product, please ensure they comply with the local safety codes.The exclamation point within an equilateral triangle is intended to alert you to the presence of important operating and servicing instructions.ATTENTION: Don't refit the system or spare parts without being authorized as this will .void the warranty WARNING: Don't (such as candles) the equipment.place naked flames close toTLA-1212CONTENTSDual 12'' line array speaker45333344455667811109CONTENTSPRODUCT INTRODUCTIONMain Features Product Description ApplicationCONNECTIONTerminal Plate Nl4 ConnectionSystem Connection DemonstrationINSTALLATIONInstallation Accessories Installation ReferenceTECHNICAL SPECIFICATIONSpecification Sheet Frequency Response Impedance Curve Harmonic Distortion WaterfallDimension DrawingProduct information updated without notification, please visit for latest update.may beTLA-121TLA-1213Dual 3 Neo compression driver.''Dual 12Neo woofer unit.''Long term continuous power: LF 500W, HF 100W.o o o o Dispersion angle: LF 110 x 90, HF 90x20.Frequency response: LF 90Hz-4KHz (-3dB), HF 900Hz-15KHz(-3dB).Sensitivity: LF 102dB, HF 110dB.Max SPL: LF 131dB, HF 134dB.Appropriate hanging frame with shackle for installation.Dual 12'' line array speakerMain FeaturesProduct Descriptionutilizing appropriate frame, which can hang 12pcs TLA-121 speaker at its maximum in vertical direction.T L A-121'' i s t wo -way s p e a k e r, b u i l t-i n d u a l 12 N e o woofer and dual 3 Kapton compression driver. The ''Cylindrical wave segments of each cabinet will couple w i t h o u t g a p s a n d s u m u p co h e re nt l y. S p l ay a n g l e s b e t we e n a d j a ce nt c a b i n e t s c a n b e s e t i n t h e ra n g e O O from 0 to 10.Through FEA (Finite Element Analysis) to optimize t h e m a g n e t i c s y s t e m a n d c o p p e r r i n g, d u a l 12 L F '' driver can realize super low distortion and maximum cleanness, besides overheat protection for compression dr iver and per fec t circuit protec tion for reliabilit y.TLA-121 adopts multi-func tional struc ture design, suitable for live per formance and fixed installation. The cabinet is made of 15mm, 11 layers birch plywood a n d w e a t h e r r e s i s t a n t p o l y u r e t h a n e f i n i s h. T h e cabinet is included appropriate flying frame, which can be installed and hanged conveniently according to different environment.ApplicationTheaterReligion Place Auditorium Multi-function hall All kinds of living performance Sports eventsMobile performancePRODUCT INTRODUCTIONDual 12'' line array speakerTLA-121 is medium size line array speaker system,β3 The driver have function of overload protection.TLA-121121234Elder Audio Manufacture Co., Ltd.No.INPUTOUTPUTTLA-121Warranty does not cover permanent damages of parts inside of the speaker caused by overload running for a long time.LF:500W/HF:100WSENSITIVITY(1W/1m):POWER(RMS):IMPEDANCE:LF:102dB/HF:110dBLF:16 Ohm/HF:16 OhmTLA-121 has two Speakon NL4 socket and amplifier connection. Two parallel connection socket is convenient to connect with another speaker.Terminal Plate2: Disconnection1: ConnectionNl4 ConnectionDual 12'' line array speakerCONNECTIONNL4 Interface NL4 Interface1+1-2+2-1+1-2+2-Passive limiterSystem Connection DemonstrationNote: The output impedance of speaker and amplifier should be matched.Note: The polar of speaker and amplifier should be correctly connected.CHA BRIDGE INCHBSIGNAL GND SIGNAL +SIGNAL -BRIDGE PARALLEL STEREOON OFF50HZ 25HZ ONOFF CHB OUTPUTCHA OUTPUTPOWER CABLEFUSE-B+-A+-+5HZCAUTIONB R D G EOUTPUT ASSIGNMENT: BRIDGE MONO OUTPUT:CHA :PIN1+ : SIGNAL GNDCHA:PIN 1+ :PIN 1 - :PIN 2+ :PIN 2 - : CHA SIGNALCHA GND CHB SIGNAL CHB GNDCHB:PIN 1+ :PIN 1 - :PIN 2+ :PIN 2 - :CHB SIGNALCHB GND PIN2+ : !Serial no:Special design for big power ！RISK OF ELECTRIC SHOCKDO NOT OPENMODELF FILTERGROUNDCLIPLIMITERINPUTPIN1: PIN2: PIN3: TLA-121TLA-12154-YXPJ-112with brake 4-YXPJ-113without brake.Frame （7-DJ-RH-B01)Wheel bracket （1-AZPJ-85)1: Hanging2: Installation drawing with wheelsInstallation AccessoriesTLA-121 speaker includes appropriate flying frame and 4 "wheel, which can be installed or hanged conveniently according to different environment.Hanging system includes frame, front hanging TLA-121 plate, rear hanging plate and lockpin.The rear hanging plate is fixed on cabinet to choose splay angle between adjacent speakers quickly.TLA-121 frame is soldering steel frame, which can hang 12pcs speaker at its maximum.TLA-121Dual 12'' line array speakerINSTALLATIONThe outstanding point of real hanging plate indicates the present angle.4 wheel"Installation ReferenceTLA-1216LF:102dB HF:110dBDispersion（H×V）:LF: 500W : 100W (RMS)LF: 1000W HF: 200W (MUSIC)LF: 2000W HF: 400W (PACK)HFLF:90Hz-4kHz HF:900Hz-15kHzLF:131dB/137dB(PEAK)HF:134dB/140dB(PEAK)0000LF:110×90 HF:90×20LF:8 Ohms HF:8 OhmsLF:6 Ohms HF:6.4 OhmsCabinet dimension(W×H×D):Package dimension(W×H×D):960×372×523mm(37.8×14.6×20.6in)700×1080×440mm(27.6×42.5×17.3in)37kg(81.4 lb)43kg(94.6 lb)NL4×2 @ LF:1+ 1- HF2+2-System type:HF driver:LF driver:Frequency response (-3dB):Sensitivity (1W@1m):Power:Rated impedance:DC impedance:Cabinet:Installation:Carry:weather resistant polyurethane finish, black powder coating for grille.Connector:Net Weight:Gross weight:Max SPL(1m):Dual 3" Neo compression driverDual 12" woofer15mm 11 layers birch plywoodAppropriate frame with 3/4"shackle2 wooden handleFinish:Optional accessory: Frame Wheel bracket4" wheel with brake without brake.（7-DJ-RH-B01), （1-AZPJ-85),（4-YXPJ-112，4-YXPJ-113)Specification SheetDual 12'' line array speaker TECHNICAL SPECIFICATIONDual 12'' line array speakerTLA-12172 501002005001k2k5k10k20k20Hz120dBS 180.0Deg110108.010036.090 -36.080 -108.070- 180.0CLIO1302 501002005001k2k5k10k20k20Hz120dBS 11010090 80 CLIO180.0Deg108.036.0-36.0-108.0- 180.0Dual 12'' line array speakerTECHNICAL SPECIFICATIONFrequency Response/phase Curve-LFFrequency ResponsePhase Curve Frequency Response/phase Curve-HFFrequency ResponsePhase CurveTLA-121810 Hz20501002005001K2K5K10K20KOhm789102030405060Impedance vs Freq10 Hz20501002005001K2K5K10K20KOhm3456789102030Impedance vs FreqDual 12'' line array speakerTECHNICAL SPECIFICATIONImpedance Curve-LF Impedance Curve-HF2 501002005001k2k5k10k20k20Hz130dBS 180.0Deg120108.011036.0100 -36.090 -108.080- 180.0CLIO180.0Deg108.036.0-36.0-108.0- 180.01 3 01 2 01 1 01 0 09 08 0CLIO20501002005001k2k 5k10k20kHz10TLA-1219Dual 12'' line array speakerTECHNICAL SPECIFICATIONHarmonic Distortion-LFHarmonic Distortion-HFDistortion CurveFrequency Response Distortion CurveFrequency ResponsedB2 0050 01K 2K 5K 1 0K 2 0K Hz-2.3 -5.7-8.0 dB2 0050 01K 2K 5K 1 0K 2 0K Hz-2.3 -5.7-8.0 Waterfall-HFTLA-12111960mm 372m m (14.6i n )(37.8in)623mm (24.5in)Dual 12'' line array speakerTECHNICAL SPECIFICATIONDimension DrawingTop viewFront view Side viewBack view。