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Dynamic Hardware Plugins (DHP) Exploiting Reconfigurable Hardware for High-Performance Prog

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Abstract--ThispaperpresentstheDynamicHard-

warePlugins(DHP)architectureforimplementingmultiplenetworkingapplicationsinhardwareatpro-

grammablerouters.Byenablingmultipleapplica-

tionstobedynamicallyloadedintoasinglehardware

device,theDHParchitectureprovidesascalablemechanismforimplementinghigh-performancepro-

grammablerouters.TheDHParchitectureispre-

sentedwithinthecontextofaprogrammablerouterarchitecturewhichprocessesflowsinbothsoftware

andhardware.Possibleimplementationsare

describedaswellastheprototypetestbedatWashing-ton University in Saint Louis1.

Keywords--Programmablerouter,reconfigurable

hardware, active networking, port processor.

I.INTRODUCTION

Asresearchersvigorouslydevelopadvancedcontrol

andprocessingschemesforprogrammablenetworks[1],thereexistsaneedforascalablerouterarchitecturecapa-

bleofrobustflow-specificprocessingatopticalline

speedswithoutprohibitivelyhighper-portcosts.Asthe

quantityanddiversityofstreamingdataandcomputa-tionallyintensiveapplicationscontinuestoincrease,

routerarchitecturesmustrespondwithgreaterflexibility,

processingcapacity,andperformance.Withnext-genera-tionrouterscontaininghundredsofports,processing

mechanisms must scale at a reasonable per-port cost.

Existingrouterarchitecturesthatprovidesufficientflexibilityandper-flowprocessingemploysoftwarepro-

cessingenvironmentscontainingmultipleReduced

InstructionSetComputer(RISC)cores.Existinghigh-

performancerouterarchitecturescapableofdataprocess-ingatopticallinespeedsemployApplicationSpecific

IntegratedCircuits(ASICs)toperformparallelcomputa-tionsinhardware.However,thesearchitecturesoften

providelimitedflexibilityfordeploymentofnewapplica-

tionsorprotocols,andnecessitatelongerdesigncycles

andhighercoststhansoftware-basedsolutions.Clearly,theidealrouterarchitecturemustexhibittheflexibility

availableinsoftwareandtheperformanceofferedby

hardware.Thediversityofnetworkingapplicationsanddataflows

suggeststhatdynamicallyreprogrammableprocessing

environmentisneededtocoverthepotentialdesignspace.Whilesomeapplicationsperforminglimitedpro-

cessingatlowdataratesreadilylendthemselvestosoft-

wareimplementation,avastarrayofapplicationsmap

welltohardwareimplementationduetohighdatarates,dataregularities,andparalleloperations.Thisimplies

thataviablesolutiontotheprogrammablerouterprob-

lemshouldemploybothsoftwareandreconfigurablehardwaretoprocessdataflows.Withthedevelopmentof

severalmulti-RISCcoreprocessorarchitecturesand

implementations,theproblemofprovidingascalablesoftwareprocessingenvironmentiswellinvestigated.

Theproblemofaddingaflexibleandscalablehardware

processing environment remains.

Traditionallyusedforlow-volumeprototypingandtestingpurposes,thereconfigurablehardwareemployed

inFieldProgrammableGateArrays(FPGAs)providesa

flexiblehardwareplatform.Recently,reconfigurablehardwaretechnologyhasmadeseveralcompellingper-

formanceadvances,identifyingitasapossiblesolution

fortheprogrammablerouternodeproblem.Newrecon-figurablehardwaredevicestoutapproximately1million

applicationlogicgates,internalclockratesupto200

MHz,over100KBofon-chipmemory,andpartial-recon-

figurationcapability[2].Moreimpressivethanthecur-renttechnicalstatisticsistherateofprogressdue

to1.ThisresearchsupportedbyNSF:ANI-0096052andXilinx, Inc.Dynamic Hardware Plugins (DHP):

Exploiting Reconfigurable Hardware for High-Performance

Programmable Routers

David E. Taylor, Jonathan S. Turner, John W. Lockwood

det3@arl.wustl.edu, jst@cs.wustl.edu, lockwood@arl.wustl.edu

Applied Research Laboratory

Washington University in Saint Louis

Campus Box 1045

One Brookings Drive

Saint Louis, MO 63130

USA

(314) 935-4845

0-7803-7064-3/01/$10.00 (C) 2001 IEEEIEEE OPENARCH 2001

architecturaloptimizationsandsiliconfabrication

improvements:usablelogicgatecountincreasedby10timesintwoyears;systemclockfrequencydoubledin

oneyear;I/Obandwidthquadrupledintwoyears;block

anddistributedon-chipmemorycapacityquadrupledin

oneyear[3].Reconfigurablehardwaredevicesareclearlypositioningthemselvesasviableoptionsforflexible,

high-performance systems.

TheDynamicHardwarePlugins(DHP)architectureemploysreconfigurablehardwaretoprovideaflexible

hardwareprocessingenvironmentforprogrammable,

multi-portrouters.DHPallowsmultiplehardwareappli-cations,orplugins,tobedynamicallyloadedintoasingle

deviceandruninparallel,providingasubstantialamount

ofper-flowprocessing.Withdedicatedon-chiplogicandmemoryresourcesprovisionedforeachpluginaswellas

arbitratedaccesstotwotypesofoff-chipmemory

resources,DHPsupportsabroadspectrumofapplica-

tions.ResultsofseveralcasestudiesofAdvancedEncryptionStandard(AES)implementationsinsoftware,

FPGAs,andASICsareusedtoshowthepotentialperfor-

manceandflexibilitygainsoftheDHParchitecturefornetworking applications in programmable routers.

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4翻译

4翻译

毕 业 设 计（论 文）外 文 参 考

资 料 及 译 文

译文题目： CIC MegaCore Function

学生姓名： 高佳 学 号： 1021129024

专 业： 通信工程

所在学院： 龙蟠学院

指导教师： 姜志鹏

职 称： 讲师

2013年11月06日

1 CIC MegaCore Function

----From

Description

This document describes the Altera CIC MegaCore function. The Altera CIC

MegaCore function implements a cascaded integrator-comb filter with data ports that

are compatible with the Avalon Streaming interface. CIC filters (also known as

Hogenauer filters) are computationally efficient for extracting baseband signals from

narrow-band sources using decimation, and for constructing narrow-band signals from

processed baseband signals using interpolation.CIC filters use only adders and

registers, and require no multipliers to handle large rate changes. Therefore, CIC is a

eDP规范 1.4b 20191209

eDP规范 1.4b 20191209

第1頁，全部62頁 VESA嵌入式DisplayPort（eDP）標準

v1.4b 2015年10月23日

目的

本標准為嵌入式顯示器的應用，定義了標準顯示面板接口的要求和選項。 它基於VESA DisplayPort標準版本1.3（DP v1.3），並包括建議系統集成商考慮的，特定於產品實作的選項。

摘要

DP v1.3是有彈性的、可擴展的視頻數據接口，開髮用於嵌入式（內部）和外部（設備對設備）應用程序。 雖然DisplayPort標準確實引用了嵌入式應用程序，但它主要是面向外部應用程序，強調系統供應商與互連電纜。 本標准定義了DisplayPort嵌入式版本的功能集，用於應用程序，包括但不限於筆記本電腦和Al-In-One一體機電腦。

內容

目的

摘要

序言

知識產權

商標

對這個標準的支持

專利

致謝

修訂記錄

第一節概述

1.1背景

1.2首字母縮寫詞

1.3詞彙表

1.4參考資料

第2節eDP系統架構

2.1 eDP系統的應用

2.2源設備Source和宿設備Sink對eDP的支持

2.3 Multi-SST體系結構

第3節eDP v1.4b與DP v1.3的差異

3.1背景

3.2 eDP實施

3.3特定於eDP v1.4b的寄存器摘要

3.4 eDP AUX鏈接服務

3.5顯示身份驗證和內容保護支持 第2頁，全部62頁 3.6面板輸入功率（LCDVCC）

3.7主流屬性數據

3.8多SST操作

3.8.1 Multi-SST體系結構概述

3.8.2多SST操作源配置

3.8.3具有兩個SST鏈接的多SST操作，每個通道（2x1）

3.8.4具有兩個SST鏈接的多SST操作，每個通道（2x2）

3.8.5具有四個SST鏈接的Multi-SST操作，四個通道每個（4x1）

3.8.6像素重疊的多SST操作相鄰面板細分

3.8.7多SST操作DPCD功能寄存器

3.8.8多SST操作時序要求（僅相關的多SST操作鏈接）

MetaHDL:面向自动推断和参数追踪硬件描述域特定语言

MetaHDL:面向自动推断和参数追踪硬件描述域特定语言

MetaHDL：面向自动推断和参数追踪硬件描述域特定语言

孟昕;沈海斌;严晓浪

【期刊名称】《浙江大学学报（工学版）》

【年(卷),期】2010(044)006

【摘 要】针对利用工业标准的硬件描述语言(HDL)进行可配置参数化系统芯片(SoC)设计工作繁琐、代码不易维护的问题.提出域特定语言MetaHDL,用于可配置数字集成电路的可综合功能描述,范围从面向逻辑的底层模块设计到IP集成的soc设计.MetaHDL利用自动推断和参数追踪技术,针对电路结构功能描述作了专门的语法优化,提高了语言的描述力和表现力,进而提升了代码的可读性和可维护性,并达到65%以上的代码精简;通过封装寄存器传输级(RTL)设计规则,降低了RTL描述的复杂度,提高了团队工作质量和工作效率;由MetaHDL预处理器和参数追踪机制构成的二级代码配置体系,大大简化了面向重用的可配置参数化模块的设计和IP集成过程.MetaHDL被应用在"统一威胁管理"芯片设计项目中,很好地应对了复杂重用环境下代码配置的设计挑战,提高了项目开发的效率和质量.

【总页数】8页(P1079-1085,1097)

【作 者】孟昕;沈海斌;严晓浪

【作者单位】浙江大学超大规模集成电路研究所,浙江,杭州,310027;浙江大学超大规模集成电路研究所,浙江,杭州,310027;浙江大学超大规模集成电路研究所,浙江,杭州,310027

【正文语种】中 文 【中图分类】TN402

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