LM2596T中文资料元器件交易网/doc/a66360844.html,3.0A, 150Khz, Step-Down Switching RegulatorFEATURES3.3V, 5.0V, 12V, 15V, and Adjustable Output Versions Adjustable Version Output Voltage Range, 1.23 to 37V +/- 4%. Maximum Over Line and Load Conditions Guaranteed 3.0A Output Current Wide Input Voltage Range Requires Only 4 External Components 150Khz Fixed Frequency Internal Oscillator TTL Shutdown Capability, Low Power Standby Mode High Efficiency Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection Moisture Sensitivity Level(MSL) Equals1 TO-263(D2) TO-220V TO-220LM2596ApplicationsSimple High-Efficiency Step-Down(Buck) Regulator Efficient Pre-Regulator for Linear Regulators On-Card Switching Regulators Positive to Negative Converter(Buck-Boost) Negative Step-Up Converters Power Supply for Battery Chargers1. 2. 3. 4. 5. Vin Output Ground Feedback On/OffDESCRIPTIONThe LM2596 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step-down switching regualtor(buck converter). All circuits of this series are capable of driving a 3.0A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3V, 5.0V,12V, 15V, and an adjustable output version.ORDERING INFORMATIONDevice LM2596T-X.X LM2596TV-X.X LM2596R MarkingLM2596T-X.X LM2596T-X.X LM2596R-X.X Package TO-220 TO-220V TO-263These regulatiors were designed to minimize the number of externalcomponents to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2596 converter is a switch-mode power supply, its efficiency is significantly higher in comparison with popular three-terminal limear reguators, especially with higher input voltages. In many cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically. A standard series of inductors optimized for use with the LM2596 are available from several different manufacturers. This feature greatly simplifies the design of switch-mode power supplies. The LM2596 features include a guaranteed +/- 4% tolerance on output voltage within specified input voltages and output load conditions, and +/-15% on the oscillator frequency (+/- 2% over 0oC to 125 oC). External shutdown is included, featuring 80 uA(typical) standby current. The output switch includes cycle-bycycle current limiting, as well as thermal shutdown for full protection under fault conditions.HTC1Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTypical Application (Fixed Output Voltage Versions)LM2596LM2596-5.033 uH680 uF1N5824220 uFFigure 1. Block Diagram and Typical ApplicationABSOLUTE MAXIMUM RATINGS(Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.)Power DissipationTO-220, 5-LeadThermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-caseTO-263Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-caseHTC2Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596OPERATING RATINGS (Operating Ratings indicate conditions for which the device is intended to befunctional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.)ELECTRICAL CHARACTERISTICS / SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 2) (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.)LM2596-3.3 ([ Note 1]. Test Circuit Figure 2 )73 LM2596-5.0 ([ Note 1]. Test Circuit Figure 2 ) 180 LM2596-12 ([ Note 1]. Test Circuit Figure 2 )90 LM2596-15 ([ Note 1]. Test Circuit Figure 2 )98 LM2596-ADJ ([ Note 1]. Test Circuit Figure 2 )73HTC3Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorELECTRICAL CHARACTERISTICS / Device ParametersLM2596(Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500 mA. For typical values Tj = 25°C, for min/max values Tj is the operating junction temperature range that applies [Note 2], unless otherwise noted.)10 0 127 110 15050 100 173 1731.16 01.4 1.53.6 3.4100 4.5 6.9 7.5 50 30 102 5 00 2 0 2.0 2.0 2 V LOGIC = 2.5V (Regulator OFF) V LOGIC = 0.5V (Regulator ON) 5 0.02 1.3 1.32500.6 0.6 15 5.01. External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2596 is used as shown in the Figure 1 test circuit, system performance will be as shown in system parameters section .2. Tested junction temperature range for the LM2596 : TLOW = –0°C THIGH = +125°C3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to drop approximately 40% from the nominal output voltage. This self protection feature lowers the average dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%.4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to output pin.5. Feedback (Pin 4) removed from output and connected to 0 V.6. Feedback (Pin 4) removed from output and connected to +12 V for the Adjustable, 3.3 V, and 5.0V ersions, and +25 V for the 12 V and15 V versions, to force the output transistor “off”.7. Vin = 40 V.HTC4Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTYPICAL PERFORMANCE CHARACTERISTICS (Circuit ofFigure 2)LM2596HTC5Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 2)Feedback Pin Bias CurrentLM2596HTC6Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorTest Circuit and Layout GuidelinesLM2596Figure 2. Typical Test Circuits and Layout GuideAs in any switching regulator, layout is very important. Rapidly switching currents associated with wiring inductance can generate voltage transients which can cause problems. For minimal inductance and ground loops, the wires indicated by heavy lines should be wide printed circuit traces and should be kept as short as possible. For best results, external components should be located as close to the switcher lC as possible using ground plane construction or single point grounding. If open core inductors are used, special care must be taken as to thelocation and positioning of this type of inductor. Allowing the inductor flux to intersect sensitive feedback, lC groundpath and COUT wiring can cause problems. When using the adjustable version, special care must be taken as to the location of the feedback resistors and the associated wiring. Physically locate both resistors near the IC, and route the wiring away from the inductor, especially an open core type of inductor.HTC7Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596PIN FUNCTION DESCRIPTION Symbol 1VinDescription This pin is the positive input supply for the LM2596 step–down switching23 45regulator.In order to minimize voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass capacitor must be present .(Cin in Figure 1). Output This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.5 V. It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to minimize coupling to sensitive circuitry. Circuit ground pin. See the information about the printed circuit board layout. Gnd Feedback This pin senses regulated outputvoltage to complete the feedback loop. The signal is divided by the internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier. In the Adjustable version of the LM2596 switching regulator this pin is the direct input of the error amplifier and the resistor network R2, R1 is connected externally to allow programming of the output voltage. ON/OFF It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total input supply current to approximately 80 mA. The threshold voltage is typically 1.4 V. Applying a voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than 1.4V or if this pin is left open, the regulator will be in the "on" conditionHTC8Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorLM2596PACKAGES DIMENSION : TO220-5LHTC9Oct 2004 - Rev 0元器件交易网/doc/a66360844.html,3.0A, 15V, Step-Down Switching RegulatorPACKAGES DIMENSION : TO220V-5LLM2596HTC10Oct 2004 - Rev 0元器件交易网/doc/a66360844.html, 3.0A, 15V, Step-Down Switching RegulatorLM2596PACKAGES DIMENSION : TO263-5LHTC11Oct 2004 - Rev 0。
±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorDatasheetProduct Featuress Code Compatible with all 80960Jx ProcessorssHigh-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is:1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT —Load/Store Programming Model —Sixteen 32-Bit Global Registers—Sixteen 32-Bit Local Registers (8 sets)—Nine Addressing Modes—User/Supervisor Protection Model sTwo-Way Set Associative Instruction Cache—80960JA - 2Kbyte —80960JF/JD - 4Kbyte —80960JS/JC/JT - 16Kbyte —Programmable Cache-Locking MechanismsDirect Mapped Data Cache —80960JA - 1Kbyte —80960JF/JD - 2Kbyte —80960JS/JC/JT - 4Kbyte —Write Through Operation sOn-Chip Stack Frame Cache—Seven Register Sets May Be Saved —Automatic Allocation on Call/Return —0-7 Frames Reserved for High-Priority InterruptssOn-Chip Data RAM—1Kbyte Critical Variable Storage —Single-Cycle Access s3.3V Supply Voltage —5V Tolerant Inputs—TTL Compatible Outputs sHigh Bandwidth Burst Bus—32-Bit Multiplexed Address/Data—Programmable Memory Configuration —Selectable 8-, 16-, 32-Bit Bus Widths —Supports Unaligned Accesses—Big or Little Endian Byte Ordering sHigh-Speed Interrupt Controller —31 Programmable Priorities —Eight Maskable Pins plus NMI#—Up to 240 Vectors in Expanded Mode sTwo On-Chip Timers—Independent 32-Bit Counting —Clock Prescaling by 1, 2, 4 or 8—Internal Interrupt Sources s Halt Mode for Low Powers IEEE 1149.1 (JTAG) Boundary Scan Compatibility sPackages—132-Lead Pin Grid Array (PGA)—132-Lead Plastic Quad Flat Pack (PQFP)—196-Ball Mini Plastic Ball Grid Array (MPBGA)Order Number: 273159-006August 2004INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling1-800-548-4725 or by visiting Intel’s website at .AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Copyright © Intel Corporation, 2002, 2004Contents Contents1.0Introduction (7)2.080960Jx Overview (9)2.180960 Processor Core (10)2.2Burst Bus (11)2.3Timer Unit (11)2.4Priority Interrupt Controller (11)2.5Instruction Set Summary (12)2.6Faults and Debugging (12)2.7Low Power Operation (12)2.8Test Features (12)2.9Memory-Mapped Control Registers (13)2.10Data Types and Memory Addressing Modes (13)3.0Packaging Information (15)3.1Available Processors and Packages (15)3.2Pin Descriptions (16)3.2.1Functional Pin Definitions (16)3.2.280960Jx 132-Lead PGA Pinout (23)3.2.380960Jx 132-Lead PQFP Pinout (27)3.2.480960Jx 196-Ball MPBGA Pinout (30)4.0Electrical Specifications (35)4.1Absolute Maximum Ratings (35)4.2Operating Conditions (35)4.3Connection Recommendations (36)4.4VCC5 Pin Requirements (VDIFF) (36)4.5VCCPLL Pin Requirements (37)4.6 D.C. Specifications (38)4.7 A.C. Specifications (42)4.7.1 A.C. Test Conditions and Derating Curves (45)4.7.1.1Output Delay or Hold vs. Load Capacitance (46)4.7.1.2T LX vs. AD Bus Load Capacitance (47)4.7.1.3ICC Active vs. Frequency (49)4.7.2 A.C. Timing Waveforms (53)5.0Device Identification (59)5.180960JS/JC/JT Device Identification Register (60)5.280960JD Device Identification Register (61)5.380960JA/JF Device Identification Register (62)6.0Thermal Specifications (63)6.1Thermal Management Accessories (68)6.1.1Heatsinks (68)7.0Bus Functional Waveforms (69)7.1Basic Bus States (79)7.2Boundary-Scan Register (80)ContentsFigures180960Jx Microprocessor Package Options (7)280960Jx Block Diagram (10)3132-Lead Pin Grid Array Top View-Pins Facing Down (23)4132-Lead Pin Grid Array Bottom View-Pins Facing Up (24)5132-Lead PQFP - Top View (27)6196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down (30)7196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up (31)8VCC5 Current-Limiting Resistor (36)9VCCPLL Lowpass Filter (37)10 A.C. Test Load (45)11Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) (46)12Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5V Signals) (46)13Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD (47)14T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3V Signals) (47)15T LX vs. AD Bus Load Capacitance–80960JS/JC/JT (5V Signals) (48)16T LX vs. AD Bus Load Capacitance–80960JA/JF/JD (48)17I CC Active (Power Supply) vs. Frequency–80960JA/JF (49)1880960JA/JF I CC Active (Thermal) vs. Frequency (49)1980960JD I CC Active (Power Supply) vs. Frequency (50)2080960JD I CC Active (Thermal) vs. Frequency (50)2180960JC I CC Active (Power Supply) vs. Frequency (51)2280960JC I CC Active (Thermal) vs. Frequency (51)2380960JS I CC Active (Power Supply) vs. Frequency (52)2480960JS I CC Active (Thermal) vs. Frequency (52)25CLKIN Waveform (53)26T OV1 Output Delay Waveform (53)27T OF Output Float Waveform (54)28T IS1 and T IH1 Input Setup and Hold Waveform (54)29T IS2 and T IH2 Input Setup and Hold Waveform (54)30T IS3 and T IH3 Input Setup and Hold Waveform (55)31T IS4 and T IH4 Input Setup and Hold Waveform (55)32T LX, T LXL and T LXA Relative Timings Waveform (56)33DT/R# and DEN# Timings Waveform (56)34TCK Waveform (57)35T BSIS1 and T BSIH1 Input Setup and Hold Waveforms (57)36T BSOV1 and T BSOF1 Output Delay and Output Float Waveform (57)37T BSOV2 and T BSOF2 Output Delay and Output Float Waveform (58)38T BSIS2 and T BSIH2 Input Setup and Hold Waveform (58)3980960JS/JC/JT Device Identification Register Fields (60)4080960JD Device Identification Register Fields (61)4180960JA/JF Device Identification Register Fields (62)42Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus (69)43Burst Read and Write Transactions Without Wait States, 32-Bit Bus (70)44Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus (71)45Burst Read and Write Transactions Without Wait States, 8-Bit Bus (72)46Burst Read and Write Transactions With 1, 0 Wait Statesand Extra Tr State on Read, 16-Bit Bus (73)47Double Word Read Bus Request, Misaligned One Byte FromQuad Word Boundary, 32-Bit Bus, Little Endian (74)Contents 48HOLD/HOLDA Waveform For Bus Arbitration (75)49Cold Reset Waveform (76)50Warm Reset Waveform (77)51Entering the ONCE State (78)52Bus States with Arbitration (80)53Summary of Aligned and Unaligned Accesses (32-Bit Bus) (84)54Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) (85)Tables180960Jx 3.3-V Microprocessor Family (7)280960Jx Instruction Set (14)380960Jx Processors Available in 132-Pin PGA Package (15)480960Jx Processors Available in 132-Pin PQFP Package (15)580960Jx Processors Available in Extended Temperature (16)680960Jx Processors Available in 196-Ball MPBGA Package (16)7Pin Description Nomenclature (17)8Pin Description—External Bus Signals (18)9Pin Description—Processor Control Signals, Test Signals, and Power (21)10Pin Description—Interrupt Unit Signals (22)11132-Lead PGA Pinout—In Signal Order (25)12132-Lead PGA Pinout—In Pin Order (26)13132-Lead PQFP Pinout—In Signal Order (28)14132-Lead PQFP Pinout—In Pin Order (29)15196-Ball MPBGA Pinout—In Signal Order (32)16196-Ball MPBGA Pinout—In Pin Order (33)17Absolute Maximum Ratings (35)1880960Jx Operating Conditions (35)19VDIFF Parameters (37)2080960Jx D.C. Characteristics (38)2180960Jx I CC Characteristics (39)2280960Jx A.C. Characteristics (42)23Note Definitions for Table 22, 80960Jx AC Characteristics (45)2480960Jx Device Type and Stepping Reference (59)2580960JS/JC/JT Device ID Register Field Definitions (60)2680960JS/JC/JT Device ID Model Types (60)2780960JD Device ID Field Definitions (61)2880960JD Device ID Model Types (61)2980960JA/JF Device ID Field Definitions (62)3080960JA/JF Device ID Model Types (62)31Thermal Resistance for q CA and q JC Reference Table (63)32Maximum Ambient Temperature Reference Table (63)33132-Lead PGA Package Thermal Characteristics (64)3480960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics (64)3580960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics (65)36132-Lead PQFP Package Thermal Characteristics (65)37Maximum T A at Various Airflows in °C (80960JT) (66)38Maximum T A at Various Airflows in °C (80960JC) (66)39Maximum T A at Various Airflows in °C (80960JD) (67)40Maximum T A at Various Airflows in °C (80960JS) (67)41Maximum T A at Various Airflows in °C (80960JA/JF) (68)Contents42Boundary-Scan Register—Bit Order (81)43Natural Boundaries for Load and Store Accesses (81)44Summary of Byte Load and Store Accesses (82)45Summary of Short Word Load and Store Accesses (82)46Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) (83)Revision HistoryDate Revision DescriptionSeptember 2002005Removed reference to A80960JF-16 from Table 3 on page15. Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16,and NG80960JF-16 from Table 4 on page15.Removed reference to GD80960JC-40, GD80960JC-33, and 80960JS-16 in Table 6 on page16.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 in Table 18 on page35.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and 80960JF-16 from Table 21 on page39.Removed reference to 80960JC-40, 80960JC-33, 80960JS-16 and 80960JF-16 from Table 22 on page42.September 1999004Added new extended temp device offerings. See Table 5 on page16. Removed PGA package availability from JS/JC/JT processors. Changed AC timing parameter T OV1 (min) for extended temp devices only.See Table 22 on page42.June 1999003Merged the 80960JS/JC datasheet information into this datasheet (previously named 80960JA/JF/JD/JT 3.3V Embedded 32-Bit Microprocessor datasheet).Updated I CC values for the 80960JS/JC/JT processors. Increased TIH1 specification for the 80960JS/JC/JT processors. Updated MPBGA thermal specifications.December 1998002Corrected orientation of MPBGA package diagrams (Figure 6 on page30 and Figure 7 on page31).Added Figure 11 on page46,Figure 12 on page46,Figure 14 on page47, and Figure 15 on page48 to distinguish 80960JT 3.3-V and 5-V signal derating curves from the 80960JA/JF/JD derating curves.March 1998001This datasheet supersedes revisions to the following 80960Jx datasheets: #273109 (JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to combining the documents into one, the following content was changed: Figure 1 on page7: Added MPBGA package to diagram.Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page30: Added new Figures 6 and 7, Tables 10, 11 and 13.Figure 16 on page48: Added with the note that follows the figure.August 2004006To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor1.0IntroductionThis document contains information for the 80960Jx microprocessors, including electrical characteristics and package pinout information. Detailed functional descriptions, other than parametric performance, are published in the i960® Jx Microprocessor Developer’s Manual(272483) and may be viewed online at /design/i960/Techinfo/80960JX/.Throughout this datasheet, references to ‘80960Jx’ indicate features that apply to the 3.3-V Jx processors only:Figure 1. 80960Jx Microprocessor Package Optionsi960®iM©19xxx80960JXXXXXXXXX SS132-Pin PQFPTable 1. 80960Jx 3.3-V Microprocessor FamilyProcessor Voltage Instruction Cache Data Cache Core Clock80960JA 3.3 V (5 V Tolerant) 2 Kbyte 1 Kbyte 1x 80960JF 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 1x 80960JD 3.3 V (5 V Tolerant) 4 Kbyte 2 Kbyte 2x 80960JS 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 1x 80960JC 3.3 V (5 V Tolerant)16 Kbyte 4 Kbyte 2x 80960JT3.3 V (5 V Tolerant)16 Kbyte4 Kbyte3xNOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".This page intentionally left blank.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor 2.080960Jx OverviewThe 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications.The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustainedexecution at the rate of one instruction per clock. This processor’s features include generousinstruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism anddual-programmable timer units.The 80960Jx processor’s clock multiplication operates the processor core at two or three times thebus clock rate to improve execution performance without increasing the complexity of boarddesigns.Memory subsystems for cost-sensitive embedded applications often impose substantial wait statepenalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPUexecution from the external bus.The 80960Jx rapidly allocates and de-allocates local register sets during context switches. Theprocessor must flush a register set to the stack only when it saves more than seven sets to its localregister cache.A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A fullcomplement of control signals simplifies the connection of the 80960Jx to external components.The user programs physical and logical memory attributes through memory-mapped controlregisters (MMRs), an extension not found on the i960® Kx, Sx or Cx processors. Physical andlogical configuration registers enable the processor to operate with all combinations of bus widthand data object alignment. The processor supports a homogeneous byte ordering model.This processor integrates two important peripherals: a timer unit and an interrupt controller. Theseand other hardware resources are programmed through memory-mapped control registers, anextension to the familiar i960 processor architecture.The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks andgeneral-purpose system timing. These operate in either single-shot or auto-reload mode and maygenerate interrupts.The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. TheICU takes advantage of a cached priority table and optional routine caching to minimize interruptlatency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% comparedto the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% comparedto the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reducelatency. Acting independently from the core, the ICU compares the priorities of posted interruptswith the current process priority, off-loading this task from the core. The ICU also supports theintegrated timer interrupts.The 80960Jx features a Halt mode designed to support applications where low power consumptionis critical. The halt instruction shuts down instruction execution, resulting in a power savings of upto 90 percent.The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and BoundaryScan (JTAG), provide a powerful environment for design debug and fault diagnosis.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit MicroprocessorThe Solutions960® program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.2.180960 Processor CoreThe 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this processor core as a very high performance device that is also cost-effective. Factors that contribute to the core ’s performance include:•Core operates at the bus speed with the 80960JA/JF/JS•Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,respectively•Single-clock execution of most instructions •Independent Multiply/Divide Unit•Efficient instruction pipeline minimizes pipeline break latency•Register and resource scoreboarding allow overlapped instruction execution •128-bit register bus speeds local register caching •Two-way set associative, integrated instruction cache •Direct-mapped, integrated data cache•1-Kbyte integrated data RAM delivers zero wait state program dataFigure 2. 80960Jx Block DiagramProgrammable Interrupt Controller Control Address/Instruction SequencerPhysical Region Configuration Interrupt Port1K Data RAMMemory Interface Execution Multiply UnitDivide UnitMemory-Mapped Register InterfaceData BusGlobal / Local Register FileSRC2DESTSRC1addressControleffective ConstantsGenerationUnitAddress 32-bit Address 32-bit DataBus Request Queuesand Two 32-BitTimers8-SetLocal Register CacheS R C 1S R C 2D E S TPLL, Clocks,Power MgmtBoundary Scan ControllerTAP 5CLKINS R C 1S R C 2D E S TS R C 1D E S T93232-bit buses address / data21Instruction Cache 80960JA - 2K 80960JF/JD - 4K80960JS/JC/JT - 16KDirect Mapped Data Cache 80960JA - 1K 80960JF/JD - 2K 80960JS/JC/JT -1283 Independent 32-Bit SRC1, SRC2, and DEST BusesBus Control Unit80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.2Burst BusA 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memoryand peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bitwords per six clock cycles. The external address/data bus is multiplexed.Users may configure the 80960Jx’s bus controller to match an application’s fundamental memoryorganization. Physical bus width is register-programmed for up to eight regions. Byte ordering anddata caching are programmed through a group of logical memory templates and a defaults register.The BCU’s features include:•Multiplexed external bus to minimize pin count•32-, 16-, and 8-bit bus widths to simplify I/O interfaces•External ready control for address-to-data, data-to-data and data-to-next-address wait state types•Support for big or little endian byte ordering to facilitate the porting of existing program code•Unaligned bus accesses performed transparently•Three-deep load/store queue to decouple the bus from the coreUpon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, itperforms an external bus confidence test by performing a checksum on the first words of theinitialization boot record (IBR).2.3Timer UnitThe timer unit (TU) contains two independent 32-bit timers that are capable of counting at severalclock rates and generating interrupts. Each is programmed by use of the TU registers. Thesememory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shotmode and auto-reload capabilities for continuous operation. Each timer has an independentinterrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault whenunauthorized writes from user mode are detected. Clock prescaling is supported.2.4Priority Interrupt ControllerA programmable interrupt controller manages up to 240 external sources through an 8-bit externalinterrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channelsand a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their prioritylevels relative to the current process priority.Low interrupt latency is critical to many embedded applications. As part of its highly flexibleinterrupt mechanism, the 80960Jx exploits several techniques to minimize latency:•Interrupt vectors and interrupt handler routines may be reserved on-chip.•Register frames for high-priority interrupt handlers may be cached on-chip.•The interrupt stack may be placed in cacheable memory space.•Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and 80960JT, respectively.80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor2.5Instruction Set SummaryThe 80960Jx adds several new instructions to the i960 processor core architecture. The newinstructions are:•Conditional Move•Conditional Add•Conditional Subtract•Byte Swap•Halt•Cache Control•Interrupt ControlTable 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx MicroprocessorDeveloper’s Manual (272483) for a detailed description of each instruction.2.6Faults and DebuggingThe 80960Jx employs a comprehensive fault model. The processor responds to faults by makingimplicit calls to a fault handling routine. Specific information collected for each fault allows thefault handler to diagnose exceptions and recover appropriately.The processor also has built-in debug capabilities. In software, the 80960Jx may be configured todetect as many as seven different trace event types. Alternatively, mark and fmark instructionsmay generate trace events explicitly in the instruction stream. Hardware breakpoint registers arealso available to trap on execution and data addresses.2.7Low Power OperationIntel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’ssub-micron topology provides the circuit density for optimal cache size and high operating speedswhile dissipating modest power. The processor also uses dynamic power management to turn offclocks to unused circuits.Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,the processor core stops completely while the integrated peripherals continue to function, reducingoverall power requirements up to 90 percent. Processor execution resumes from internally orexternally generated interrupts.2.8Test FeaturesThe 80960Jx incorporates numerous features that enhance the user’s ability to test both theprocessor and the system to which it is attached. These features include ONCE (On-CircuitEmulation) mode and Boundary Scan (JTAG).80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor The 80960Jx provides testability features compatible with IEEE Standard Test Access Port andBoundary Scan Architecture (IEEE Std. 1149.1).One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins(ONCE mode). ONCE mode may also be initiated at reset without using the boundary scanmechanism.ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx toelectrically “remove” itself from a circuit board. This allows for system-level testing in which aremote tester, such as an in-circuit emulator, may exercise the processor system.The provided test logic does not interfere with component or circuit board behavior and ensuresthat components function correctly, connections between various components are correct, andvarious components interact correctly on the printed circuit board.The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.It may examine connections that might otherwise be inaccessible to a test system.2.9Memory-Mapped Control RegistersThe 80960Jx, although compliant with the i960 processor core, has the added advantage ofmemory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. Theseregisters give software the interface to easily read and modify internal control registers.Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplishedthrough regular memory-format instructions. The processor ensures that these accesses do notgenerate external bus cycles.2.10Data Types and Memory Addressing ModesAs with all i960 processors, the 80960Jx instruction set supports several data types and formats:•Bit•Bit fields•Integer (8-, 16-, 32-, 64-bit)•Ordinal (8-, 16-, 32-, 64-bit unsigned integers)•Triple word (96 bits)•Quad word (128 bits)The 80960Jx provides a full set of addressing modes for C and assembly programming:•Two Absolute modes•Five Register Indirect modes•Index with displacement•IP with displacement。
