SN74LS256D中文资料

5-421FAST AND LS TTL DATADUAL 4-BIT

ADDRESSABLE LATCH

The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common controlinputs; these include two Address inputs (A0, A1), an active LOW Enable input(E) and an active LOW Clear input (CL). Each latch has a Data input (D) andfour outputs (Q0–Q3).When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs(Q0–Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) andE are both LOW. When CL is HIGH and E is LOW, the selected output(Q0–Q3), determined by the Address inputs, follows D. When the E goesHIGH, the contents of the latch are stored. When operating in the addressablelatch mode (E=LOW, CL=HIGH), changing more than one bit of the Address(A0, A1) could impose a transient wrong address. Therefore, this should bedone only while in the memory mode (E=CL=HIGH).

•Serial-to-Parallel Capability•Output From Each Storage Bit Available•Random (Addressable) Data Entry•Easily Expandable•Active Low Common Clear•Input Clamp Diodes Limit High Speed Termination Effects14131211109

1

23

45671615

8VCC

A0CLEDbQ3bQ1bQ2bQ0b

A1DaQ0aQ1aQ2aQ3aGNDCONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.

PIN NAMESLOADING (Note a)HIGHLOW

A0

, A

1

Address Inputs0.5 U.L.0.25 U.L.Da, DbData Inputs0.5 U.L.0.25 U.L.EEnable Input (Active LOW)1.0 U.L.0.5 U.L.CLClear Input (Active LOW)0.5 U.L.0.25 U.L.Q0a–Q3a,Q0b–Q3bParallel Latch Outputs (Note b)10 U.L.5 (2.5) U.L.NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial(74) Temperature Ranges.元器件交易网www.cecb2b.com

5-422FAST AND LS TTL DATASN54/74LS256

LOGIC DIAGRAM

EDaA0A1CLDb

Q0aQ1aQ2aQ3aQ0bQ1bQ2bQ3b1412

673

4591112101315

VCC= PIN 16GND = PIN 8= PIN NUMBERSTRUTH TABLE

CLEDA0A1Q0Q1Q2Q3MODE

LHXXXLLLLClear

LLLLLLLLLDemultiplexLLHLLHLLLLLLHLLLLLLLHHLLHLLLLLLHLLLLLLHLHLLHLLLLHHLLLLLLHHHLLLH

HHXXXQN–1QN–1QN–1QN–1Memory

HLLLLLQN–1QN–1QN–1AddressableHLHLLHQN–1QN–1QN–1LatchHLLHLQN–1LQN–1QN–1HLHHLQN–1HQN–1QN–1HLLLHQN–1QN–1LQN–1HLHLHQN–1QN–1HQN–1HLLHHQN–1QN–1QN–1LHLHHHQN–1QN–1QN–1HH = HIGH Voltage LevelL = LOW Voltage LevelX = ImmaterialMODE SELECTION

ECLMODE

LHAddressable LatchHHMemoryLLDual 4-Channel DemultiplexerHLClear元器件交易网www.cecb2b.com

5-423FAST AND LS TTL DATASN54/74LS256

GUARANTEED OPERATING RANGES

SymbolParameterMinTypMaxUnit

VCCSupply Voltage54744.54.755.05.05.55.25V

TAOperating Ambient Temperature Range5474–550252512570°C

IOHOutput Current — High54, 74–0.4mA

IOLOutput Current — Low54744.08.0mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)Limits

SymbolParameterMinTypMaxUnitTest Conditions

VIHInput HIGH Voltage2.0VGuaranteed Input HIGH Voltage forAll Inputs

V540.7Guaranteed Input LOW Voltage forILInput LOW Voltage740.8VAll Inputs

VIKInput Clamp Diode Voltage–0.65–1.5VVCC = MIN, IIN = –18 mA

VOHOutput HIGH Voltage54, 742.43.5VVCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table

V54, 740.250.4VIOL = 4.0 mAVCC = VCC MIN,OLOutput LOW Voltage740.350.5VIOL = 8.0 mAVIN = VIL or VIHper Truth Table

IIHInput HIGH CurrentOthersE Input2040µAVCC = MAX, VIN = 2.7 V

OthersE Input0.10.2mAVCC = MAX, VIN = 7.0 V

IILInput LOW CurrentOthersE Input–0.4–0.8mAVCC = MAX, VIN = 0.4 V

IOSShort Circuit Current (Note 1)–20–100mAVCC = MAX

ICCPower Supply Current30mAVCC = MAXNote 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)LimitsSymbolParameterMinTypMaxUnitTest Conditions

tPLHtPHLTurn-Off Delay, Enable to OutputTurn-On Delay, Enable to Output20162724nsnsFigure 1

VtPLHtPHLTurn-Off Delay, Data to OutputTurn-On Delay, Data to Output20133020nsnsFigure 2CC = 5.0 V,

tPLHtPHLTurn-Off Delay, Address to OutputTurn-On Delay, Address to Output20143024nsnsFigure 3CL = 15 pF

tPHLTurn-On Delay, Clear to Output1223nsFigure 5元器件交易网www.cecb2b.com

5-424FAST AND LS TTL DATASN54/74LS256

AC SET-UP REQUIREMENTS (TA = 25°C)LimitsSymbolParameterMinTypMaxUnitTest Conditions

tsData Setup Time20ns

tsAddress Setup Time0nsFigures 4 & 6

VthData Hold Time0nsFigure 4CC = 5.0 V

thAddress Hold Time15nsFigure 6

tWEnable Pulse Width15nsFigure 1

tsFigure 1. Turn-on and Turn-off Delays, Enable ToOutput and Enable Pulse Width

Figure 4. Setup and Hold Time, Data to EnableFigure 2. Turn-on and Turn-off Delays,Data to Output

Figure 3. Turn-on and Turn-off Delays,Address to Output

Figure 5. Turn-on Delay, Clear to OutputFigure 6. Setup Time, Address to Enable(See Notes 1 and 2)

NOTES:1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch isaddressed and the other latches are not affected.2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.OTHER CONDITIONS: CL = H, A = STABLEOTHER CONDITIONS: E = L, CL = H, A = STABLE