74LS83中文资料

© 2000 Fairchild Semiconductor Corporation DS006378August 1986Revised March 2000DM74LS83A 4-Bit Binary Adder with Fast CarryDM74LS83A4-Bit Binary Adder with Fast CarryGeneral DescriptionThese full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit.These adders feature full internal look ahead across all four bits. This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.Featuress Full-carry look-ahead across the four bitss Systems achieve partial look-ahead performance with the economy of ripple carry s Typical add timesTwo 8-bit words 25 ns Two 16-bit words 45 nss Typical power dissipation per 4-bit adder 95 mWOrdering Code:Connection DiagramOrder Number Package NumberPackage DescriptionDM74LS83ANN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 2D M 74L S 83ATruth TableH= HIGH Level, L = LOW LevelInput conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs ∑3, ∑4, and C4.Logic DiagramDM74LS83AAbsolute Maximum Ratings (Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation.Recommended Operating ConditionsElectrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)Note 2: All typicals are at V CC = 5V, T A = 25°C.Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.Note 4: I CC1 is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V.Note 5: I CC2 is measured with all outputs OPEN and all inputs grounded.Supply Voltage 7V Input Voltage7VOperating Free Air Temperature Range 0°C to +70°C Storage Temperature Range−65°C to +150°CSymbol ParameterMin Nom Max Units V CC Supply Voltage4.7555.25V V IH HIGH Level Input Voltage 2V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current −0.4mA I OL LOW Level Output Current 8mA T AFree Air Operating Temperature70°CSymbol ParameterConditionsMinTyp Max Units (Note 2)V I Input Clamp Voltage V CC = Min, I I = −18 mA −1.5V V OH HIGH Level V CC = Min, I OH = Max 2.73.4VOutput Voltage V IL = Max, V IH = Min V OLLOW Level V CC = Min, I OL = Max0.350.5Output VoltageV IL = Max, V IH = Min VI OL = 4 mA, V CC = Min 0.250.4I I Input Current @ Max V CC = Max A or B 0.2mA Input Voltage V I = 7V C00.1I IH HIGH Level V CC = Max A or B 40µA Input Current V I = 2.7V C020I IL LOW Level V CC = MaxA orB −0.8mA Input CurrentV I = 0.4VC0−0.4I OS Short Circuit Output Current V CC = Max (Note 3)−20−100mA I CC1Supply Current V CC = Max (Note 4)1934mA I CC2Supply CurrentV CC = Max (Note 5)2239mA 4D M 74L S 83ASwitching Characteristicsat V CC = 5V and T A = 25°CFrom (Input)R L = 2 k ΩSymbol ParameterTo (Output)C L = 15 pF C L = 50 pF UnitsMinMax MinMax t PLH Propagation Delay Time C0 to ∑1 or ∑22428ns LOW-to-HIGH Level Output t PHL Propagation Delay Time C0 to ∑1 or ∑22430ns HIGH-to-LOW Level Output t PLH Propagation Delay Time C0 to ∑32428ns LOW-to-HIGH Level Output t PHL Propagation Delay Time C0 to ∑32430ns HIGH-to-LOW Level Output t PLH Propagation Delay Time C0 to ∑42428ns LOW-to-HIGH Level Output t PHL Propagation Delay Time C0 to ∑42430ns HIGH-to-LOW Level Output t PLH Propagation Delay Time A i , B i to ∑i 2428ns LOW-to-HIGH Level Output t PHL Propagation Delay Time A i , B i to ∑i 2430ns HIGH-to-LOW Level Output t PLH Propagation Delay Time C0 to C41724ns LOW-to-HIGH Level Output t PHL Propagation Delay Time C0 to C41725ns HIGH-to-LOW Level Output t PLH Propagation Delay Time A i , B i to C41724ns LOW-to-HIGH Level Output t PHLPropagation Delay Time A i , B i to C41726ns HIGH-to-LOW Level Output5DM74LS83A 4-Bit Binary Adder with Fast CarryPhysical Dimensions inches (millimeters) unless otherwise noted16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N16EFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。