MSE05_Session_7_Pleskacz
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1MSE’05 Anaheim, California, USA –June 12-13, 2005DefSim –the Educational Integrated Circuit for Defect Simulation
1) Institute of Microelectronics and OptoelectronicsWarsaw University of Technology, POLANDPleskacz@imio.pw.edu.pl2) Department of MicroelectronicsSlovak University of Technology, Bratislavastopjak@elf.stuba.sk
Witold A. Pleskacz1, Tomasz Borejko1, TomaszGugala1, Pawel Pizon1and Viera Stopjakova2
Copyright ©2005 W.A.Pleskacz
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20052Outline•Motivation•Goals•DefSim structure and design•Lab environment•DefSim in a classroom•Conclusions•Future works2
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20053Motivation•ITRS: testing is already one of key problems in current generation of VLSI chips and its importance will be growing.
•There is strong demand for well-educated specialists in the area of IC testing.
•Test techniques should be based on real defects as much aspossible.•Teaching of testing topics is based on abstract models which do not reflect well physical reality. •Simulation alone is not sufficient, “real silicon”is needed forbetter understanding of test problems and for training infault simulation and test pattern generation.
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20054Goals•Development of a VLSI chipproviding practical possibility for students to test real circuits with artificially introducedbut realphysical defects, and in particular:–demonstration of defects thatare not easy to be modeled or for which existing fault models do not follow the real electrical effect of the respective defect precisely,
–testing of simple gates as well as gates embedded in larger digital circuits,
–comparison of theoretical and real defect coverage for various sets oftest vectors,
–demonstration of IDDQtesting and its efficiency,
–making the chip “student-proof”and avoiding possible damage resulting from its operation with intentionally introduced defects.3
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20055VDDGNDQABDC
Example 1AN3cell with IN-OUTshort
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20056Example 2NA2cell with floating gate
VDD
GNDQA
BX4
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20057VDDGNDQA
B
Example 3NA2cell with D-S short(missing poly)
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20058DefSimstructure (1)•DefSimchip consists of two blocks, each block consists of 2 matrices with various digital cells implemented in them (by cellwe mean here either asingle gateor a bigger circuitsuch as ISCAS-85 benchmark circuits).
•Additional circuitry (multiplexers and decoders, etc.) allows addressing and activating selected cells and transmitting their responses to the outputs of the chip.
•Only one cell can be activated at a time.5
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 20059DefSimstructure (2)•Each cell represents combinational fault-free circuit and the same circuit with intentionally injected defects.
•Implemented defects are shorts and opens in metal and poly layers.
•To be close to the silicon reality each cell is loaded and driven by standard non-inverting buffers.
•A built-in current monitor for IDDQtestingis implemented in each block.
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 200510Schematic diagram of block16Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 200511
Implemented Standard Cells•AN1 NOR( AND(A,B) , AND(C,D) )•AN3 NOR( AND(A,B) , C, D)•EN1 XNOR(A,B) = NAND( OR(A,B) , NAND(A,B) )•EO1 XOR(A,B) = NOR( AND(A,B) , NOR(A,B) )•IN1 NOT(A)•NA2 NAND2•NA3 NAND3•NA4 NAND4•NO2 NOR2•NO3 NOR3•NO4 NOR4•NO42 NOR4 = NOT( NAND( NOR(A,B) , NOR(C,D) ) )•ON1 NAND( OR(A,B) , OR(C,D) )•ON3 NAND( OR(A,B) , C, D)
Witold A. PleskaczMSE’05 Anaheim, California, USA –June 12-13, 200512C17ISCAS-85 Benchmark
