74LVT16245MEAX_1368518

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© 2005 Fairchild Semiconductor CorporationDS500152

www.fairchildsemi.com

January 1999Revised June 200574LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs74LVT16245 • 74LVTH16245

Low Voltage 16-Bit Transceiver with 3-STATE Outputs

General Description

The LVT16245 and LVTH16245 contain sixteen non-invert-

ing bidirectional buffers with 3-STATE outputs and is

intended for bus oriented applications. The device is byte

controlled. Each byte has separate control inputs which

can be shorted together for full 16-bit operation. The T/R

inputs determine the direction of data flow through the

device. The OE inputs disable both the A and B ports by

placing them in a high impedance state.

The LVTH16245 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These non-inverting transceivers are designed for low-volt-

age (3.3V) VCC applications, but with the capability to pro-

vide a TTL interface to a 5V environment. The LVT16245

and LVTH16245 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining low power dissipation.Features

sInput and output interface capability to systems at

5V VCC

sBushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16245),

also available without bushold feature (74LVT16245).

sLive insertion/extraction permitted

sPower Up/Down high impedance provides glitch-free

bus loading

sOutputs source/sink 󰀐32 mA/󰀎64 mA

sFunctionally compatible with the 74 series 16245

sLatch-up performance exceeds 500 mA

sESD performance:

Human-body model !2000V

Machine model !200V

Charged-device !1000V

sAlso packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic SymbolOrder NumberPackage

NumberPackage Description

74LVT16245GX

(Note 1)BGA54A

(Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

74LVT16245MEA

(Note 2)MS48A48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16245MTD

(Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74LVTH16245GX

(Note 1)BGA54A

(Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

74LVTH16245MEA

(Note 2)MS48A48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16245MTD

(Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Widewww.fairchildsemi.com274LVT16245 • 74LVTH16245

Connection DiagramsPin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru View)Pin Descriptions

FBGA Pin Assignments

Truth Tables

H HIGH Voltage Level

L LOW Voltage Level

X Immaterial

Z High ImpedancePin NamesDescription

OEnOutput Enable Input (Active LOW)

T/RnTransmit/Receive Input

A0–A15Side A Inputs/3-STATE Outputs

B0–B15Side B Inputs/3-STATE Outputs

NCNo Connect

123456

AB0NCT/R1OE1NCA0

BB2B1NCNCA1A2

CB4B3VCCVCCA3A4

DB6B5GNDGNDA5A6

EB8B7GNDGNDA7A8

FB10B9GNDGNDA9A10

GB12B11VCCVCCA11A12

HB14B13NCNCA13A14

JB15NCT/R2OE2NCA15

Inputs

Outputs

OE1T/R1

LLBus B0–B7 Data to Bus A0–A7

LHBus A0–A7 Data to Bus B0–B7

HXHIGH–Z State on A0–A7,B0–B7

Inputs

Outputs

OE2T/R2

LLBus B8–B15 Data to Bus A8–A15

LHBus A8–A15 Data to Bus B8–B15

HXHIGH–Z State on A8–A15,B8–B153www.fairchildsemi.com74LVT16245

• 74LVTH16245

Functional DescriptionThe LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is bytecontrolled with each byte functioning identically, but independent of the other. The control pins can be shorted together toobtain full 16-bit operation.

Logic Diagrams

Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.www.fairchildsemi.com474LVT16245 • 74LVTH16245

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions

Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.

Note 4: IO Absolute Maximum Ratings must be observed.

DC Electrical CharacteristicsSymbolParameterValueConditionsUnits

VCCSupply Voltage󰀐0.5 to 󰀎4.6V

VIDC Input Voltage󰀐0.5 to 󰀎7.0V

VOOutput Voltage󰀐0.5 to 󰀎7.0Output in 3-STATEV󰀐0.5 to 󰀎7.0Output in HIGH or LOW State (Note 4)

IIKDC Input Diode Current󰀐50VI 󰀟 GNDmA