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54F374中文资料

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54F󰁋74F374

Octal

D-Type

Flip-Flop

with

TRI-STATE

Outputs

May1995

54F󰁋74F374

OctalD-TypeFlip-FlopwithTRI-STATE󰀂Outputs

GeneralDescription

The’F374isahigh-speed󰀷low-poweroctalD-typeflip-flop

featuringseparateD-typeinputsforeachflip-flopand

TRI-STATEoutputsforbus-orientedapplications󰀟Abuff-

eredClock(CP)andOutputEnable(OE)arecommontoall

flip-flops󰀟Features

YEdge-triggeredD-typeinputs

YBufferedpositiveedge-triggeredclock

YTRI-STATEoutputsforbus-orientedapplications

YGuaranteed4000VminimumESDprotection

CommercialMilitaryPackagePackageDescriptionNumber

74F374PCN20A20-Lead(0󰀟300󰀁Wide)MoldedDual-In-Line

54F374DM(QB)J20A20-LeadCeramicDual-In-Line

74F374SC(Note1)M20B20-Lead(0󰀟300󰀁Wide)MoldedSmallOutline󰀷JEDEC

74F374SJ(Note1)M20D20-Lead(0󰀟300󰀁Wide)MoldedSmallOutline󰀷EIAJ

74F374MSA(Note1)MSA2020-LeadMoldedShrinkSmallOutline󰀷EIAJTypeII

54F374FM(QB)W20A20-LeadCerpack

54F374LM(QB)E20A20-LeadCeramicLeadlessChipCarrier󰀷TypeC

Note1󰀌Devicesalsoavailablein13󰀁reel󰀟UsesuffixeSCX󰀷SJX󰀷andMSAX󰀟

LogicSymbolsConnectionDiagrams

TL󰁋F󰁋9524–1

IEEE󰁋IEC

TL󰁋F󰁋9524–4PinAssignmentforDIP󰀸

SOIC󰀸SSOPandFlatpak

TL󰁋F󰁋9524–2PinAssignment

forLCC

TL󰁋F󰁋9524–3

TRI-STATE󰀂isaregisteredtrademarkofNationalSemiconductorCorporation󰀟

C1995NationalSemiconductorCorporationRRD-B30M75󰁋PrintedinU󰀟S󰀟A󰀟元器件交易网www.cecb2b.com

UnitLoading󰁋FanOut

Pin54F󰁋74F

NamesDescriptionU󰀟L󰀟InputIIH󰁋IILHIGH󰁋LOWOutputIOH󰁋IOL

D0–D7DataInputs1󰀟0󰁋1󰀟020mA󰁋b0󰀟6mA

CPClockPulseInput(ActiveRisingEdge)1󰀟0󰁋1󰀟020mA󰁋b0󰀟6mA

OETRI-STATEOutputEnableInput(ActiveLOW)1󰀟0󰁋1󰀟020mA󰁋b0󰀟6mA

O0–O7TRI-STATEOutputs150󰁋40(33󰀟3)b3mA󰁋24mA(20mA)

FunctionalDescription

The’F374consistsofeightedge-triggeredflip-flopswithin-

dividualD-typeinputsandTRI-STATEtrueoutputs󰀟The

bufferedclockandbufferedOutputEnablearecommonto

allflip-flops󰀟Theeightflip-flopswillstorethestateoftheir

individualDinputsthatmeetthesetupandholdtimere-

quirementsontheLOW-to-HIGHClock(CP)transition󰀟With

theOutputEnable(OE)LOW󰀷thecontentsoftheeightflip-

flopsareavailableattheoutputs󰀟WhentheOEisHIGH󰀷the

outputsgotothehighimpedancestate󰀟Operationofthe

OEinputdoesnotaffectedthestateoftheflip-flops󰀟TruthTable

InputsInternalOutput

DnCPOERegisterOn

HLLHH

LLLLL

XXHXZ

HeHIGHVoltageLevelLeLOWVoltageLevelXeImmaterialZeHighImpedanceLeLOW-to-HIGHClockTransition

LogicDiagram

TL󰁋F󰁋9524–5

Pleasenotethatthisdiagramisprovidedonlyfortheunderstandingoflogicoperationsandshouldnotbeusedtoestimatepropagationdelays󰀟

2元器件交易网www.cecb2b.com

AbsoluteMaximumRatings(Note1)

IfMilitary󰁋Aerospacespecifieddevicesarerequired󰀸

pleasecontacttheNationalSemiconductorSales

Office󰁋Distributorsforavailabilityandspecifications󰀟

StorageTemperatureb65󰀃Ctoa150󰀃C

AmbientTemperatureunderBiasb55󰀃Ctoa125󰀃C

JunctionTemperatureunderBiasb55󰀃Ctoa175󰀃C

Plasticb55󰀃Ctoa150󰀃C

VCCPinPotentialto

GroundPinb0󰀟5Vtoa7󰀟0V

InputVoltage(Note2)b0󰀟5Vtoa7󰀟0V

InputCurrent(Note2)b30mAtoa5󰀟0mA

VoltageAppliedtoOutput

inHIGHState(withVCCe0V)

StandardOutputb0󰀟5VtoVCCTRI-STATEOutputb0󰀟5Vtoa5󰀟5V

CurrentAppliedtoOutput

inLOWState(Max)twicetheratedIOL(mA)ESDLastPassingVoltage(Min)4000V

Note1󰀌Absolutemaximumratingsarevaluesbeyondwhichthedevicemaybedamagedorhaveitsusefullifeimpaired󰀟Functionaloperationundertheseconditionsisnotimplied󰀟

Note2󰀌Eithervoltagelimitorcurrentlimitissufficienttoprotectinputs󰀟

RecommendedOperating

Conditions

FreeAirAmbientTemperature

Militaryb55󰀃Ctoa125󰀃C

Commercial0󰀃Ctoa70󰀃C

SupplyVoltage

Militarya4󰀟5Vtoa5󰀟5V

Commerciala4󰀟5Vtoa5󰀟5V

DCElectricalCharacteristics

SymbolParameter54F󰁋74FUnitsVCCConditionsMinTypMax

VIHInputHIGHVoltage2󰀟0VRecognizedasaHIGHSignal

VILInputLOWVoltage0󰀟8VRecognizedasaLOWSignal

VCDInputClampDiodeVoltageb1󰀟2VMinIINeb18mA

VOHOutputHIGH54F10%VCC2󰀟5IOHeb1mA

Voltage54F10%VCC2󰀟4IOHeb3mA

74F10%VCC2󰀟5VMinIOHeb1mA

74F10%VCC2󰀟4IOHeb3mA

74F5%VCC2󰀟7IOHeb1mA

74F5%VCC2󰀟7IOHeb3mA

VOLOutputLOW54F10%VCC0󰀟5VMinIOLe20mA

Voltage74F10%VCC0󰀟5IOLe24mA

IIHInputHIGH54F20󰀟0mAMaxVINe2󰀟7V

Current74F5󰀟0

IBVIInputHIGHCurrent54F100mAMaxVINe7󰀟0V

BreakdownTest74F7󰀟0

ICEXOutputHIGH54F250mAMaxVOUTeVCCLeakageCurrent74F50

VIDInputLeakage74F4󰀟75V0󰀟0IIDe1󰀟9mA

TestAllOtherPinsGrounded

IODOutputLeakage74F3󰀟75mA0󰀟0VIODe150mV

CircuitCurrentAllOtherPinsGrounded

IILInputLOWCurrentb0󰀟6mAMaxVINe0󰀟5V

IOZHOutputLeakageCurrent50mAMaxVOUTe2󰀟7V

IOZLOutputLeakageCurrentb50mAMaxVOUTe0󰀟5V

IOSOutputShort-CircuitCurrentb60b150mAMaxVOUTe0V

IZZBusDrainageTest500mA0󰀟0VVOUTe5󰀟25V

ICCZPowerSupplyCurrent5586mAMaxVOeHIGHZ

3元器件交易网www.cecb2b.com

合集下载

IDT54FCT138CTD中文资料

IDT54FCT138CTD中文资料

FAST CMOS

1-OF-8 DECODER

WITH ENABLE

Integrated Device Technology, Inc.

DESCRIPTION:

The IDT54/74FCT138T/AT/CT are 1-of-8 decoders built

using an advanced dual metal CMOS technology. The IDT54/

74FCT138T/AT/CT accepts three binary weighted inputs (A

0,

A

1, A

2) and, when enabled, provides eight mutually exclusive

active LOW outputs (O

0-O

7). The IDT54/74FCT138T/AT/CT

features three enable inputs, two active LOW (E

1, E

2) and one

active HIGH (E

3). All outputs will be HIGH unless E

1 and E

2 are

LOW and E

3 is HIGH. This multiple enable function allows

easy parallel expansion of the device to a 1-of-32 (5 lines to

32 lines) decoder with just four IDT54/74FCT138T/AT/CT

devices and one inverter.IDT54/74FCT138T/AT/CT

FUNCTIONAL BLOCK DIAGRAM

2570 drw 012570 drw 02

2570 drw 03PIN CONFIGURATIONS

O6INDEX

A

2

O

2A0

NC

VCC

LCC

TOP VIEW322019

1

4

74LS377中文资料

74LS377中文资料

74LS377中文资料:

54/74377

双 2 位 D 触发器

简要说明：

54/74LS377 为八 D 边沿触发器，其主要电特性的典型值如下（具体厂家有

可能不是完全一至）：

型号 fm PD

54/74LS377 40MHz 85mW

当允许控制端/E 为低电平时，时钟端（CP）脉冲上升沿作用下，输出端 Q

与数据端 D 相一致。当 CP 为高电平或者低电平时，D 对 Q 没影响。

引出端符号：

/E 允许控制端（低电平有效）

D0~D7 数据输入端

Q0~Q7 数据输出端

CP 时钟输入端（上升沿有效）

外接管腿;:逻辑图：功能表：

SN54ALS373AJ中文资料

SN54ALS373AJ中文资料

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SDAS083C – APRIL 1982 – REVISED MARCH 2002

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265DEight Latches in a Single Package

D3-State Bus-Driving True Outputs

DFull Parallel Access for Loading

DBuffered Control Inputs

Dpnp Inputs Reduce dc Loading on Data

Lines

description

These octal transparent D-type latches feature

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance

loads. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

IDT54FCT162374ATPF资料

IDT54FCT162374ATPF资料

Integrated Device Technology, Inc.

DESCRIPTION:The FCT16374T/AT/CT/ET and FCT162374T/AT/CT/ET16-bit edge-triggered D-type registers are built using ad-vanced dual metal CMOS technology. These high-speed,low-power registers are ideal for use as buffer registers fordata synchronization and storage. The Output Enable (xOE)and clock (xCLK) controls are organized to operate eachdevice as two 8-bit registers or one 16-bit register withcommon clock. Flow-through organization of signal pins sim-plifies layout. All inputs are designed with hysteresis forimproved noise margin.The FCT16374T/AT/CT/ET are ideally suited for drivinghigh-capacitance loads and low-impedance backplanes. Theoutput buffers are designed with power off disable capabilityto allow "live insertion" of boards when used as backplanedrivers.The FCT162374T/AT/CT/ET have balanced output drivewith current limiting resistors. This offers low ground bounce,minimal undershoot, and controlled output fall times– reduc-ing the need for external series terminating resistors. TheFCT162374T/AT/CT/ET are plug-in replacements for theFCT16374T/AT/CT/ET and ABT16374 for on-board bus inter-face applications.IDT54/74FCT16374T/AT/CT/ETIDT54/74FCT162374T/AT/CT/ETFAST CMOS 16-BITREGISTER (3-STATE)