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GENERAL DESCRIPTION FEATURESCM6502THH is designed to meet 90+ spec. (total efficiency). It has the following key features.1.) 420V bulk capacitor value can be reduced, and alsoPFC Boost Capacitor ripple current can be reduced2.) Turbo Speed PFC may reduce 420 Bulk Capacitorsize further3.) A PGB function is designed for interfacing to nextstage controller or the House Keeping IC atsecondary side. It has a customer programmablelow threshold PGTHL4.) “Remember it was Light Load” function and“Remember it was Full Load” function may reducePFC 420V Bulk Capacitor size further. It boosts thetotal efficiency as well.5.) No Load Consumption can be reduced to 290mW at270VAC6.) Better Power Factor and Better THD7.) Clean Digital PFC Brown Out8.) The stress over the entire external power device isreduced and EMI noise reduced9.) Superior Surge Noise ImmunityCM6502THH is designed to meet the EPA/90+ regulation. With the proper design, its efficiency of power supply can easily approach 90+. Patents Pending23V Bi-CMOS process.Designed for EPA/90+efficiencySelectable Boost output from 380V to 355V during light loadCustomer Programmable the Low Threshold of PGB comparator at PGTHL pin“Remember It was Light Load” function to improve the efficiency“Remember It was Light Load” function to have extra hold-up time @ light loadClean Digital PFC Brown OutAll high voltage resistors can be greater than 5 Mega ohm (5 Mega to 8 Mega ohm) to improve the no load consumption.Rail to rail CMOS Drivers with on, 60 ohm and off, 30 ohm with 17V zeners.Fast Start-UP Circuit without extra bleed resistor to aid VCC reaches 13V sooner.Low start-up current (50uA typ.)Low operating current (2.1mA typ.)Adjustable Long Delay Time for Line Sagging(Up to 2 Second)16.5V VCC shunt regulatorDynamic Soft PFC to ease the stress of the Power Device and Ease the EMI-filter design.Better Power Factor and Better THDAverage current, continuous or discontinuous boost leading edge PFC.Current fed Gain Modulator for improved noise immunity. Gain Modulator is a constant maximum power limiter.Precision Current Limit, over-voltage protection, UVLO, and soft start, and Reference OK.APPLICATIONS PIN CONFIGURATIONEPA/90+ related Power Supply Desktop PC Power Supply Internet Server Power Supply LCD Power Supply PDP Power Supply AC Adaptor IPC Power Supply UPSBattery Charger DC Motor Power Supply Monitor Power SupplyTelecom System Power Supply Distributed PowerDIP-14 (P14) / SOP-14 (S14)TOP View9PGTHL 13IEAO ISS VREF VFB VEAO 12810PFCOUT11VCC RTCTISENSE 21674VRMS 3PGB GND5IAC 14PIN DESCRIPTIONOperating Voltage Pin No.SymbolDescriptionMin. Typ. Max.Unit 1 I EAOPFC transconductance current error amplifier output (Gmi).0 VREFV2 I AC IAC has 2 functions:1. PFC gain modulator reference input.2. At start up, IAC is connected to VCC and it helps to reduce the startup time and it helps to reduce the no load consumption. Typical RAC resistor is about 6 Mega ohm to 8 Mega ohm to sense the line.0 100 uA3 I SENSE PFC Current Sense: for both Gain Modulator and PFC ILIMIT comparator.-1.3 0.7 V 4V RMSLine Input Sense pin for multiplier and also it is the PFC Brown out sense pin.0 6 V5 ISSPFC Soft Start pin: It supplies ~ 10uA to SS pin. It provides a close-loop soft start function during power supply start up. When VFB is lower than PGTHL, PGBcomparator, SS pin is discharged through an internal ~ 145.3K Ohm resistor.PFC Soft Start function can just need a simple capacitor0 VCC V6 PGTHL PGTHL is an input I/O. The user can program the LowThreshold of the Power Good which can determine thecomparator output of PGB (open drain) to be pulled high.0 2.25 V7 RTCT Oscillator timing node; timing set by RT and CT 0.8 4 V 8 GND Ground9 PGB PGB is the PG comparator output. The input of PG comparator is using Vfb (pin 13) to compare with the high threshold, 2.25V (preset internally) and the low threshold, PGTHL (pin 6, Set by user).When 380V is ready, pin 9 is open-drain and it will be pulled low.0 6 V10 PFC OUT PFC driver output 0 VCC V 11 V CCPositive supply for CM6502THH10 15 18 V12 VREFMaximum 3.5mA buffered output for the internal 7.5V reference when VCC=14V7.5 V13 V FBPFC transconductance voltage error amplifier input0 2.5 3 V14 VEAO PFC transconductance voltage error amplifier output(GmV)0 6 VSimplified Block Diagram (CM6502THH)ORDERING INFORMATIONPart Number Temperature Range PackageCM6502THHXIS* -40℃ to 125℃14-Pin Narrow SOP (S14)CM6502THHXISTR* -40℃ to 125℃14-Pin Narrow SOP (S14)CM6502THHXIP* -40℃ to 125℃14-Pin Narrow DIP (P14)*Note: X : Suffix for Halogen Free and PB Free ProductTR : Package is Typing ReelABSOLUTE MAXIMUM RATINGSAbsolute Maximum ratings are those values beyond which the device could be permanently damaged.Parameter Min.Max.UnitsV CC18V IEAO 0VREF+0.3V I SENSE Voltage -5 0.7 VPFC OUT GND – 0.3 VCC + 0.3 VI REF 3.5mAI AC Input Current 1 mAPeak PFC OUT Current, Source or Sink 0.5 APFC OUT, Energy Per Cycle 1.5 μJJunction Temperature 150 ℃Storage Temperature Range -65 150 ℃Operating Temperature Range -40 125 ℃Lead Temperature (Soldering, 10 sec) 260 ℃Thermal Resistance (θJA)Plastic DIP Plastic SOIC 80105℃/W℃/WELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, R T = 5.88K k Ω, C T = 1000pF, T A =Operating Temperature Range (Note 1)CM6502THHSymbol ParameterTest ConditionsMin. Typ. Max.UnitClean Digital PFC Brown Out VRMS Threshold High Room Temperature=25℃ 1.70 1.78 1.88 VVRMS Threshold LowRoom Temperature=25℃ 0.98 1.03 1.1VHystersis 710 760 810 mVAC High/Low line ThresholdSweep Vrms pin3.3253.53.675VVoltage Error Amplifier (g mv )Input Voltage Range0 3 VTransconductance V NONINV = V INV , VEAO = 2.25V @ T=25℃35 50 65μmhoFeedback Reference Voltage (High)SS > VREF and Veao > 2.25V and Vrms<2V2.45 2.52 2.58 VFeedback Reference Voltage (Low)SS > VREF and Veao < 1.75V and Vrms<2V 2.17 2.26 2.35 V Input Bias Current Note 2 -0.1 -0.05 μAOutput High Voltage 5.8 6.0 VOutput Low Voltage0.10.4VSource Current Overdrive Voltage = 100mV @ T=25℃ 1 7μA Sink Current Overdrive Voltage = 100mV @ T=25℃ -55 -28μA Open Loop GainDC gain30 40 dBPower Supply Rejection Ratio11V < V CC < 16.5V6075dBCurrent Error Amplifier (g mi )Input Voltage Range (Isense pin)-1.2 0.7 VTransconductance V NONINV = V INV , IEAO = 1.5V @ T=25℃ 50 67 85μmho Input Offset Voltage VEAO=0V, IAC is open -1010mVOutput High Voltage 6.8 7.3 7.8 VOutput Low Voltage0.1 0.4 VELECTRICAL CHARACTERISTICS :(Unless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, R T = 5.88K kΩ, C T = 1000pF,T A=Operating Temperature Range (Note 1)CM6502THHSymbol Parameter TestConditionsMin. Typ. Max.Unit SinkCurrent I SENSE = -0.5V, IEAO = 1.5V -40 -34 -28μA SourceCurrent I SENSE = +0.5V, IEAO = 4.0V 25 33 40μA Open Loop Gain DC Gain 30 40 dBPower Supply Rejection Ratio 11V < V CC < 16.5V 60 75 dBPFC OVP ComparatorThresholdVoltage 2.7 2.85 3 V Hysteresis 200 320 mV PFC Green Power Detect ComparatorVeao Threshold Voltage 0.14 0.28 0.4 VTri-Fault DetectFault Detect HIGH 2.7 2.85 3 VTime to Fault Detect HIGH V FB=V FAULT DETECT LOW toV FB=OPEN, 470pF from V FB to GND2 4 msFault Detect LOW 0.1 0.28 0.4 VPFC I LIMIT ComparatorThresholdVoltage -1.38 -1.28 -1.18 V(PFCI LIMIT– Gain Modulator Output) 300450mVDelay to Output (Note 4) Overdrive Voltage = -100mV 700 nsPGTHLPGB_CMP_HIGH PGTHL=2V 2.14 2.25 2.36 V PGB_CMP_LOW PGTHL=2V 1.88 2.07 V Hystersis 100 350 mV Offset -3535mV Remember Full-Load Threshold 1.94 2.02 VRemember Light-Load Threshold 1.82 1.9 VELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, R T = 5.88K kΩ, C T = 1000pF, T A=Operating Temperature Range (Note 1)CM6502THHSymbol Parameter TestConditionsMin. Typ. Max.Unit GAIN ModulatorGain1 (Note 3) I AC = 20μA, V RMS =1.125, V FB = 2.375V @T=25℃ SS<VREF4.45.56.6Gain2 (Note 3 ) I AC = 20μA, V RMS = 1.45588V, V FB=2.375V @ T=25℃ SS<VREF4 5 6Gain3 (Note 3) I AC = 20μA, V RMS =2.91V, V FB = 2.375V @T=25℃ SS<VREF0.88 1.1 1.32Gain4 (Note 3) I AC = 20μA, V RMS = 3.44V, V FB = 2.375V@ T=25℃ SS<VREF0.72 0.9 1.08Bandwidth (Note 4) I AC = 40μA 1 MHzOutput Voltage = Rmul * (I SENSE-I OFFSET) I AC = 50μA, V RMS = 1.125V, V FB = 2.375VSS<VREF0.75 0.8 0.85 VOscillator (Measuring fpfc)Initial fpfc Accuracy 1 R T = 5.88 kΩ, C T = 1000pF, T A = 25℃IAC=0uA64 68 72 kHzVoltage Stability 11V < V CC < 16.5V 2 %TemperatureStability 2 % Ramp Valley to Peak Voltage VEAO=6V and IAC=20uA 2.5 VPFC Dead Time (Note 4) 550 950 nsCT Discharge Current V RAMP2 = 0V, V RAMP1 = 2.5V 10 11 12 mALight Load Veao ThresholdLight Load Threshold (High) Room Temperature=25℃ 2.38 2.5 2.62 VLight Load Threshold (Low) Room Temperature=25℃ 1.9 2 2.1 VHysteresis 400 500 600 mVELECTRICAL CHARACTERISTICSUnless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, R T = 5.88K kΩ, C T = 1000pF,T A=Operating Temperature Range (Note 1)CM6502THHUnitSymbol Parameter Test ConditionsMin. Typ. Max.ReferenceVoltage T A = 25℃, I(VREF) = 0mA 7.3 7.5 7.7 V OutputRegulation 11V < V CC < 16.5V@ T=25℃ 3 5 mV LineVCC=10.5V,0mA < I(VREF) < 2.0mA;25 50 mV@ T=25℃Load RegulationVCC=14V,0mA < I(VREF) < 3.5mA;25 50 mVT A = -40℃~85℃Stability 0.4 % TemperatureTotal Variation Line, Load, Temp 7.3 7.7 VmV Long Term Stability T J = 125℃, 1000HRs 5 25PFCMinimum Duty Cycle IEAO > 4.5V 0 %Maximum Duty Cycle V IEAO < 1.2V 93 95 %I OUT = -20mA @ T=25℃ 11.8 18 ohmI OUT = -100mA @ T=25℃18Output Low RdsonohmI OUT = 10mA, V CC = 9V @ T=25℃ 0.5 1 VI OUT = 20mA @ T=25℃ 24 40 ohmOutput High RdsonI OUT = 100mA @ T=25℃40ohm Rise/Fall Time (Note 4) C L = 100pF @ T=25℃ 50 ns Soft StartμA Soft Start Current Room Temperature=25℃7 10 12μA Soft Start Discharge Current Vrms=0.926V, Soft Start=8V 1 3.5SupplyμA Start-UpCurrent V CC = 12V, C L = 0 @ T=25℃ 50 65 Operating Current 14V, C L = 0 2.35 3.5 mATurn-On Undervoltage Lockout Threshold CM6502THH 12.35 12.85 13.65 VTurn-Off Undervoltage Lockout Hysteresis CM6502THH 2.8 2.95 3.1 V Shunt Regulator (VCC zener)Zener Threshold Voltage Apply VCC with Iop=20mA 16.15 17 17.85 VNote 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.Note 2: Includes all bias currents to other circuits connected to the V FB pin.Note 3: Gain ~ K x 5.3V; K = (I SENSE – I OFFSET) x [I AC (VEAO – 0.7)]-1; VEAO MAX = 6VNote 4: Guaranteed by design, not 100% production test.Getting Start:To start evaluating CM6502THH from the exiting CM6800 or ML4800 board, 6 things need to be taken care before doing the fine tune:1.) Change RAC resistor (on pin 2, IAC) from the old valueto a higher resistor value between 6 Mega ohms to 8 Mega ohms. Start with 6 Mega ohm first.2.) Change RTCT pin (pin 7) from the existing value toRT=5.88K ohm and CT=1000pF to have fpfc=68Khz, fRTCT=272Khz for CM6502THH.3.) Adjust all high voltage resistor around 5 mega ohm orhigher.4.) VRMS pin (pin 4) needs to be 1.1V at VIN=80Vac rightbefore PFC brown out and to be 1.70V at VIN=85VAC right before PFC brown in for universal input application for line input from 85VAC to 270VAC.5.)At full load, the average Veao needs to be around 4.5Vand the ripple on the Veao needs to be less than 250mV when the light load comparator are triggered.6.) Soft Start pin (pin 5), the soft start current has beenreduced from CM6800’s 20uA to CM6502THH’s 10uA.Soft Start capacitor can be reduced to 1/2 from your original CM6800 capacitor.Functional DescriptionCM6502THH is designed for high efficient power supply for both full load and light load. It is a ZVS-Like PFC supply controller.The CM6502THH is an average current controlled, continuous/discontinuous boost Power Factor Correction (PFC) which uses leading edge modulation.In addition to power factor correction, a number of protection features have been built into the CM6502THH. These include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. Power Factor CorrectionPower factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved.To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the CM6502THH uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC rms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10VAC on a 385V DC level); from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/(Vin x Vin), which linearizes the transfer function of the system as the AC input to voltage varies.Since the boost converter topology in the CM6502THH PFC isof the current-averaging type, no slope compensation is required. More exactly, the output current of the gain modulator is given by:Gain=Imul/IacK=Gain/(VEAO-0.7V)I mul = K x (VEAO – 0.7V) x I ACDynamic Soft PFC (patent pending)Dynamic Soft PFC is one of the main feature of CM6502THH. Dynamic Soft PFC is to improve the efficiency, to reduce power device stress, to ease EMI, and to ease the monotonic output design while it has the more protection such as the short circuit with power-foldback protection. Its unique sequential control maximizes the performance and the protections among steady state, transient and the power on/off conditions.PFC Section: Gain ModulatorFigure 1 shows a block diagram of the PFC section of the CM6502THH. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltages. There are three inputs to the gain modulator. These are:1. A current representing the instantaneous input voltage (amplitude and wave-shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at I AC . Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current.2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output isinversely proportional to V RMS 2. The relationship between V RMS and gain is illustrated in the Typical Performance Characteristics of this page.3. The output of the voltage error amplifier, VEAO. The gainmodulator responds linearly to variations in this voltage.The output of the gain modulator is a current signal, in theform of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general formula of the output of the gain modulator is:I mul =2RMSAC V 0.7V)-VEAO I (×x constant(1)Where K is in units of [V -1]Note that the output current of the gain modulator is limited around 140μA and the maximum output voltage of the gain modulator is limited to 140uA x 5.7K=0.8V. This 0.8V also will determine the maximum input power.However, I GAINMOD cannot be measured directly from I SENSE . I SENSE = I GAINMOD -I OFFSET and I OFFSET can only be measured when VEAO is less than 0.5V and I GAINMOD is 0A. Typical I OFFSET is around 25uA.IAC=20uA, Veao=6V Gain vs. VRMS (pin4) When VRMS below 1V, the PFC is shut off. Designer needs to design 80VAC with VRMS average voltage= 1.14V.AC MUL AC OFFSET SENSE I I I I I =−=GainSelecting R AC for IAC pin IAC pin is the input of the gain modulator. IAC also is a current mirror input and it requires current input. By selecting a proper resistor R AC , it will provide a good sine wave current derived from the line voltage and it also helps program the maximum input power and minimum input line voltage.R AC =Vin min peak x 50K. For example, if the minimum line voltage is 85VAC, the R AC =85 x 1.414 x 50K = 6.0 Mega ohm.Vrms Description:VRMS pin is designed for the following functions:1. VRMS is used to detect the AC Brown Out (Also, wecan call it Clean Digital PFC brown out.). When VRMS is less than 1.03 V +/-5%, PFCOUT will be turned off and VEAO will be softly discharged. When VRMS is greater than 1.78V +/-5%, PFCOUT is enabled and VEAO is released.Current Error Amplifier, IEAO The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductora linear function of the line voltage. At the inverting input tothe current error amplifier, the output current of the gain modulator is summed with a current which results from anegative voltage being impressed upon the I SENSE pin. The negative voltage on I SENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier.In higher power applications, two current transformers aresometimes used, one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its dutycycle until the voltage on I SENSE is adequately negative to cancel this increased current. Similarly, if the gainmodulator’s output decreases, the output duty cycle willdecrease, to achieve a less negative voltage on the I SENSEpin.Error Amplifier CompensationThe PWM loading of the PFC can be modeled as anegative resistor; an increase in input voltage to the PWMcauses a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to V REF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on I EAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter.Clean Digital PFC Brown OutClean Digital PFC Brown Out provides a clean cut off when AC input is much lower than regular AC input voltage such as 67Vac. Inside of Clean Digital PFC Brown Out, there is a comparator monitors the Vrms (pin 4) voltage. Clean Digital PFC Brown Out inhibits the PFC and Veao (PFC error amplifier output) is pulled down when the Vrms is lower than off threshold, 1.04V (The off Vin voltage usually corresponds to 70Vac). When the Vrms voltage reaches 1.75V (The On Vin voltage usually corresponds to 86.62V and when Vin = 80Vac, Vrms = 1.14V), PFC is on. Before PFC is turned on, Vrms (pin 4) represents the peak voltage of the AC input. Before PFC is turned off, Vrms (pin 4)represents the Vrms voltage of the AC input.Cycle-By-Cycle Current Limiter andSelecting R SENSE The I SENSE pin, as well as being a part of the current feedbackloop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than –1.25V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of thenext PFC power cycle.R S is the sensing resistor of the PFC boost converter. During the steady state, line input current x R SENSE = I mul x 5.7K. Sincethe maximum output voltage of the gain modulator is I mul max x5.7K= 0.8V during the steady state, RSENSE x line input current willbe limited below 0.8V as well. When VEAO reaches maximum VEAO which is 6V, Isense can reach 0.8V. At 100% load, VEAO should be around 4.5V and ISENSE average peak is 0.6V. It will provide the optimal dynamic response + tolerance of thecomponents.Therefore, to choose R SENSE , we use the following equation: R SENSE + R Parasitic =0.6V x Vinpeak / (2 x Line Input power)For example, if the minimum input voltage is 80VAC, and the maximum input rms power is 200Watt, R SENSE + R Parasitic = (0.6V x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer needs to consider the parasitic resistance and the margin of the powersupply and dynamic response. Assume R Parasitic = 30 mOhm,R SENSE = 139 mOhm.PFC OVP In the CM6502THH, PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.79V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.54V. The VFB power components and the CM6502THH are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop.PFC Voltage LoopThere are two major concerns when compensating the voltage loop error amplifier, V EAO ; stability and transientresponse. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency).deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier, GMv will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristics. The Voltage Loop Gain (S)CVV DC EAO 2OUTDC IN FBEAOOUT FB EAO OUT Z *GM *C *S *ΔV *V 2.5V*P ΔV ΔV *ΔV ΔV *ΔV ΔV ≈=Z CV : Compensation Net Work for the Voltage Loop GM v : Transconductance of VEAO P IN : Average PFC Input PowerV OUTDC : PFC Boost Output Voltage; typical designed value is 380V.C DC : PFC Boost Output CapacitorPFC Current LoopThe current transcondutance amplifier, GMi, I EAO compensation is similar to that of the voltage error amplifier, V EAO with exception of the choice of crossover frequency. The crossover frequency of thecurrent amplifier should be at least 10 times that ofthe voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 8.33kHz for a 50kHz switching frequency.The Current Loop Gain (S)CI I S OUTDC SENSE EAOEAO OFF OFFISENSE Z *GM *2.5V*L *S R *V ΔI ΔI *ΔI ΔD *ΔD ΔV ≈=Z CI : Compensation Net Work for the Current Loop GM I : Transconductance of IEAOV OUTDC :PFC Boost Output Voltage; typical designed value is 380V and we use the worst condition to calculate the Z CI R SENSE : The Sensing Resistor of the Boost Converter2.5V:The Amplitude of the PFC Leading Edge Modulation Ramp(typical)L: The Boost InductorThe gain vs. input voltage of the CM6502THH’s voltage error amplifier, V EAO has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier, GMv is at a local minimum. Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (V FB ) toI SENSE Filter, the RC filter between R SENSE and I SENSE : There are 2 purposes to add a filter at I SENSE pin:1.) Protection: During start up or inrush current conditions, it will have a large voltage cross Rs which is the sensing resistor of the PFC boost converter. It requires the I SENSE Filter to attenuate the energy.2.) To reduce L, the Boost Inductor: The I SENSE Filter To reduceL, the Boost Inductor: The I SENSE Filter also can reduce the Boost Inductor value since the I SENSE Filter behaves like an integrator before going I SENSE which is the input of the current error amplifier, IEAO.The I SENSE Filter is a RC filter. The resistor value of the I SENSE Filter is 100 ohm because I OFFSET x the resistor can generate an offset voltage of IEAO. By selecting R FILTER equal to 100ohm will keep the offset of the IEAO less than 10mV. Usually, we design the pole of I SENSE Filter at fpfc/6=8.33Khz, one sixth of the PFC switching frequency. Therefore, the boost inductor can be reduced 6 times without disturbing the stability. Therefore, the capacitor of the I SENSE Filter, C FILTER , will be around 190.5nF.。

PRELIMINARY36-Mbit DDR-II SRAM 2-WordBurst ArchitectureCY7C1416AV18CY7C1427AV18CY7C1418AV18CY7C1420AV18Features•36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)•250-MHz clock for high bandwidth•2-Word burst for reducing address bus frequency •Double Data Rate (DDR) interfaces(data transferred at 500 MHz) @ 250 MHz•Two input clocks (K and K) for precise DDR timing —SRAM uses rising edges only•Two output clocks (C and C) account for clock skew and flight time mismatching•Echo clocks (CQ and CQ) simplify data capture in high-speed systems•Synchronous internally self-timed writes•1.8V core power supply with HSTL inputs and outputs •Variable drive HSTL output buffers •Expanded HSTL output voltage (1.4V–V DD )•15 x 17 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix)•JTAG 1149.1 compatible test access port•Delay Lock Loop (DLL) for accurate data placementConfigurationsCY7C1416AV18 – 4M x 8CY7C1427AV18 – 4M x 9CY7C1418AV18 – 2M x 18CY7C1420AV18 – 1M x 36Functional DescriptionThe CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1416AV18 and two 9-bit words in the case of CY7C1427AV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1416AV18 and CY7C1427AV18. On CY7C1418AV18 and CY7C1420AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418AV18 and two 36-bit words in the case of CY7C1420AV18 sequentially into or out of the device.Asynchronous inputs include impedance match (ZQ).Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design.Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.Selection Guide250 MHz200 MHz 167 MHz Unit Maximum Operating Frequency 250200167MHz Maximum Operating CurrentTBDTBDTBDmAShaded areas contain advance information.PRELIMINARYCY7C1418AV18CY7C1420AV18Logic Block Diagram (CY7C1416AV18)CLK A (20:0)Gen.K K Control LogicAddress RegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [7:0]Output Logic Reg.Reg.Reg.88168NWS [1:0]V REF W r i t e A d d . D e c o d e8CC 8LDControl212M x 8 Array2M x 8 ArrayWrite Reg Write Reg CQCQ R/W DOFFLogic Block Diagram (CY7C1427AV18)CLK A (20:0)Gen.K K Control LogicAddress RegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [8:0]Output Logic Reg.Reg.Reg.99189BWS [0]V REF W r i t e A d d . D e c o d e9CC 9LDControl212M x 9 Array2M x 9 ArrayWrite Reg Write Reg CQCQ R/W DOFFPRELIMINARYCY7C1418AV18CY7C1420AV182M x 18 ArrayWrite RegWrite Reg Logic Block Diagram (CY7C1418AV18)CLK A (20:0)Gen.K K Control LogicAddressRegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [17:0]Output Logic Reg.Reg.Reg.18183618BWS [1:0]V REF W r i t e A d d . D e c o d e1821CC 18LD ControlBurst LogicA0A (20:1)20CQ CQR/W DOFFLogic Block Diagram (CY7C1420AV18)CLK A (19:0)Gen.K K Control LogicAddressRegisterR e a d A d d . D e c o d eRead Data Reg.R/W DQ [35:0]Output Logic Reg.Reg.Reg.36367236BWS [3:0]V REF W r i t e A d d . D e c o d e3620CC 36LD ControlBurst LogicA0A (19:1)191M x 36 ArrayWrite RegWrite Reg CQCQ36R/W DOFFPRELIMINARY CY7C1418AV18 CY7C1420AV18Pin ConfigurationsCY7C1416AV18 (4M × 8) – 15 × 17 FBGA234567 1ABCDEFGHJKLMNP RACQNCNCNCNCDOFFNCNC/72M A NWS1 KR/W NC/144MNC NCNCNCNCTDONCNCNCNCNCNCTCKNCNCA NC/288M K NWS0V SS A A ANC V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ4NCV DDQNCNCNCNCDQ7AV DDQ V SSV DDQ V DD V DDDQ5V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AANC V SSNC V SSNCNCV REFV SSV DDV SSV SSAV SSCNCDQ6NCNCNCV DDA891011NCA ALD CQA NC NC DQ3V SS NC NC NCNCV SS NCDQ2NCNCNCV REFNCNCV DDQ NCV DDQ NC NCV DDQV DDQV DDQNCV DDQ NC DQ1NCV DDQV DDQ NCV SS NC NCNCTDITMSV SSA NCANCNCNCZQNCDQ0NCNCNCNCACY7C1427AV18 (4M × 9) – 15 × 17 FBGA2345671A B C D E F G H J K L M NP RACQNCNCNCNCDOFFNCNC/72M A NC KR/W NC/144MNC NCNCNCNCTDONCNCNCNCNCNCTCKNCNCA NC/288M K BWS0V SS A A ANC V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ4NCV DDQNCNCNCNCDQ7AV DDQ V SSV DDQ V DD V DDDQ5V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AANC V SSNC V SSNCNCV REFV SSV DDV SSV SSAV SSCNCDQ6NCNCNCV DDA891011DQ8A ALD CQA NC NC DQ3V SS NC NC NCNCV SS NCDQ2NCNCNCV REFNCNCV DDQ NCV DDQ NC NCV DDQV DDQV DDQNCV DDQ NC DQ1NCV DDQV DDQ NCV SS NC NCNCTDITMSV SSA NCANCNCNCZQNCDQ0NCNCNCNCAPRELIMINARY CY7C1418AV18 CY7C1420AV18Pin Configurations (continued)CY7C1418AV18 (2M × 18) – 15 × 17 FBGA2345671ABCDEFGHJKLMNP RACQNCNCNCNCDOFFNCNC/72M A BWS1 KR/W NC/144MDQ9NCNCNCNCTDONCNCNCNCNCNCTCKNCNCA NC/288M K BWS0V SS A A0ADQ10V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ11NCV DDQNCDQ14NCDQ16DQ17AV DDQ V SSV DDQ V DD V DDDQ13V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AANC V SSNC V SSDQ12NCV REFV SSV DDV SSV SSAV SSCNCDQ15NCNCNCV DDA891011DQ0A ALD CQA NC NC DQ8V SS NC DQ7NCNCV SS NCDQ6NCNCNCV REFNCDQ3V DDQ NCV DDQ NC DQ5V DDQV DDQV DDQNCV DDQ NC DQ4NCV DDQV DDQ NCV SS NC NCNCTDITMSV SSA NCANCNCNCZQNCDQ2NCDQ1NCNCA2345671A B C D E F G H J K L M NP RACQNCNCNCNCDOFFNCNC/144M A BWS2 KR/W BWS1DQ27DQ18NCNCNCTDONCNCDQ31NCNCNCTCKNCDQ28A BWS3K BWS0V SS A A0ADQ19V SSV SS V SSV SSV DDAV SSV SSV SSV DDDQ20DQ21V DDQDQ32DQ23DQ34DQ25DQ26AV DDQ V SSV DDQ V DD V DDDQ22V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AADQ29V SSNC V SSDQ30NCV REFV SSV DDV SSV SSAV SSCNCDQ33NCDQ35DQ24V DDA891011DQ0A NC/72MLD CQA NC NC DQ8V SS NC DQ17DQ7NCV SS NCDQ6DQ14NCNCV REFNCDQ3V DDQ NCV DDQ NC DQ5V DDQV DDQV DDQDQ4V DDQ NC DQ13NCV DDQV DDQ NCV SS NC DQ1NCTDITMSV SSA NCADQ16DQ15NCZQDQ12DQ2DQ10DQ11DQ9NCACY7C1420AV18 (1M × 36) – 15 × 17 FBGAPRELIMINARY CY7C1418AV18 CY7C1420AV18Pin DefinitionsPin Name I/O Pin DescriptionDQ[x:0]Input/Output-Synchronous Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically three-stated. CY7C1416AV18 − DQ[7:0]CY7C1427AV18 − DQ[8:0]CY7C1418AV18 − DQ[17:0]CY7C1420AV18 − DQ[35:0]LD Input-Synchronous Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and Read/Write direction. All transactions operate on a burst of 2data.NWS0, NWS1Input-Synchronous Nibble Write Select 0, 1 − active LOW(CY7C1416AV18 only). Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations. Nibbles not written remain unaltered.NWS0 controls D[3:0] and NWS1 controls D[7:4].All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device.BWS0, BWS1, BWS2, BWS3Input-SynchronousByte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocksduring Write operations. Used to select which byte is written into the device during the currentportion of the Write operations. Bytes not written remain unaltered.CY7C1427AV18 − BWS0 controls D[8:0]CY7C1418AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].CY7C1420AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3controls D[35:27].All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte WriteSelect will cause the corresponding byte of data to be ignored and not written into the device.A, A0Input-Synchronous Address Inputs. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1416AV18 and 4M x 9 (2 arrays each of 2M x 9) for CY7C1427AV18, a single 2M x 18 array for CY7C1418AV18, and a single array of 1M x 36 for CY7C1420AV18.CY7C1416AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array.CY7C1427AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array.CY7C1418AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array.CY7C1420AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected.R/W Input-Synchronous Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K.C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.C Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.K Input-Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode.PRELIMINARYCY7C1418AV18CY7C1420AV18Functional OverviewThe CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface.Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C or K/K when in single clock mode).All synchronous data inputs (D [x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q [x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C or K/K when in single-clock mode).All synchronous control (R/W, LD, BWS [0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K).CY7C1418AV18 is described in the following sections. The same basic descriptions apply to CY7C1416AV18,CY7C1427AV18, and CY7C1420AV18.Read OperationsThe CY7C1418AV18 is organized internally as a single array of 2M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Read address register and the least significant bit of the address is presented to the burst counter.The burst counter increments the address in a linear fashion.Following the next K clock rise the corresponding 18-bit word of data from this address location is driven onto the Q [17:0]using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto the Q [17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C, or K and K when in single clock mode, 200-MHz and 250-MHz device). In order to maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K).When Read access is deselected, the CY7C1418AV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C).CQOutput-Clock CQ is referenced with respect to C . This is a free running clock and is synchronized to the output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.CQOutput-Clock CQ is referenced with respect to C . This is a free running clock and is synchronized to the output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.ZQInputOutput Impedance Matching Input . This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q [x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DD , which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.DOFF InputDLL Turn Off, active LOW . Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDR™-II.”TDO Output TDO for JTAG .TCK Input TCK pin for JTAG .TDI Input TDI pin for JTAG .TMS Input TMS pin for JTAG .NC N/A Not connected to the die . Can be tied to any voltage level.NC/72M N/A Not connected to the die . Can be tied to any voltage level.NC/144M N/A Not connected to the die . Can be tied to any voltage level.NC/288M N/A Not connected to the die . Can be tied to any voltage level.V REF Input-Reference Reference Voltage Input . Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.V DD Power Supply Power supply inputs to the core of the device . V SS GroundGround for the device .V DDQPower Supply Power supply inputs for the outputs of the device .Pin Definitions (continued)Pin Name I/O Pin DescriptionPRELIMINARY CY7C1418AV18 CY7C1420AV18This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.Write OperationsWrite operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K).When Write access is deselected, the device will ignore all inputs after the pending Write operations have been completed.Byte Write OperationsByte Write operations are supported by the CY7C1418AV18.A Write operation is initiated as described in the Write Opera-tions section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock ModeThe CY7C1418AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. DDR OperationThe CY7C1418AV18 enables high-performance operation through high clock frequencies (achieved through pipelining)and double data rate mode of operation. The CY7C1418AV18 requires a single No Operation (NOP) cycle when transitioning from a Read to a Write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention.If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The Write information must be stored because the SRAM cannot perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write.If a Read is performed on the same address on which a Write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth ExpansionDepth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.Programmable ImpedanceAn external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with V DDQ=1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.Echo ClocksEcho clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLLThese chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns.PRELIMINARYCY7C1418AV18CY7C1420AV18Notes:1.The above application shows two DDR-II used.2.X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.3.Device will power-up deselected and the outputs in a three-state condition.4.On CY7C1418AV18 and CY7C1420AV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses sequence in the burst. On CY7C1416AV18, “A1” represents A + ‘0’ and A2 represents A + ‘1’.5.“t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.6.Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.7.It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.Application Example [1]Truth Table [2, 3, 4, 5, 6, 7]OperationK LD R/W DQDQWrite Cycle:Load address; wait one cycle; input write data on consecutive K and K rising edges.L-HLLD(A1)at K(t + 1) ↑D(A2) at K(t + 1) ↑Read Cycle:Load address; wait one and a half cycle; read data on consec-utive C and C rising edges.L-H L H Q(A1) at C(t + 1)↑Q(A2) at C(t + 2) ↑NOP: No Operation L-H H X High-Z High-Z Standby: Clock StoppedStoppedXXPrevious StatePrevious StateBurst Address Table (CY7C1418AV18, CY7C1420AV18)First Address (External)Second Address (Internal)X..X0X..X1X..X1X..X0PRELIMINARY CY7C1418AV18 CY7C1420AV18Write Cycle Descriptions(CY7C1416AV18 and CY7C1418AV18)[2, 8]BWS0,NWS0BWS1,NWS1K K CommentsL L L-H–During the Data portion of a Write sequence:CY7C1416AV18 − both nibbles (D[7:0]) are written into the device,CY7C1418AV18 − both bytes (D[17:0]) are written into the device.L L–L-H During the Data portion of a Write sequence:CY7C1416AV18 − both nibbles (D[7:0]) are written into the device,CY7C1418AV18 − both bytes (D[17:0]) are written into the device.L H L-H–During the Data portion of a Write sequence:CY7C1416AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]will remain unaltered,CY7C1418AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]will remain unaltered.L H–L-H During the Data portion of a Write sequence:CY7C1416AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]will remain unaltered,CY7C1418AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]will remain unaltered.H L L-H–During the Data portion of a Write sequence:CY7C1416AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]will remain unaltered,CY7C1418AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]will remain unaltered.H L–L-H During the Data portion of a Write sequence:CY7C1416AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]will remain unaltered,CY7C1418AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]will remain unaltered.H H L-H–No data is written into the devices during this portion of a Write operation.H H–L-H No data is written into the devices during this portion of a Write operation.Write Cycle Descriptions[2, 8] (CY7C1420AV18)BWS0BWS1BWS2BWS3K K CommentsL L L L L-H–During the Data portion of a Write sequence, all four bytes (D[35:0]) arewritten into the device.L L L L–L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) arewritten into the device.L H H H L-H–During the Data portion of a Write sequence, only the lower byte (D[8:0]) iswritten into the device. D[35:9] will remain unaltered.L H H H–L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) iswritten into the device. D[35:9] will remain unaltered.H L H H L-H–During the Data portion of a Write sequence, only the byte (D[17:9]) iswritten into the device. D[8:0] and D[35:18]will remain unaltered.H L H H–L-H During the Data portion of a Write sequence, only the byte (D[17:9]) iswritten into the device. D[8:0] and D[35:18]will remain unaltered.H H L H L-H–During the Data portion of a Write sequence, only the byte (D[26:18]) iswritten into the device. D[17:0] and D[35:27]will remain unaltered.H H L H–L-H During the Data portion of a Write sequence, only the byte (D[26:18]) iswritten into the device. D[17:0] and D[35:27]will remain unaltered.H H H L L-H During the Data portion of a Write sequence, only the byte (D[35:27]) iswritten into the device. D[26:0] will remain unaltered.Note:8.01012, 3 can be altered on differentportions of a Write cycle, as long as the set-up and hold requirements are achieved.。

元器件交易网
LPC2378
Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 01 — 6 December 2006
and PORT2 can be usedources. I Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt). I Two independent power domains allow fine tuning of power consumption based on needed features. I Each peripheral has its own clock divider for further power saving. I Brownout detect with separate thresholds for interrupt and forced reset. I On-chip power-on reset. I On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. I 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.

速度控制参数设置..........TORQUE DEMAND [432 ] = 0.00 % *..........TENSION ENABLE [433 ] = ENABLED 0.00 % * ..........OVER WIND [434 ] = ENABLED = DISABLED4 ] = 309 * ........SETPOINT SUM 2N MODE [201 ] =..........INPUT 2 [445 ] = 0.00 %........POS. I CLAMP [301 ] = 0.00 %..........INPUT 1 [443 ] = 0.00 %342........NEG. I CLAMP [48 ] =..........INPUT 0 [444 ] = 0.00 % ] =........I DMD. ISOLATE [119 ] = DISA..........RATIO 1 [446 ] = 1.0000......SPEED LOOP 344 *........P..........RATIO 0 [447 ] = 1.0000.....PNO 119 [319 ] = 122 ..........DIVIDER 1 [466 ] = 1.000015 SE CS *........PNO 120 [320 ] = ..........DIVIDER 0 [448 ] = 1.0000202 ] = OFF........PNO 121..........LIMIT [449 ] = 1OS..........DERIVATIVE TC [401 ] = 0.000 SECS * ............SPD BRK2 (HIGH) [270 ] =..........POSITIVE LIMIT [405 ] = 100.00 %............PROP. GAIN [271 ]..........NEGATIVE LIMIT [406 ] = -100.00 %27 ] =............INT. TIME CONST. [272 ]..........O/P SCALER(TRIM) [407 ] = 0.2000......SOFTWARE..........I GAIN IN R..........INPUT 1 [410 ] = 0.00 % ENABLE [39 ] = DIS ..........POS. LOOP P GAI..........INPUT 2 [411 ] = 0.00 %............ZERO SPD. QUENC..........RATIO 1 [412 ] = 1.0000SPD. LEVEL [284 ] = 0.50 % ..........RATIO 2 [413 ] =..........MIN PROFILE GAIN [474.................SETPOINT 4 [41 ] =..........PROFILED GAIN [475 ] = 0.0.................MAX DEMAND [357........TENS+COMP CALC...........STATIC COMP [487 ] = 0.00 %ND [358 ] = -18.79 % *..........DYNAMIC COMP [488 ] = 0.00 %..STANDSTILL 0 * ........STANDSTIL..........REWIND [489 ] = ENA...ANIN 4 (A5)..........TENSION SCALER [486 ] = 1.00000 %........ANALOG OUTPUT......FIELD CONTROL [375 ] =........FIELD ENABLE [170 ] =........INPUT 2 [423........FLD CTRL MODE IS [209 ] = CURRE..........PROP. GAIN [173 ] = 0.101 ] = 0x0001 *[248 ] = 100.00 % ..........INT. GAIN [172 ] = 1.28............MO......HEAL TH WORD [115..........FLD WEAK VARS..............FLD. WEAK ENABLE [174 ] = ENABLED *....MENUS.............FU............EMF LEAD [175 ] = 2.00......MENU DELA Y............EMF LAG [176 ] = 40.00INPUT C4NGUAGE.........P............EMF GAIN [177 ] = 0.30S......MAIN PORT (P1).......D............MIN FLD CURRENT [179 ] = 25.00 % *STINATION TAG [495 ] =........RATE [200 ] = 60.0 SECS........UNIT ID (UID)......STOP RATES 0 [4........STOP TIME [27 ] = 10.0 SECS [149 ] = EI ASCIITAG [97 ] = ........STOP LIMIT [217 ] = 60.0 SECS51 ] = 9600.INVERTED [359 ] = FALSE........CONTACTOR DELAY [302 ] = 1.0 SECSABLED.DIGOUT 2 (B6)............PROG STOP TIME [26 ] = 0.1 SECS.............PROG STOP LIMIT [216 ] = 60.0 SECS........PNO. 7........PROG STOP I LIM [91 ] = 100.00 %......SYSTEM PORT (P3).........STOP ZERO SPEED [29 ] = 0.70 % *..........MODE [130 ] = CELite (EIAS......CALIBRATION....................ARMATURE V CAL. [20 ] = 1.0000ORT........ANALOG TACH CAL [23 ] = 1.0000= 0.00 % [134 ] = 89 ........ZERO SPD. OFFSET [10 ] = 0.00 %...DESTINATION TAG [135 ............GROUP I........ARMATURE I (A9) [25 ] = BIPOLAR....BLOCK DIAGRAM.................SPDFBK ALM LEVEL [180 ] = 50.0 %.............STALL THRESHOLD [263 ] = 95.00 %..............STALL TRIP DELAY [224 ] = 10.0 SECS *......ACTUAL NEG I........OVER SPEED LEVEL [188 ] = 125.00 %0 0......INVERSE TIME O/P........FIELD I CAL. [182 ] = 1.0000xFFFF 0......AT CURRENT LIMIT......INHIBIT ALARMS......ANIN 3 (A4)........ADDITIONAL DEM [30 ] = 0.00 % * 0......ANIN 4 (A........BIPOLAR CLAMPS [90 ] = DISABLED2 ] = 60 *RCE TAG [454 ........REGEN MODE [201 ] = ENABLEDNO 123 [323 ] = 207 ........POS. I CLAMP [301 ] = 100.00 %OLTS........PNO 124 [324 ] =........NEG. I CLAMP [48 ] = -100.00 %6 ] = 0........PNO 125........I DMD. ISOLATE [119 ] = DISABLEDG [457 ] = 0..........SPEED LOOP [326 ] =........PROP. GAIN [14 ] = 3.00 *....PNO 127 [327 ] =.........INT. TIME CONST. [13 ] = 0.500 SECS ]......SOFTWARE (I)......CONFIGURE........INT. DEFEAT [202 ] = FIGURE ENAB............SPD BRK2 (HIGH) [270 ] = 5.00 %............CALIBRATION [233 ]............PROP. GAIN [271 ] = 5.00............MAX VALUE [234 ]............INT. TIME CONST. [272 ] = 0.500 SECS [390 ] = 0PUT ............MIN VALUE..........I GAIN IN RAMP [274 ] = 1.000091 ] = 0 [63 ] = ..........ANIN 3 (A..........POS. LOOP P GAIN [273 ] = 0.00 % [236 ] = 1.0000-2.6 % ..........ZERO SPD. QUENCH.........MAX VALUE..........RATIO 2 (A3) [7 ] = 1.0000N VALUE [241 ] = -100.00 %.........A ..........SETPOINT 2 (A3) [290 ] = 0.00 %....DESTINATION TAG [250 ] = 379 ..........SETPOINT 3 [291 ] = 0.00 %..........ANIN 5 (A6)NOT ALTER !!..........SETPOINT 4 [41 ] = 0.00 %1.0000162 ] = 80..........MAX DEMAND [357 ] = 100.00 % *%3 ] = 2 ........AUTO R.............MIN DEMAND [358 ] = -105.00 % 160........EXTERNAL RESET [28......STANDSTILL.........SETPOINT SUM 1ODULUS [362........RATIO 1 [6 ] = 1.0000 [16................OFFSET [4........RATIO 0 [208 ] = 1.0000FF....................SOURCE........SIGN 1 [8 ] = POSITIVE............DISC ADAPT........SIGN 0 [292 ] = POSITIVE............% TO GET 10V [248........DIVIDER 1 [419 ] = 1.0000....................DIVIDER 0 [420 ] = 1.0000............OFFSET........DEADBAND WIDTH [131 ] = 0.0 %2........ENABLE...................LIMIT [375 ] = 105.00 %......JOG/........GROUP ID (GID) [138 ] = 07 ] = 32............VALUE FOR FAL........UNIT ID (UID) [139 ] = 0 [386 ] = 20 ............D........PROTOCOL [148 ] = OPTION * [279 ] = 12200 ......SPECIAL.............BAUD RATE [150 ] = 9600.........DIGOUT 1 (B5) ..........LINE SPE........ESP SUP. (ASCII) [152 ] = DISABLED 0.00 %N [280 ] = 1800 ..................CHANGEBAND (BIN) [144 ] = 0.00 %[43 ] = TRUE TC [281 ] = 3 ..............ERROR REPORT [158 ] = 0x03C1 * 77SHOLD [282 ] = 4 ..........MIN SP........PNO. 7 [142 ] = 0xFFFFLSE IP OFFSET [265 ] = 2..............OPTION ADDRESS [499 ] = 12 *............THRESHOLD (>) [196 ] = 0.00 %RN........OPTION VERSION [303 ] = 14.00............INVERTED [361 ]........ESP SUP. (ASCII) [153 ] = DISABLED........CONFIGURE 5703..TOT..............CHANGEBAND (BIN) [145 ] = 0.00 %= 89............ACT........ERROR REPORT [159 ] = 0x00C0 ] = 412 ] = 0.00 %......A........PNO. 7 [143 ] = 0xFFFF...TENSION ENABLE..........RAISE/LOWER D......SYSTEM PORT (P3)] = 200.00 %..............P3 SETUP..........RA..........MODE [130 ]...............UDP XFER <- P3367 ] = 0........UDP XFER -> P34) [52 ] =..........PNO CONFIG00 %............PNO 112 [312 ] = 339 * = 3.00 VOLTS= -100.00 % ............DE........PNO 113 [313 ] = 340 *0 VOLTS= 0.2000 ..........LINK 4........PNO 114 [314 ] = 309 * 0 %..............PNO 115 [315 ] = 341 *...............L........PNO 116 [316 ] = 342 *454 ] = 0INPUT C4 [69 ] = OFF.RATIO 2........PNO 117 [317 ] =..........DIVIDER 1......DIGIN........PNO 118 [318 ] = 344 *E TAG [456 ] = 0 [72 ] = OFF00..........................SOURCE T........PNO 127 [327 ] = 0..............TERMIN................SYSTEM TAG [470......SOFTWARE......CONFIGURE I/O EMF................CONFIGURE ENAB............DESTINATION TAG [246 ] = 0 *................LINK 12 [4 ] = ENABL..........ANIN 2 (A3)TAG [395 ] =............CALIBRATION [233 ] = 1.0000R............DESTINATION TAG [396 ] =............MAX VALUE [234 ] = 100.00 %............ADVANCED [397 ] = OFF............MIN VALUE [235 ] = -100.00 %..MODE [398 ] = SWITCH...RAMPING THR..........ANIN 3 (A4)6 %........................CALIBRATION [236 ] = 1.0000..AUTO RESET [287 ] = ENABL ......RESERV............MAX VALUE [237 ] =NLYTERNAL RESET..........ANOUT 1 (A7) 3.00 % *............% TO GET 10V [245 ] = 100.00 %....JOG SPEED 2..............MODULUS [362 ] = FALSE *......TAKE UP 1 [253 ] = ............OFFSET [464 ] = 0.00 % [213 ] = 1 *KE UP 2 [254............SOURCE TAG [251 ] = 62.ZCD THRESHOLD [214 ] = 6RAWL SPEED..........ANOUT 2 (A8)%.........................% TO GET 10V [248 ] = 100.00 %[228 ] = FALSE....................M............MODULUS [363 ] = FALSE 2.0 SECS *........IMAX...................OFFSET [465 ] =........RESET VALUE [25.......................SOURCE TAG [252 ] = 630........INCREASE RATE [256 ]...................DIGITAL INPUTS] = 155] = 10..........DIGITAL INPUT C4 [257............FIEL............VALUE FOR TRUE [109 ] = 0.01 %S *..MENU LEVEL....DIAGNOSTICS...............VALUE FOR FALSE [110 ] = 0.00 %.00 % *..................DESTINATION TAG [108 ] = 168 * [438 ] = 0.00 % ......SPEED ERROR [29........DIGITAL OUTPUTS................DIGOUT 1 (B5)T DEMAND [299 ] =............THRESHOLD (>) [195 ] = 0.00 %......CURRENT FEEDBACK [298 ] = 0.00 % [33............MODULUS [43 ] = TRUEIGITAL DC DRIVE............STANDBYISSUE:............SOURCE TAG [97 ] = 77OSTICS1 ] = 0.00......SPEED DEMAND [............INVERTED [359 ] = FALSE......SPEED FEEDBACK [20..........DIGOUT 2 (B6) [123 ] = [0x0078]............THRESHOLD (>) [196 ] = 0.00 %.00 % ]........PEEK SCALE [1............MODULUS [44 ] = TRUE4= ENABLEDIELD FAIL [19 ] = ENA......A..........DIAMETER [431 ] = 0 [405 ] = 100.00 %......INVER..........TAPER [442 ] = 0IMIT [406 ] = -100.00 %......AT CURREN..........SETPOINT SUM 2 [450 ] = 0ALER(TRIM) [40......AT ZERO SPEED [77 ]..........POS. I CLAMP [435 ] = 0.....AT ZERO SETPOINT [78 ] = TRUE ..........NEG. I CLAMP [436 ] = 0LL [79 ] = TRUE ] = 0.00 % ..........TENS+COMP CALC. [478 ] = 0K.RATIO 1 [412 ] = 1.000 ......RA........INTERNAL LINKS FALSE..................LINK 1 [4......PROGR............SOURCE TAG [364 ] = 0 (IVI)......DRIVE START [82 ]............DESTINATION TAG [365 ] = 0.DRIVE ENABLE [84 ] = DISABLED1.0000 ..........LINK 2..........STATI......ANIN 3 (A4) [..........LINK 5VOLTS.......POS.............SOURCE TAG [454 ] = 04 (A5) [53 ] = 0.00 VOLTS..... ............DESTINATION TAG [455 ] = 05 (A6) [54 ] = 10.01 VOLTS.50 % ..........LINK 6.......FIX.INERT............SOURCE TAG [456 ] = 0TS 1.50 %..........VAR.INERT............DESTINATION TAG S............DESTINATION TAG [461 ] = 0[484 ] = 0.00 % *......DIGOU..........LINK 9] = ON.......INE............SOURCE TAG [467 ] = 0 [75 ] = ON..........TEN............DESTINATION TAG [468 ] = 0......RAISE/LOWER O/P..........LINK 100 %....................SOURCE TAG [469 ] = 0 [417 ] = 0.00 %.......FLD CTRL MODE I ............DESTINATION TAG [470 ] = 06 ] = FALSE........FLD V..........LINK 11 [415 ] =............SOURCE TAG [390 ] = 0...........SPT SUM OUTPUT [86 ]............AUX.SOURCE [394 ] = 0..........FLD WEAK......TACH INPUT..........LINK 12 0.0 %. WEAK ENA............SOURCE TAG [395 ] = 0 [206 ] = 0 RPM.....DIV ...................DESTINATION TA.........RAMPSD WI..................ADVANCED [397 ] = OFF SECS........LIMIT............MODE [398 ] = SWITCH 10.0 SECS........INPUT 2............AUX.SOURCE [399 ] = 0 ] = ENABLED *........INPUT 1......RESERVED.RAMP HOLD........FACTORY USE ONLY[178 ] = 94.28 %..........DO NOT ALTER !! [5 ] = 0.00 %............MIN MMI CYCLE............12 BIT DAC [220 ] = DISABLED......JOG SPEED 1 [218 ] = 5.00 % ............MMI FILTER T.C. [221 ] =............PRED STEP [222 ] = 3KE UP 1 [253 ] = 5.00 % 14.00 ............SCAN THRESHOLD [223 ] = 4P 2 [254 ] = -5.00 % [334 ] = EVE............FIELD FBKSTOP [34 ] = 155D [225 ] = 10.00 % ........SRL LI............FIELD FFRSTOP [35 ] = 209 [228 ] = FALSEURE V CAL. [20 ] = 1.0000 ............IFFB DELAY [36 ] = 20 1.0 SECSENSATION [21 ] = 0.00 %141 ] (II)............PLL PROP [276 ] = 80........CHANGEBAN.............RAISE INP............PLL INT [277 ] = 32........ERROR........LOWER INPUT [262 ]............FILTER T.C. [386 ] = 20........MIN VALUE [258 ] = -100.00 %............ARM ENDSTOP [279 ] = 12200.....MAX VALUE [259 ] = 100.00 % 95.0............SCAN TC [283 ] = 10.EXTERNAL RESET [307 ] = FALSE = 10.0 SE ............HF C/O DISC GAIN [280 ] = 1800RT........OVER SPE........DIAMETER CALC..00......miniLINK........VALUE 1 [339 ] = 0.00 %........VALUE 2 [340 ] = 0.00 %........VALUE 3 [341 ] = 0.00 %........VALUE 4 [342 ] = 0.00 %........VALUE 5 [343 ] = 0.00 %........VALUE 6 [344 ] = 0.00 %........VALUE 7 [345 ] = 0.00 %........VALUE 8 [379 ] = 0.00 %........VALUE 9 [380 ] = 0.00 %........VALUE 10 [381 ] = 0.00 %........VALUE 11 [382 ] = 0.00 %........VALUE 12........VALUE 13 [384 ] = 0.00 %........VALUE 14 [385 ] = 0.00 %........LOGIC 1 [346 ] = OFF........LOGIC 2 [347 ] = OFF........LOGIC 3 [348 ] = OFF........LOGIC 4 [349 ] = OFF........LOGIC 5 [350 ] = OFF........LOGIC 6 [351 ] = OFF........LOGIC 7 [352 ] = OFF........LOGIC 8 [353 ] = OFF。