1．用VHDL设计60进计数器。
设计一个BCD码60进计数器。要求实现同步，异步两种情况，且规定个位显示0~9，十位显示0~5，均用4位二进制数表示。用VHDL语言描述中小规模集成电路74LS169。
VHDL的源程序如下：
（1）：同步，文件名为bcd60count
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcd60count is
port(clk,bcd1wr,bcd10wr,cin: in std_logic;
co: out std_logic;
datain: in std_logic_vector(3 downto 0);
bcd1p: out std_logic_vector(3 downto 0);
bcd10p: out std_logic_vector(2 downto 0));
end bcd60count;
architecture behave of bcd60count is
signal bcd1n: std_logic_vector(3 downto 0);
signal bcd10n: std_logic_vector(2 downto 0);
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1: process(clk,bcd1wr)
begin
if (bcd1wr='1') then
bcd1n<=datain;
elsif(clk'event and clk='1') then
if (cin='1') then
if(bcd1n="1001" ) then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
end if;
end if;
end if;
end process kk1;
kk2: process(clk,bcd10wr)
begin
if (bcd10wr='1') then
bcd10n<=datain(2 downto 0);
elsif(clk'event and clk='1') then
if(cin='1') and (bcd1n="1001") then
if(bcd10n="101") then
bcd10n<="000";
else
bcd10n<=bcd10n+'1';
end if;
end if;
end if;
end process kk2;
kk3: process(bcd10n,bcd1n,cin)
begin
if(cin='1' and bcd1n="1001" and bcd10n="101") then
co<='1';
else
co<='0';
end if;
end process kk3;
end behave;
（2）异步程序如下：
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cou60 is
port(clk,reset,cin : in std_logic;
co : out std_logic;
bcd1p : out std_logic_vector(3 downto 0);
bcd10p : out std_logic_vector(2 downto 0)); end cou60;
architecture behave of cou60 is
signal bcd1n: std_logic_vector(3 downto 0);
signal bcd10n: std_logic_vector(2 downto 0);
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcd1n<="0000";
elsif (cin='1') then
if(bcd1n="1001" ) then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
end if;
end if;
end if;
end process kk1;
kk2: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcd10n<="101";
elsif(cin='1') and (bcd1n="1001") then
if(bcd10n="001") then
bcd10n<="101";
else
bcd10n<=bcd10n+'1';
end if;
end if;
end if;
end process kk2;
kk3: process(bcd10n,bcd1n,cin)
begin
if(cin='1' and bcd1n="1001" and bcd10n="001") then
co<='1';
else
co<='0';
end if;
end process kk3;
end behave;
