GX_SOPC_EP2C35_M484

PULSE-WIDTH MODULATOR (PWM)ADSP-BF60X PWM REGISTER DESCRIPTIONS

ADSP-BF6011(R/W)MODE1BMode of TRIP1 for Channel B.The PWM_TRIPCFG.MODE1B bit selects the trip mode of TRIP1 for Channel B. For more information, see the PWM_TRIPCFG.MODE0A bit description.0Fault Trip on TRIP1 Input1Self Restart on TRIP1 Input10(R/W)EN1BEnable TRIP1 as a trip source for Channel B.The PWM_TRIPCFG.EN1B bit enables TRIP1 as a trip source for Channel B.0Disable TRIP1 for Channel B1Enable TRIP1 for Channel B9(R/W)MODE0BMode of TRIP0 for Channel B.The PWM_TRIPCFG.MODE0B bit selects the trip mode of TRIP0 for Channel B. For more information, see the PWM_TRIPCFG.MODE0A bit description.0Fault Trip on TRIP0 Input1Self Restart on TRIP0 Input8(R/W)EN0BEnable TRIP0 as a trip source for Channel B.The PWM_TRIPCFG.EN0B bit enables TRIP0 as a trip source for Channel B.0Disable TRIP0 for Channel B1Enable TRIP0 for Channel B3(R/W)MODE1AMode of TRIP1 for Channel A.The PWM_TRIPCFG.MODE1A bit selects the trip mode of TRIP1 for Channel A. For more information, see the PWM_TRIPCFG.MODE0A bit description.0Fault Trip on TRIP1 Input1Self Restart on TRIP1 Input2(R/W)EN1AEnable TRIP1 as a trip source for Channel A.The PWM_TRIPCFG.EN1A bit enables TRIP1 as a trip source for Channel A.0Disable TRIP1 for Channel A1Enable TRIP1 for Channel ATable 18-8:PWM_TRIPCFG Register Fields (Continued)Bit No.(Access)Bit NameDescription/EnumerationPULSE-WIDTH MODULATOR (PWM)ADSP-BF60X PWM REGISTER DESCRIPTIONS

D

IRECT M

EMORY A

CCESS (DMA)

DMA C

HANNEL E

VENT C

ONTROL

ADSP-BF60

X B

LACKFIN P

ROCESSOR H

ARDWARE R

EFERENCEservice is required. Triggers may also be used to enforce a handshake DMA operation in which the trigger

acts as a signal for a DMA request.

NOTE:

Using the trigger to control the pace of data transfers, such as in the case of a handshake DMA,

requires that all the data for the entire work unit is ready for transfer.

The DMA channel has a single incoming trigger that can be used to control the pace of the data transfers

performed by the DMA channel. The DMA channel can be configured to wait for the incoming trigger

before starting the work unit transfer or fetching a descriptor set from memory.

The DMA channel also has a single outgoing trigger signal that may be configured to signal the end of row

or an entire work unit. The DMA channel issues the last memory read or memory write transaction for the

Stratix II Device Handbook, Volume 2Design ConsiderationsStratixII and StratixIIGX on-chip series and parallel termination provides the convenience of no external components. External pull-up resistors can be used to terminate the voltage-referenced I/O standards such as SSTL-2 and HSTL.1Refer to the “StratixII and StratixIIGX I/O Standards Support” on page4–2 for more information on the termination scheme of various single-ended I/O standards.Differential I/O StandardsDifferential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the bus. StratixII and StratixIIGX devices provide an optional differential on-chip resistor when using LVDS and HyperTransport standards.I/O Banks RestrictionsEach I/O bank can simultaneously support multiple I/O standards. The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in StratixII and StratixIIGX devices.Non-Voltage-Referenced StandardsEach StratixII and StratixIIGX device I/O bank has its own VCCIO pins and supports only one VCCIO, either 1.5, 1.8, 2.5, or 3.3 V. An I/O bank can simultaneously support any number of input signals with different I/O standard assignments, as shown in Table4–8.For output signals, a single I/O bank supports non-voltage-referenced output signals that are driving at the same voltage as VCCIO. Since an I/O bank can only have one VCCIO value, it can only drive out that one value for non-voltage-referenced signals. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V standard inputs and outputs and 3.3-V LVCMOS inputs (not output or bidirectional pins).Table4–8. Acceptable Input Levels for LVTTL and LVCMOS(Part 1 of2)Bank VCCIO (V)Acceptable Input Levels (V)3.32.51.81.53.3vv (1)2.5vvStratix II Device Handbook, Volume 2Selectable I/O Standards in StratixII and StratixIIGX DevicesStratix II Device Handbook, Volume 2Document Revision HistoryStratix II Device Handbook, Volume 2Differential I/O TerminationSynchronizerThe synchronizer is a 1-bit  6-bit deep FIFO buffer that compensates for the phase difference between the recovered clock from the DPA circuit and the diffioclk that clocks the rest of the logic in the receiver. The synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver’s INCLK. An optional port, RX_FIFO_RESET, is available to the internal logic to reset the synchronizer. The synchronizer is automatically reset when the DPA first locks to the incoming data. Altera® recommends using RX_FIFO_RESET to reset the synchronizer when the DPA signals a loss-of-lock condition beyond the initial locking condition.Differential I/O TerminationStratixII and Stratix II GX devices provide an on-chip 100-differential termination option on each differential receiver channel for LVDS and HyperTransport standards. The on-chip termination eliminates the need to supply an external termination resistor, simplifying the board design and reducing reflections caused by stubs between the buffer and the termination resistor. You can enable on-chip termination in the QuartusII assignments editor. Differential on-chip termination is supported across the full range of supported differential data rates.fFor more information, refer to the High-Speed I/O Specifications section of the DC & Switching Characteristics chapter in volume 1 of the StratixII Device Handbook or the High-Speed I/O Specifications section of the DC& Switching Characteristics chapter in volume 1 of the StratixIIGX Device Handbook.Figure5–11 illustrates on-chip termination.Figure5–11.On-Chip Differential TerminationOn-chip differential termination is supported on all row I/O pins and on clock pins CLK[0, 2, 8, 10]. The clock pins CLK[1, 3, 9, 11], and FPLL[7..10]CLK, and the clocks in the top and bottom I/O banks (CLK[4..7, 12..15]) do not support differential on-chip termination.LVDS/HTTransmitterStratix II DifferentialReceiver with On-Chip100 Ω TerminationRDZ0 = 50 ΩZ0 = 50 ΩStratix II Device Handbook, Volume 2High-Speed Differential I/O Interfaces with DPA in Stratix II andStratixIIGX DevicesFast PLL The high-speed differential I/O receiver and transmitter channels use the fast PLL to generate the parallel global clocks (rx- or tx- clock) and high-speed clocks (diffioclk). Figure5–12 shows the locations of the fast PLLs. The fast PLL VCO operates at the clock frequency of the data rate. Each fast PLL offers a single serial data rate support, but up to two separate serialization and/or deserialization factors (from the C0 and C1 fast PLL clock outputs) can be used. Clock switchover and dynamic fast PLL reconfiguration is available in high-speed differential I/O support mode. fFor additional information on the fast PLL, refer to the PLLs in StratixII & Stratix II GX Devices chapter in volume 2 of the StratixII Handbook or the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Handbook.Figure5–12 shows a block diagram of the fast PLL in high-speed differential I/O support mode.Figure5–12.Fast PLL Block DiagramNotes to Figure5–12:(1)StratixII fast PLLs only support manual clock switchover.(2)The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global orregional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or pin-driven dedicated global or regional clock.(3)In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. StratixII devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.(4)This signal is a high-speed differential I/O support SERDES control signal.(5)If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.ChargePumpVCO÷c188448ClockInputPFD÷c0÷mLoopFilterPhaseFrequencyDetectorVCO Phase SelectionSelectable at each PLLOutput PortPost-ScaleCountersGlobal clocksdiffioclk0 (3)loaden0 (4)diffioclk1 (3)loaden1 (4)Regional clocksto DPA blockGlobal orregional clock (2)Global orregional clock (2)÷c2÷c3÷n4Clock (1)SwitchoverCircuitryShaded Portions of thePLL are Reconfigurable÷k(5)

3.1.4.2.3. OCT Intel FPGA IP Architecture

Figure 40.OCT IP Top-Level DiagramThis figure shows the top-level diagram of the OCT IP.

OCT rzqinOCT Intel® FPGA IPPad

Pad

Table 37.OCT IP Components

ComponentDescription

RZQ pin•Dual-purpose pin.•When used with OCT, the pin connects to an external reference resistor to calculate thecalibration codes to implement the required impedance.

OCT blockGenerates and sends calibration code words to the I/O buffer blocks.

RZQ Pin

There are two RZQ pins in each GPIO bank. The RZQ pin shares the same VCCIO supplywith the I/O bank where the pin is located.

RZQ pins are dual-purpose pins. If the pins are not connected to the OCT block, youcan use the pins as regular I/O pins. When you use the RZQ pin for OCT calibration,the RZQ pin connects the OCT block to ground through an external 240 Ω resistor witha precision of ±1 %.