EM681FU16中文资料

Document Title512K x16 bit Low Power and Low Voltage Full CMOS Static RAMRevision HistoryRevision No. History Draft Date Remark0.0Initial Draft April 12 , 20020.12’nd Draft Changed Icc, Icc1 value &November 11 , 200255ns product tDW valueDecember 23 , 20020.23’rd Draft Changed I SB1 test conditions,Changed VDR & IDRmeasurement condition0.3 4’th Draft Add Pb-free part number February 13 , 2004Emerging Memory & Logic Solutions Inc.IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.123456A LB OE A 0A 1A 2DNU B I/O 9UBA 3A 4CS I/O 1C I/O 10I/O 11A 5A 6I/O 2I/O 3D V SS I/O 12A 17A 7I/O 4V CC E V C CI/O 13 DNU A 16I/O 5V SS F I/O 15I/O 14A 14A 15I/O 6I/O 7G I/O 16DNU A 12A 13WE I/O 8HA 18A 8A 9A 10A 11DNUFEATURES•Process Technology : 0.18µm Full CMOS •Organization : 512K x 16 bit•Power Supply Voltage : 2.7V ~ 3.3V•Low Data Retention Voltage : 1.5V (Min.)•Three state output and TTL Compatible •Package Type : 48-FPBGA 8.0x10.0GENERAL DESCRIPTIONThe EM681FU16 families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The fami-lies also supports low data retention voltage for battery back-up operation with low data retention current.PRODUCT FAMILYProduct Family Operating Temperature Vcc RangeSpeedPower DissipationPKG TypeStandby (I SB1, Typ.)Operating (I CC1.Max) EM681FU16Industrial (-40 ~ 85o C)2.7V~3.3V551) / 70ns 2 µA2 mA48-FPBGAName FunctionName FunctionCS Chip select input Vcc Power Supply OE Output Enable input Vss GroundWE Write Enable input UB Upper Byte (I/O 9~16)A 0~A 18Address InputsLBLower Byte (I/O 1~8)I/O 1~I/O 16 Data Inputs/outputsDNU Do Not UseR o w S e l e c tI/O Circuit Column SelectDataCont Data ContPre-charge CircuitMemory Array 2048 x 4096A 1A 2A 3A 4A 5A 6A 7A 0A 8A 9A 11A 12A 13A 14A 15A 16A 17W E O E UB LBC SI/O1 ~ I/O8I/O9 ~ I/O16V C C V SSControl LogicFUNCTIONAL BLOCK DIAGRAM1. The parameter is measured with 30pF test load.A 10PIN DESCRIPTION48-FPBGA : Top view (ball down)A 18ABSOLUTE MAXIMUM RATINGS *Parameter Symbol Minimum Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to 3.6V VVoltage on Vcc supply relative to Vss V CC -0.2 to 4.0V VPower Dissipation P D 1.0 WOperating Temperature T A -40 to 85 o C*Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.FUNCTIONAL DESCRIPTIONCS OE WE LB UB I/O1-8I/O9-16Mode PowerH X X X X High-Z High-Z Deselected Stand byX X X H H High-Z High-Z Deselected Stand byL H H L X High-Z High-Z Output Disabled ActiveL H H X L High-Z High-Z Output Disabled ActiveL L H L H Data Out High-Z Lower Byte Read ActiveL L H H L High-Z Data Out Upper Byte Read ActiveL L H L L Data Out Data Out Word Read ActiveL X L L H Data In High-Z Lower Byte Write ActiveL X L H L High-Z Data In Upper Byte Write ActiveL X L L L Data in Data In Word Write ActiveNote: X means don’t care. (Must be low or high state)DC AND OPERATING CHARACTERISTICSParameterSymbol Test Conditions Min Typ Max Unit I LI IN =V SS to V CC-1-1uA I LO IH or OE=V IH or WE=V IL , LB=UB=V IH ,IO =V SS to V CC-1-1uA I CC IO =0mA, CS=V IL , V IN =V IH or V IL --2mA I CC1µs, 100% duty, I IO =0mA,IN IN CC -0.2V--2 mAI CC2IO =0mA, 100% duty,IL, LB=V IL or/and UB=V IL , V IN =V IL or V IH--mA --V OL OL = 2.1mA --0.4V V OH OH = -1.0mA2.2--V I SBIH , LB=UB =V IH Other inputs=V IH or V IL --0.3mAI SB1CC -0.2V(CS controlled) or≥ V CC trolled)CC(Typ. condition : V CC =3.0V @ 25o C)CC =3.3V @ 85o C)-215uARECOMMENDED DC OPERATING CONDITIONS 1)1. TA= -40 to 85o C, otherwise specified2. Overshoot: V CC 4. Overshoot and undershoot are sampled, not 100% tested .Parameter SymbolMinTypMaxUnit Supply voltage V CC 2.7 3.0 3.3 V GroundV SS 000VInput high voltage V IH 2.2-V CC + 0.22) VInput low voltageV IL-0.23)-0.6VCAPACITANCE 1) (f =1MHz, T A =25o C)1. Capacitance is sampled, not 100% testedItemSymbol Test ConditionMin Max Unit Input capacitance C IN V IN =0V -8pF Input/Ouput capacitanceC IOV IO =0V-10pFEM681FU16 SeriesLow Power, 512Kx16 SRAMmerging Memory & Logic Solutions Inc.ParameterSymbol55ns 70nsUnitMin Max Min Max Read cycle time t RC 55-70-ns Address access time t AA -55-70ns Chip select to outputt CO -55-70ns Output enable to valid output t OE -30-35ns UB, LB acess time t BA 55 70ns Chip select to low-Z output t LZ 5-5-ns UB, LB enable to low-Z output t BLZ 10- 10-ns Output enable to low-Z output t OLZ 5-5-ns Chip disable to high-Z output t HZ 020025ns UB, LB disable to high-Z output t BHZ 020025ns Output disable to high-Z output t OHZ 020025ns Output hold from address changet OH10-10-nsParameterSymbol55ns 70nsUnitMin Max Min Max Write cycle timet WC 55-70-ns Chip select to end of write t CW 45-60-ns Address setup timet AS 0-0-ns Address valid to end of write t AW 45-60-ns UB, LB valid to end of write t BW 45-60-ns Write pulse width t WP 45-55-ns Write recovery time t WR 0-0-ns Write to ouput high-Z t WHZ 020025ns Data to write time overlap t DW 30 30 ns Data hold from write time t DH 0-0-ns End write to output low-Zt OW5-5-nsREAD CYCLE (V cc =2.7 to 3.3V, Gnd = 0V, T A = -40o C to +85o C)WRITE CYCLE (V cc =2.7 to 3.3V, Gnd = 0V, T A = -40o C to +85o C)AC OPERATING CONDITIONSTest Conditions (Test Load and Test Input/Output Reference)Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5nsInput and Output reference Voltage : 1.5V Output Load (See right) : CL = 100pF+ 1 TTL CL 1) = 30pF + 1 TTL 1. Including scope and Jig capacitance 2. R 1=3070Ω, R 2=3150Ω3. V TM =2.8VCL 1)V TM 3)R 12)R 22)t AddressCSUB,LBOEData Outt COt OHt B At O EHigh-ZTIMING WAVEFORM OF READ CYCLE(2) (WE = V IH )Data ValidOLZt t LZAAHZt RCAddresst AA Data Validt OHPrevious Data ValidTIMING WAVEFORM OF READ CYCLE(1). IL IH, or/and =V IL )Data OutTIMING DIAGRAMSNOTES (READ CYCLE)1. t HZ and t OHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.WR (4)t WC AddressCS UB,LB WE Data in Data outt CW(2)t AWt BWt WP(1)t AS(3)High-Zt DW t DHHigh-Zt OWt WHZData UndefinedTIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)Data Validt WCAddressCS UB,LB WE Data in Data outt CW(2)t WR(4)t AWt BWt WP(1)t DW t DHTIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)tAS(3)High-Z High-ZData Validt AddressCSUB,LBWEData in Data outt CW (2)W R (4)t A W t B Wt W P (1)t DWDHTIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)High-ZHigh-ZData ValidA S NOTES (WRITE CYCLE)1. A write occurs during the overlap(t WP ) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The t WP is measured from the beginning of write to the end of write.2. t CW is measured from the CS going low to end of write.3. t AS is measured from the address valid to the beginning of write.4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as CS or WE going high.DATA RETENTION CHARACTERISTICSNOTES1. See the I SB1 measurement condition of datasheet page 4.ParameterSymbolTest ConditionMinTypMaxUnitV CC for Data Retention V DR I SB1 Test Condition (Chip Disabled) 1)1.5- 3.3V Data Retention CurrentI DR V CC =1.5V, I SB1 Test Condition (Chip Disabled) 1)- - 4 uAChip Deselect to Data Retention Time t SDR See data retention wave form0--nsOperation Recovery Timet RDRt RC--V cc 2.7V2.2V V DRCS,LB/UBGNDDATA RETENTION WAVE FORMA0.79T y p ..25T y p .PACKAGE DIMENSION48 Ball Fine Pitch BGA (0.75mm ball pitch)Bottom ViewTop ViewYMinTyp Max A -0.75-B 7.908.008.10B1- 3.75-C 9.9010.0010.10C1- 5.25-D 0.300.350.40E 1.00 1.04 1.10E1-0.79-E2-0.25-Y--0.081. Bump counts : 48(8row x 6column)2. Bump pitch : (x,y)=(0.75x0.75) (typ.)3. All tolerence are +/-0.050 unless otherwise specified.4. Typ : Typical5. Y is coplanarity : 0.08(Max)Side ViewDetail AUnit: millimetersEM681FU16 SeriesLow Power, 512Kx16 SRAMmerging Memory & Logic Solutions Inc.1. EMLSI Memory2. Device Type3. Density 5. Technology 8. Version 9. Packages 10. Speed7. Orgainzation1. Memory Component2. Device Type6 ------------------------ Low Power SRAM7 ------------------------ Pseudo SRAM 3. Density1 ------------------------- 1M2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Option0 ----------------------- Dual CS 1 ----------------------- Single CS 5. TechnologyBlank ------------------ CMOSF ------------------------ Full CMOS 6. Operating Voltage Blank ------------------- 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 7. Orginzation8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit8. VersionBlank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision 9. PackageBlank ---------------------- Package W --------------------- Wafer 10. Speed45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns11. PowerLL ---------------------- Low Low PowerLF ---------------------- Low Low Power(Pb-Free) L ---------------------- Low PowerS ---------------------- Standard Power4. Option 11. Power 元器件交易网。