TFRA08C13-DB中文资料

Preliminary Data SheetOctober 2000

TFRA08C13 OCTAL T1/E1 Framer FeaturessEight independent T1/E1 transmit and receive framers.sInternal DS1 transmit clock synthesis—no external oscillator necessary.sComprehensive alarm reporting and performance monitoring:— Programmable automatic and on-demand alarm transmission.sAutomatic facility data link:— Automatic transmission of ESF performance report message.sCommon 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s TDM highway.sDual- or single-rail line-side I/O.sSupports one second polling interval for perfor-mance monitoring.sIEEE* Std. 1149.1 JTAG boundary scan.s3.3 V low-power CMOS with 5 V tolerant inputs.sAvailable in 352-pin PBGA.T1/E1 Framer FeaturessSupports T1 framing modes ESF, D4, SLC®-96, T1DM DDS.sSupports G.704 basic and CRC-4 multiframe for-mat E1 framing and procedures consistent with G.706.sSupports unframed transmission format.sT1 signaling modes: transparent; ESF 2-state, 4-state, and 16-state; D4 2-state and 4-state; SLC-96 2-state, 4-state, 9-state, and 16-state. E1 signaling modes: transparent and CAS.sAlarm reporting and performance monitoring per AT&T, ANSI†, and ITU-T standards.sProgrammable, independent transmit and receive system interfaces at a 2.048 MHz, 4.096 MHz, or 8.192 MHz data rate.Facility Data Link FeaturessHDLC or transparent mode.sAutomatic transmission of the ESF performance report messages (PRM).

sDetection of the ESF PRM.sDetection of the ANSI ESF FDL bit-oriented codes.s64-byte FIFO in both transmit and receive direc-tions.

sProgrammable FIFO full and empty level interrupt.sUser-programmable microprocessor interface.

Microprocessor Interfaces33 MHz read and write access.s12-bit address, 8-bit data interface.sIntel‡ or Motorola§ style control interfaces.

sDirectly addressable internal registers.sProgrammable interrupts.

ApplicationssDS3 and E3 port cards for narrowband DXCs.sMultiservice switches.sHigh density DS1 and E1 port cards.sFrame relay access devices.sByte-synchronous SDH/SONET mapping.sSONET and SDH drop alignment.sIP and packet routers.

* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.† ANSI is a registered trademark of American National Standards Institute, Inc.‡ Intel is a registered trademark of Intel Corporation.§ Motorola is a registered trademark of Motorola, Inc.

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Preliminary Data SheetTFRA08C13 OCTAL T1/E1 FramerOctober 2000

2Lucent Technologies Inc.Features...................................................................................................................................................................1T1/E1 Framer Features.........................................................................................................................................1Facility Data Link Features.......................................................................................................................................1Microprocessor Interface..........................................................................................................................................1Applications..............................................................................................................................................................1Feature Descriptions..............................................................................................................................................10T1/E1 Framer Feature Descriptions....................................................................................................................10Functional Description............................................................................................................................................11Pin Information.......................................................................................................................................................15LIU-Framer Interface..............................................................................................................................................29LIU-Framer Physical Interface.............................................................................................................................29Line Encoding......................................................................................................................................................31DS1: Zero Code Suppression (ZCS)...................................................................................................................31CEPT: High-Density Bipolar of Order 3 (HDB3)..................................................................................................33Frame Formats.......................................................................................................................................................34T1 Framing Structures.........................................................................................................................................34T1 Loss of Frame Alignment (LFA).....................................................................................................................41T1 Frame Recovery Alignment Algorithms..........................................................................................................42T1 Robbed-Bit Signaling.....................................................................................................................................43CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures...................45CEPT 2.048 Basic Frame Structure....................................................................................................................46CEPT Loss of Basic Frame Alignment (LFA)......................................................................................................48CEPT Loss of Frame Alignment Recovery Algorithm.........................................................................................48CEPT Time Slot 0 CRC-4 Multiframe Structure..................................................................................................49CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)....................................................................................50CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms.....................................................................51CEPT Time Slot 16 Multiframe Structure............................................................................................................55CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA).........................................................................56CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm..............................................................56CEPT Time Slot 0 FAS/NOT FAS Control Bits.......................................................................................................56FAS/NOT FAS Si- and E-Bit Source...................................................................................................................56NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources.....................................................................................57NOT FAS Sa-Bit Sources....................................................................................................................................57Sa Facility Data Link Access...............................................................................................................................58NOT FAS Sa Stack Source and Destination.......................................................................................................59CEPT Time Slot 16 X0—X2 Control Bits.............................................................................................................61Signaling Access....................................................................................................................................................61Transparent Signaling.........................................................................................................................................61DS1: Robbed-Bit Signaling..................................................................................................................................61CEPT: Time Slot 16 Signaling.............................................................................................................................62Auxiliary Framer I/O Timing ...................................................................................................................................63Alarms and Performance Monitoring......................................................................................................................67Interrupt Generation............................................................................................................................................67Alarm Definition...................................................................................................................................................67Event Counters Definition ...................................................................................................................................73Loopback and Transmission Modes....................................................................................................................75Line Test Patterns...............................................................................................................................................78Receive Line Pattern Monitor—Using Register FRM_SR7.................................................................................80Automatic and On-Demand Commands.............................................................................................................82Facility Data Link....................................................................................................................................................84