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HCF4069资料

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1/7September 2001sMEDIUM-SPEED OPERATION tPD = 30ns (Typ.) at 10V

sSTANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS

sQUIESCENT CURRENT SPECIFIED UP TO 20V

s5V, 10V AND 15V PARAMETRIC RATINGSsINPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C

s100% TESTED FOR QUIESCENT CURRENT sMEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"

DESCRIPTIONThe HCF4069UB is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. The HCF4069UB consists of six COS/MOSinverter circuits. This device is intended for all

general purpose inverter applications where themedium power TTL-drive and logic levelconversion capabilities of circuits such HCF4049BHEX INVERTER/BUFFERS are not required.

HCF4069UBHEX INVERTER

PIN CONNECTIONORDER CODES PACKAGETUBET & RDIPHCF4069UBEYSOPHCF4069UBM1HCF4069UM013TR

DIPSOPHCF4069UB

2/7INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

TRUTH TABLE ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

PIN NoSYMBOLNAME AND FUNCTION1, 3, 5, 9, 11, 13A, B, C, D, E, FData Inputs

2, 4, 6, 8, 10, 12G, H, I, J, K, LData Outputs

7VSSNegative Supply Voltage

14VDDPositive Supply Voltage

INPUTSOUTPUTSA, B, C, D, E, FG, H, I, J, K, LLHHL

SymbolParameterValueUnitVDDSupply Voltage

-0.5 to +22V

VIDC Input Voltage-0.5 to VDD + 0.5

V

IIDC Input Current

± 10mA

PDPower Dissipation per Package200mW

Power Dissipation per Output Transistor100mWTopOperating Temperature-55 to +125°C

TstgStorage Temperature

-65 to +150°C

SymbolParameterValueUnitVDDSupply Voltage

3 to 20V

VIInput Voltage0 to VDDV

TopOperating Temperature

-55 to 125°CHCF4069UB

3/7DC SPECIFICATIONS

The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15VDYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

SymbolParameterTest ConditionValueUnitVI(V)VO(V)|IO|(µA)VDD

(V)

TA = 25°C

-40 to 85°C-55 to 125°C

Min.Typ.Max.Min.Max.Min.Max.ILQuiescent Current0/550.010.257.57.5

µA0/10100.010.515150/15150.01130300/20200.025150150VOHHigh Level Output Voltage0/5<154.954.954.95

V0/10<1109.959.959.950/15<11514.9514.9514.95VOLLow Level Output Voltage5/0<150.050.050.05

V10/0<1100.050.050.0515/0<1150.050.050.05VIHHigh Level Input Voltage0.5/4.5<15444

V1/9<1108881.5/13.5<11512.512.512.5VILLow Level Input Voltage4.5/0.5<15111

V9/1<11022213.5/1.5<1152.52.52.5IOHOutput Drive Current0/52.5<15-1.36-3.2-1.15-1.1

mA0/54.6<15-0.44-1-0.36-0.360/109.5<110-1.1-2.6-0.9-0.90/1513.5<115-3.0-6.8-2.4-2.4IOLOutput Sink Current0/50.4<150.4410.360.36

mA0/100.5<1101.12.60.90.90/151.5<1153.06.82.42.4IIInput Leakage

Current0/18Any Input18±10

-5±0.1±1±1µA

CIInput CapacitanceAny Input57.5pF

SymbolParameterTest ConditionValue (*)UnitVDD (V)

Min.Typ.Max.

tPLH tPHLPropagation Delay Time555110

ns103060152550tTLH tTHLOutput Transition Time5100200

ns1050100154080HCF4069UB

4/7TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) HCF4069UB

5/7DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.a10.510.020B1.391.650.0550.065b0.50.020b10.250.010D200.787E8.50.335e2.540.100e315.240.600F7.10.280I5.10.201L3.30.130Z1.272.540.0500.100

Plastic DIP-14 MECHANICAL DATA

P001A

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CD74HC4067SM96中文资料

CD74HC4067SM96中文资料


Copyright © 2003, Texas Instruments Incorporated
1
元器件交易网
Functional Diagram
10 S0 11 S1 14 S2
13 S3
CD74HC4067, CD74HCT4067
I0 9
PN
BINARY 1 OF 16 DECODER SN = 5 STAGES E = 4 STAGES
Thermal Information
Thermal Resistance (Typical)
θJA (oC/W)
E (PDIP) Package, Note 1 . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package, Note 2 . . . . . . . . . . . . . . . . . . .
P
N
16 I15
TRUTH TABLE
S2
S3
E
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
SELECTED CHANNEL
None 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MC74HC4060AN中文资料

MC74HC4060AN中文资料


ORDERING INFORMATION MC54HCXXXXAJ MC74HCXXXXAN MC74HCXXXXAD MC74HCXXXXADT Ceramic Plastic SOIC TSSOP
LOGIC DIAGRAM
Osc Out 1 Osc Out 2 10 9 Clock 7 5 Osc In 11 4 6 14 13 15 1 2 3 Reset 12 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 VCC 16 Q10 15 X
FUNCTION TABLE
Reset L L H Output State No Charge Advance to Next State All Outputs Are Low
Pinout: 16–Lead Plastic Package (Top View)
Q8 14 Q9 13 Osc Osc Reset Osc In Out 1 Out 2 12 11 10 9
MC54/74HC4060A
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) – 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ± 20 ± 25 ± 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† TSSOP Package† Storage Temperature Range mW Tstg TL – 65 to + 150 260 300
TC4069UBFT

TC4069UBFT


8
2007-10-01
TC4069UBP/UBF/UBFN/UBFT
RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice.
20070701-EN GENERAL
VIN = VDD
VOUT = 0.5 V, 4.5 V 5 4.0
⎯
Hale Waihona Puke 4.0⎯⎯
4.0
⎯
VOUT = 1.0 V, 9.0 V 10 8.0
⎯
8.0
⎯
⎯
8.0
⎯
VIH
mA
VOUT = 1.5 V, 13.5 V 15 12.0 ⎯ 12.0 ⎯
⎯ 12.0 ⎯
Input low voltage
|IOUT| < 1 μA
TC4069UBP/UBF/UBFN/UBFT
Note: This package is not available in Japan. Weight: 0.12 g (typ.)
7
2007-10-01
Package Dimensions
TC4069UBP/UBF/UBFN/UBFT
Weight: 0.06 g (typ.)
VDD VIN VOUT IIN PD Topr Tstg
VSS − 0.5 to VSS + 20
V
VSS − 0.5 to VDD + 0.5
V
VSS − 0.5 to VDD + 0.5
V
±10
mA
300 (DIP)/180 (SOIC)
HEF4049BT中文资料

HEF4049BT中文资料

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
Min Typ Max
3
-
15
0
-
VDD
−40 -
+85
-
-
3.75
-
-
0.5
-
-
0.08
Unit V V °C ns/V ns/V ns/V
HEF4049B_5
Product data sheet
Rev. 05 — 11 November 2008
© NXP B.V. 2008. All rights reserved.
6. Pinning information
6.1 Pinning
Fig 4. Pin configuration
HEF4049B
VDD 1 1Y 2 1A 3 2Y 4 2A 5 3Y 6 3A 7
VSS 8
16 n.c. 15 6Y 14 6A 13 n.c. 12 5Y 11 5A 10 4Y 9 4A 001aae602
HEF4049BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm