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±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。

Integrated Mixed-Signal SolutionsCopyright © 2003 SigmaTel, Inc. All rights reserved.All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc.SigmaTel, the SigmaTel logo, and combinations thereof are registered trademarks of SigmaTel, Inc. Other product names used in this pub-lication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or com-pleteness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential, or incidential damages.STIr4200USB/IrDA Bridge ControllerVersion 2.0 April ‘03OFFICIAL PRODUCT DOCUMENTATION3-4200-D1-2.0-0403STIr4200USB/IrDA Bridge Controller1.TABLE OF CONTENTS1. TABLE OF CONTENTS (2)1.1. List of Figures (3)1.2. List of Tables (3)2. PRODUCT OVERVIEW (4)2.1. Features (4)2.2. Description (4)2.3. Ordering Information (4)2.4. STIr4200 Block Diagram (5)3. CHARACTERISTICS AND SPECIFICATIONS (5)3.1. Absolute Maximum Ratings (5)3.2. Recommended Operating Conditions (5)3.3. Electrical Characteristics (6)4. FUNCTIONAL DESCRIPTION (6)4.1. Overview (6)4.2. USB Interface (7)4.3. Vendor-Specific Device Requests (7)4.3.1. Write Multiple Registers (7)4.3.2. Write One Register (7)4.3.3. Read Multiple Registers (8)4.3.4. Read ROM (8)4.3.5. Vendor Clear Stall (8)4.4. Digital IR Transceiver (9)4.5. FIFO Contents (9)5. IR FRAMING FORMATS (10)5.1. Transmit Frame Format (10)5.1.1. SIR Transmit Frame (10)5.1.2. FIR Transmit Frame (11)5.1.3. Receive Frame Format (12)5.1.3.1. SIR Receive Frame (12)5.1.3.2. FIR Receive Frame (13)6. DIGITAL IR TRANSCEIVER REGISTERS (14)6.1. Detailed STIr4200 Register Descriptions (14)6.1.1. FIFO Data Register (14)6.1.2. Mode and Baud Rate Registers (15)6.1.2.1. Mode Register (15)6.1.2.2. Baud Rate Register (15)6.1.3. Control Register (16)6.1.4. Sensitivity Register (17)6.1.5. Status Register (17)6.1.6. FIFO Count Registers (LSB,MSB) (18)6.1.6.1. FIFO Count LSB (18)6.1.6.2. FIFO Count MSB (18)6.1.7. DPLL Tune Register (18)6.1.8. IRDIG Setup Register (19)6.1.9. Test Register (19)7. PIN DESCRIPTION (20)7.1. STIr4200S 28-Pin SSOP Pin Description (20)8. PACKAGE DRAWINGS (21)STIr4200USB/IrDA Bridge Controller1.1.List of FiguresFigure 1. STIr4200 Block Diagram (5)Figure 2. Typical USB-IR Application (6)Figure 3. Block Diagram of Digital IR Transceiver (9)Figure 4. SIR Transmit Frame Format (10)Figure 5. FIR Transmit Frame Format (11)Figure 6. SIR Receive Frame Format (12)Figure 7. FIR Receive Frame Format (13)Figure 8. STIr4200S 28-Pin SSOP Pin Assignment Drawing (20)Figure 9. 28-Pin SSOP Package Drawing (21)1.2.List of TablesTable 1. Absolute Maximum Ratings (5)Table 2. Recommended Operating Conditions (5)Table 3. Electrical Characteristics (6)Table 4. Write Multiple Registers (7)Table 5. Write One Register (7)Table 6. Read Multiple Registers (8)Table 7. Read ROM (8)Table 8. Vendor Clear Stall (8)Table 9. IrLAP Frame (9)Table 10. Ir Transceiver Registers (14)Table 11. FIFO Data Register (14)Table 12. Mode Register (15)Table 13. Baud Rate Register (15)Table 14. Mode and Buad Rate Values for Required IrDA Modes of Operation (15)Table 15. Control Register (16)Table 16. Sensitivity Register (17)Table 17. Status Register (17)Table 18. FIFO Count LSB (18)Table 19. FIFO Count MSB (18)Table 20. DPLL Tune Register (18)Table 21. IRDIG Setup Register (19)Table 22. Test Register (19)Table 23. Pin Descriptions for STIr4200S 28-Pin SSOP Package (20)STIr4200USB/IrDA Bridge Controller 2.PRODUCT OVERVIEW2.1.Features•Low-power CMOS design•IrDA data rates from 2.4Kbps to 4Mbps •Obtains power from USB port •Uses standard IrDA transceivers•Optional LED driver for additional flexibility–LED driver capable of > 650ma @ 5V, 25% duty cycle •Full compliance to IrDA 1.3 and USB 1.1 specifications •4Kbyte FIFO buffer memory •Requires a single 12Mhz crystal•Windows 98/98SE/ME/2000/XP™ NDIS/USB driver •Low-profile 28-Pin SSOP package2.2.DescriptionThe SigmaTel STIr4200 is a low cost, low power, USB/IrDA Bridge Controller inte-grated circuit for enabling IrDA wireless data communications through a standard PC USB port. The STIr4200 directly interfaces to both single path and dual path receive IrDA transceiver module architectures and contains a USB controller, IrDA controller, interface logic, and memory buffer for full IrDA 1.3, 4Mbps data transfer rates. A block diagram is hown in Figure 1.The STIr4200 is bundled with a Windows 98/98SE/ME/2000/XP™ NDIS/USB driver for enabling the implementation of a cost effective USB/IrDA Adapter solution for wireless data communications.2.3.Ordering InformationPart Number PackageTemp Range Supply Range STIr4200S28-Pin SSOP0° C to +70° CVdd = 3.1 - 3.6VInfrared Communication TransmissionInfrared TransceiverSigmaTel USB/IrDA Bridge ControllerData TransferUSB Connection to the PCSTIr4200USB/IrDA Bridge Controller2.4.STIr4200 Block DiagramFigure 1. STIr4200 Block Diagram3.CHARACTERISTICS AND SPECIFICATIONS3.1.Absolute Maximum RatingsSymbol Parameter MIN MAX UNITS CONDITIONS P D Power Dissipation (Package constraint) mWT A Operating Temperature070°CT J Lead Solder Temperature260°C for 10 sec max.T S Storage Temperature-55125°CV CC Supply Voltage-0.3 V6VVmax Voltage at any pin V DD + 0.4V VESD Electrostatic Discharge (ESD)+/- 2KV V See Note 1 Note: 1.The device meets the JESD22-A114-A Electrostatic Discharge (ESD) Sensitivity T esting Human Body Model (HBM) requirements of +/- 2KV on all pins, except the TXDIODE pin (Pin 2), where the limit is +/1.5KV.Table 1. Absolute Maximum Ratings3.2.Recommended Operating ConditionsSymbol Parameter MIN TYP MAX UNITS CONDITION V DD Supply Voltage 3.1 3.3 3.6VT A Operating Temperature Range02570°CTable 2. Recommended Operating ConditionsSTIr4200USB/IrDA Bridge Controller3.3.Electrical CharacteristicsT A = 25°C A V DD = 3.3V unless otherwise specified. Cap Load = 50pF Symbol Parameter MIN TYP MAX UNITS CONDITIONI CC Active Supply Current1219mAI CC Suspend Supply Current1450µAV RXDH Receive Data Logic High V DD x 0.8VV RXDL Receive Data Logic Low0.8VV TXDH Transmit Data Logic High V DD x 0.6VV TXDL Transmit Data Logic Low V DD x 0.4VTable 3. Electrical Characteristics4.FUNCTIONAL DESCRIPTION4.1.OverviewThe STIr4200 consists of two major functional blocks, the USB controller and thedigital IR transceiver. The USB controller provides a Control, Bulk-In, and Bulk- Outendpoints to the USB host. The digital IR transceiver consists of a transmit andreceive interface that connects to an analog IR front end. Figure 1shows a block dia-gram of the device.This USB/IrDA Bridge Controller has full interface capability to connect between aUSB bus , and an IrDA-compatible infrared transceiver device. A simplified sche-matic of this arrangement is shown in Figure 2.Figure 2. Typical USB-IR ApplicationSTIr4200USB/IrDA Bridge ControllerB InterfaceThe USB interface to the host controller includes a Control endpoint, a Bulk-In end-point, and a Bulk-Out endpoint. The USB controller supports the USB 1.1 specifica-tion. Hence, it supports all standard functionality associated with deviceenumeration, standard USB device requests, etc. In addition, there is a set of ven-dor specific commands provided to allow a USB driver to access registers in theDigital IR Transceiver and ROM in the USB controller.Note: The STIr4200 device conforms to all of the USB 1.1 specifications with oneexception of the "get_interface" command. This command is used only during USBconformance testing, and during that testing, improper operation will be noted ontest results. However, the software drivers provided by SigmaTel, Inc. do NOT usethat command at all, and this does NOT cause any problem of any kind in operation.A waiver for this command has been obtained from USBIF by SigmaTel, Inc. Thiscommand is not used by the software, and therefore has no effect on device andsystem operation. The only time this "get_interface" command is even accessed isduring USB conformance testing.4.3.Vendor-Specific Device Requests4.3.1.Write Multiple RegistersThe write multiple registers vendor specific command allows the user to write multi-ple sequential registers to the Digital IR Transceiver. Each register is one byte wide,so the command indicates first register to write, the number of registers to write, andthe data phase supplies the data for those registers.Offset Field Size Value (hex)Description0bmRequestType10x40Host to device, vendor type, device recipient1Brequest10x00Write multiple registers2Wvalue2Not used (0x0000)4Windex20x0001–0x000f First register to write6Wlength20x0001–0x000f Number of registers to writeData phase1-15 bytes of Register DataTable 4. Write Multiple Registers4.3.2.Write One RegisterThe write one register vendor specific command allows the user to write a singleregister to the Digital IR Transceiver.Offset Field Size Value (hex)Description0bmRequestType10x40Host to device, vendor type, device recipient1Brequest10x03Write one register2Wvalue2LSB contains data The data to write the register4Windex20x0001 – 0x000f Register to write6Wlength2Not used (0x0000)Table 5. Write One RegisterSTIr4200USB/IrDA Bridge Controller4.3.3.Read Multiple RegistersThe read multiple registers vendor specific command allows the user to read multi-ple sequential registers from the Digital IR Transceiver. Each register is one bytewide, so the command indicates the first register to read, the number of registers toread, and the responding data phase supplies the data from those registers. Thiscommand is also used for the case of reading only one register.Offset Field Size Value (hex)Description0bmRequestType10xc0Device to host, vendor type, device recipient1BRequest10x01Read multiple registers2Wvalue2Not used (0x0000)4Windex20x0001 – 0x000f First register to read6Wlength20x0001 – 0x000f Number of registers to readTable 6. Read Multiple Registers4.3.4.Read ROMThe read ROM vendor specific command allows the user to read the contents of theUSB controller endpoint zero ROM. This is primarily a debug feature that allows ver-ification of the endpoint zero ROM contents. Only 64 bytes of ROM data can berequested at a time. The responding data phase supplies the data from the endpointzero ROM.Offset Field Size Value (hex)Description0BmRequestType10xc0Device to host, vendor type, device recipient1Brequest10x02Read ROM2Wvalue2Not used (0x0000)4Windex20x0000–0x00ff Base ROM address6Wlength20x01–0x0040Number of ROM locations to read (64 bytesmax per request)Table 7. Read ROM4.3.5.Vendor Clear StallThe vendor clear stall command is included as a potential work around for limita-tions in early versions of the Microsoft™ USB driver stack. Although not a concernwith the latest operating systems, the earlier versions could have the possibility thatthe USB driver stack would not properly clear endpoint stalls. The standard deviceclear stall request is also supported.Offset Field Size Value (hex)Description0BmRequestType10x42Device to host, vendor type, endpointrecipient1Brequest10x01Clear endpoint stall2Wvalue2Not used (0x0000)4Windex20x0000 – 0x0002Endpoint on which to clear stall6Wlength2Not used (0x0000)Table 8. Vendor Clear StallSTIr4200USB/IrDA Bridge Controller4.4.Digital IR TransceiverThe Digital IR Transceiver is responsible for driving the transmit diode and receivingthe digital input from an analog IR front end. The primary components are the trans-mit modulator, the receive demodulator, the FIFO, the analog transmit section, andthe register array. Figure 3 shows a block diagram of the Digital IR Transceiver. Byprogramming the registers in the register array, the device’s operation is deter-mined. Various registers are used to specify operations such as the modulationscheme, the baud rate, the current frame size in the FIFO, the RX input selection,etc. The FIFO is 4K bytes in size.Figure 3. Block Diagram of Digital IR TransceiverIn steady state transmit operation, the USB controller is filling the FIFO with datawhile the Digital IR Transceiver is emptying it via the transmit modulator. In steadystate receive operation, the USB controller is emptying the FIFO while the RXdemodulator is filling the FIFO.4.5.FIFO ContentsData sent to the USB controller for transmission by the TX modulator must be orga-nized into frames. An IrLAP frame is made up of the following portions:BOF A C I FCS EOFBOF Beginning of frame(s)A Address fieldC Control fieldI Information fieldFCS Frame check sequence (CRC)EOF End of frameTable 9. IrLAP FrameThe NDIS IR stack only provides the A, C, and I fields to the NDIS mini-port devicedriver that communicates with the USB/IrDA transceiver. Hence, the mini-port mustfill in the BOF, FCS, and EOF fields. Additionally, the driver must add a 2-byteheader ID code and a 2-byte frame size to the packet before passing the packetonto the USB stack for delivery to the USB/IrDA transceiver. There are additionalspecial characters and required escape sequences depending upon the rate oftransfer. Details on the frame format for each of the support rates is discussed in thefollowing sections.STIr4200USB/IrDA Bridge Controller5.IR FRAMING FORMATS5.1.Transmit Frame Format5.1.1.SIR Transmit FrameThe SIR rates include 2.4, 9.6, 19.2, 38.4, 57.6, and 115.2 Kbps. For SIR, the framepresented to the USB bulk transmit interface must be organized in the followingfashion as shown in Figure 4.Figure 4. SIR Transmit Frame Format5.1.2.FIR Transmit FrameThe FIR rate is 4 Mbps The frame organization is detailed in Figure 5.5.1.3.Receive Frame FormatData received into the STIr4200 FIFO from the digital infrared interface can beaccessed by performing a bulk read on the USB interface. The received data con-tains the encoded infrared data. The STIr4200 does not perform any frame valida-tion or CRC-Checking. Multiple frames may exist within one bulk read dependingupon the size of the bulk read. However, the end of the bulk read buffer may notnecessarily coincide with the end of an infrared frame. It is highly likely that the dataat the end of a bulk read will be a partial frame. The remaining frame data will beacquired in the next bulk read.The bulk data thus contains start-of-frame (BOF) characters, end-of-frame (EOF)characters, and escape characters that delineate the actual frame. It is the responsi-bility of the host software to reconstruct the frame.5.1.3.1.SIR Receive FrameThe standard SIR encoding scheme provides all information needed to delineatethe encoded receive frames. Figure 6 summarizes the SIR receive frame formatencoding scheme.Figure 6. SIR Receive Frame Format5.1.3.2.FIR Receive FrameThe FIR encoding scheme is modified slightly from the standard scheme. The char-acter 0x7E is used to delineate the BOF and EOF. The STIr4200 escapes three characters in the data field on receive, 0x7F, 0x7E and 0x7D, which allows the 0x7E characters used as BOF and EOF to be unique. The 0x7E character can then be used to delineate the infrared frame boundaries. This hardware escaping in the data portion is specific to the STIr4200, and the software must un-escape the data portion of the received frame to restore the original data. Figure 7 summarizes the FIR receive frame format encoding scheme.Figure 7. FIR Receive Frame Format6.DIGITAL IR TRANSCEIVER REGISTERS6.1. Detailed STIr4200 Register Descriptions6.1.1.FIFO Data RegisterOffset 0Offset Description AccessBit Position 76543210FIFO Data R/W Reserved 1Mode Register R/W FIRReservedSIRASK FASTRXEN FFRSTEN FFSPRST PDCLK(8)2Baud Rate Register R/W PDCLK(7: 0)3Control Register R/WSDMODE RXSLOW DLOOP1TXPWDRXPWDTXPWR(1: 0)SRESET 4Sensitivity Register RXDSNS(2: 0)BSTUFF R/W SPWIDTH R/W ID(2)ROID(1)ROID(0)RO5Status Register EOFRAME RO FFUNDER ROC FFOVERROCFFDIR ROFFCLR WO FFEMPTY RO FFRXERR ROC FFTXERRROC6FIFO Count (Note 1)Register (LSB)RO FFCNT(7:0)7FIFO Count (Note 1) Register (MSB)RO 0FFCNT(12: 8)8DPLL Tune Register RO DPCNT(5: 0)LONGP(1: 0)9IRDIG Setup RegisterR/W RXHIGHTXLOWReserved Reserved ReservedReserved Reserved Reserved10Reserved R/W Reserved 11Reserved R/W Reserved 12Reserved R/W Reserved 13Reserved R/W Reserved 14Reserved R/W Reserved15Test RegisterR/WPLLDWN LOOPIR LOOPUSB TSTENATSTOSC(3: 0)R/W : Read/WriteRO : Read onlyROC : Read only, clear on read WO : Write onlyNote: 1.Due to double buffering, FFCNT could be off by as much as 3 bytesTable 10. Ir Transceiver Registers7654321FIFO Data ReservedDefault State 00000Bit NumberBit Mnemonic Access Function7 – 0ReservedR/WThe FIFO data register is used internally by the USB interface to access the FIFO data in the digital infrared block. Although this register is accessible through the USB interface, it should never be accessed during normal operation.Table 11. FIFO Data Register6.1.2.Mode and Baud Rate RegistersOffset 1 and 26.1.2.1.Mode RegisterOffset 16.1.2.2.Baud Rate RegisterOffset 2Below is a table of values to be written to the mode and baud rate registers to setthe required IrDA modes of operation:76543210Mode Register FIR ReservedSIR ASK FASTRXEN FFRSTEN FFSPRST PDCLK(8)Default State100Bit Number Bit Mnemonic AccessFunction7FIR R/W When set, puts the infrared modulators into fast infrared mode (4PPM). Must be mutually exclusive with the SIR bit.6Reserved RO Reserved. Write as zero.5SIR R/W When set, puts the infrared modulators into slow infrared mode. Must be mutually exclusive with the FIR bit.4ASK R/W When set, puts the infrared modulators into amplitude shift keying infrared mode.3FASTRXEN R/W Enables simultaneous reads and writes to/from the FIFO.2FFRSTEN R/W Allows the FIFO receive shift register to be automatically reset in FIR mode.1FFSPRST R/W Manually resets the FIFO shift register. Must be set to ‘1’ to release the FIFO shift register from reset.0PDCLK(8)R/WMSB of baud rate register.Table 12. Mode Register76543210Baud Rate Register PDCLK(7: 0)Default State1110111Bit Number Bit Mnemonic AccessFunction7:0PDCLK (7 : 0)R/WSets the divide ratio of the PLL for the infrared modulator/demodulator.Table 13. Baud Rate RegisterOperational ModeSpeed Mode RegisterBaud Rate RegisterFIR4.0 Mbps 0x800x02SIR115.2 Kbps 0x200x0957.6 Kbps0x200x1338.4 Kbps 0x200x1D 19.2 Kbps 0x200x3B 9.6 Kbps 0x200x772.4 Kbps0x210xDFTable 14. Mode and Buad Rate Values for Required IrDA Modes of Operation6.1.3.Control RegisterOffset 376543210 Control Register SDMODE RXSLOW Reserved TXPWD RXPWD TXPWR(1: 0)SRESET Default State00000000Bit Number Bit Mnemonic Access Function7SD/MODE R/W Use this bit only when the STIr4200 is connected to a TEMIC style infraredtransceiver. This bit is used to put the infrared transceiver into the powerdown state or toggle the transceiver between high and low speed.POWER DOWN STATE: Set the SD/MODE bit to enter the power down state.Clear the SD/MODE bit to exit the power down state.SET TEMIC HIGH SPEED: Set the FIR bit (bit 7) in the Mode Register, thenset SD/MODE bit, then clear SD/MODE bit.SET TEMIC LOW SPEED: Clear the FIR bit (bit 7) in the Mode Register, thenset the SD/MODE bit, then clear the SD/MODE bit.The sequences described above for setting the high or low speed modeenables a state machine in the STIr4200 to automatically toggle the TXDATAand UOUT (SD/MODE) pins on the STIr4200.6RXSLOW R/W When set, selects RXSLOW as the receive input. When cleared, selectsRXFAST as the receive input.5Reserved R Reserved4TXPWD R/W When set, powers down the infrared transmitter (modulator).3RXPWD R/W When set, powers down the infrared receiver (demodulator).2-1TXPWR(1: 0)R/W Sets the internal pull down resistance to control the current presented to thetransmit diode.00 : HIGH (max current)01 : MED HIGH10 : MED LOW11 : LOW (min current)0SRESET R/W When set, performs soft reset of the infrared modulator/demodulator.Table 15. Control Register6.1.4.Sensitivity RegisterOffset 476543210 Sensitivity Register RXDSNS(2: 0)Reserved SPWIDTH ID(2: 0)Default State00100ID(2)ID(1)ID(0) Bit Number Bit Mnemonic Access Function7-5RXDSNS(2: 0)R/W Used to program the sensitivity of the DRS demodulator. The correspondingsamples is the number of consecutive samples of an IrDA pulse it takes thedigital detector to declare the presence of a valid IrDA pulse.Value FIR SIR0001400128010312011416100520101Illegal24110Illegal28111Illegal Illegal 4Reserved RO Reserved. Write as zero.3SPWIDTH R/W SIR transmit pulse width. When cleared, the pulse width for SIR modetransmission is 1.6usec. When set, the pulse width is 3/16th the bit rate.2-0ID(2: 0) (Note 1)RO Revision ID of the chip.Table 16. Sensitivity Register6.1.5.Status RegisterOffset 576543210 Status Register Reserved FFDIR FFCLR FFEMPTY Reserved Default State01010Bit Number Bit Mnemonic Access Function7-5Reserved N/A Reserved4FFDIR RO When set, the FIFO is in transmit mode. When cleared, the FIFO is in receive mode.3FFCLR WO When set, clears the FIFO by resetting the pointers to the empty position. This bitmust then be cleared to enable operation of the FIFO. Failing to do so, willprohibit operation of the FIFO. The state of the bit can not be read.2FFEMPTY RO When set, indicates there is no data in the FIFO.1-0Reserved N/A ReservedTable 17. Status Register6.1.6.FIFO Count Registers (LSB,MSB)Offset 6&76.1.6.1.FIFO Count LSBOffset 676543210 FIFO Count Register (LSB)FFCNT(7: 0)Default State00000000Bit Number Bit Mnemonic Access Function7-0FFCNT(7:0)RO When combined with the FIFO Count Registers (MSB), indicates the numberof bytes in the FIFO.Table 18. FIFO Count LSB6.1.6.2.FIFO Count MSBOffset 776543210 FIFO Count Register (MSB)Reserved FFCNT(12: 8)Default State00000000Bit Number Bit Mnemonic Access Function7-5Reserved RO Write as zeros.4-0FFCNT(12:8)RO When combined with the FIFO Count Registers (LSB), indicates the numberof bytes in the FIFO.Table 19. FIFO Count MSB6.1.7.DPLL Tune RegisterOffset 876543210 DPLL Tune Register DPCNT(5: 0)LONGP(1: 0) Default State01010010Bit Number Bit Mnemonic Access Function7-2DPCNT(5: 0)R/W Sets the sensitivity of the receiver’s digital PLL. This bit should be used forchip debug purposes only. This register setting only affects FIR mode. Thedefault setting is proper for normal operation.1-0LONGP(1: 0)R/W Sets the sensitivity of the pulse detector of the receiver. These bits should beused for chip debug purposes only.Table 20. DPLL Tune Register6.1.8.IRDIG Setup RegisterOffset 976543210 IRDIG Setup Register RXHIGH TXLOW ReservedDefault State000Bit Number Bit Mnemonic Read/Write Access Function7RXHIGH R/W When set, this bit inverts the polarity of the data received by thedigital interface on the RXFAST and RXSLOW pins.6TXLOW R/W When set, this bits inverts the polarity of the data transmitted bythe digital interface on the TXDATA pin.5-0Reserved R/W ReservedTable 21. IRDIG Setup Register6.1.9.Test RegisterOffset 1576543210Test Register PLLDWN LOOPIR LOOPUSB Reserved TSTOSC(3 : 0)Default State00000000Bit Number Bit Mnemonic Read/Write Access Function7PLLDWN R/W When set, powers down the secondary infrared transceiver PLL.This bit should be cleared for SIR operation. Two independentPLLs are required in this mode of operation. This bit should beset for FIR operation since the infrared transceiver uses the USBPLL in this mode of operation.6LOOPIR R/W When set, puts the infrared transceiver into internal loop backusing the FIFO to buffer data. This bit should be used for chipdebug purposes only.5LOOPUSB R/W When set, puts the USB interface into loop back mode using theFIFO to buffer data. This bit should be used for chip debugpurposes only.4TSTENA R/W Enables the oscillator to be powered down while in USB SuspendMode.3-0TSTOSC(3: 0)R/W Sets the bias currents for the crystal oscillator circuitry. These bitsshould be used for chip debug purposes only.Table 22. Test Register7.PIN DESCRIPTION7.1.STIr4200S 28-Pin SSOP Pin DescriptionPin NumberSignal Name Type Description 1TX DIODE GND PWR TX DIODE power supply ground 2TX DIODE O Optional LED driver output 3NC No connect 4NC No connect 5RX FAST I Receive data from IR module (Fast)6TX DATA O Transmit data output to IR module 7RX SLOW I Receive data from IR module (Slow)8U OUT O SD/Mode control to IR module 9DGND PWR Digital power supply ground 10V DD PWR Digital power supply (+)11AGND PWR USB transceiver power supply ground 12D NEG I/OUSB interface negative (-) data 13NC No connect 14NC No connect 15NC No connect 16NC No connect 17D POS I/O USB interface positive (+) data 18V DA PWR USB transceiver power supply (+)19U IN I/O Test 20TST-CLK I Test clock input 21TSTD I/O Test data input/output 22TST_EN I Test enable 23RESETZ I Master reset, active low 24GNDD PWR Power supply ground 25XTALI I 12Mhz crystal/clock input 26XTALO O 12Mhz crystal/clock output 27NC No connect 28NC No connectTable 23. Pin Descriptions for STIr4200S 28-Pin SSOP PackageTX DIODE GNDTX DIODEN/C N/C RX FAST TX DATA RX SLOWU OUTD IGITAL GNDV DDA NALOG GNDD NEG N/C N/CN/C N/C X TALO X TALI G ND D R ESET Z T ST_EN T ST D T ST-CLK U IN V DA D POS N/C N/CFigure 8. STIr4200S 28-Pin SSOP Pin Assignment Drawing。

Data Sheet No. PD60278Block DiagramPackagesProduct SummaryI O +/- 1.5 A / 1.5 A V OUT 6 V - 20 V t on/off (typ.)50 ns & 50 nsDUAL LOW SIDE DRIVERFeatures•Gate drive supply range from 6 V to 20 V •CMOS Schmitt-triggered inputs•Matched propagation delay for both channels • Outputs out of phase with inputs (IRS4426)• Outputs in phase with inputs (IRS4427)• OutputA out of phase with inputA andoutputB in phase with inputB (IRS4428)• RoHS compliantDescriptionsThe IRS4426/IRS4427/IRS4428 are low voltage,high speed power MOSFET and IGBT driver. Pro-prietary latch immune CMOS technologies en-able ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for mini-mum driver cross-conduction. Propagation delays between two channels are matched.8 Lead PDIP 1IRS4426/IRS4427/IRS4428(S)PbF8-Lead SOIC 2IRS4426/IRS4427/IRS4428(S)PbFAbsolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to GND. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.Recommended Operating ConditionsThe input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND.DC Electrical CharacteristicsV BIAS (V S ) = 15 V, T A = 25 °C unless otherwise specified. The V IN and I IN parameters are referenced to GND and are applicable to input leads: INA and INB. The V O and I O parameters are referenced to GND and are applicable to the 3IRS4426/IRS4427/IRS4428(S)PbFDC Electrical Characteristics cont.V BIAS (V S ) = 15 V, T A = 25 °C unless otherwise specified. The V IN , and I IN parameters are referenced to GND and are applicable to input leads: INA and INB. The V O and I O parameters are referenced to GND and are applicable to the 4IRS4426/IRS4427/IRS4428(S)PbFFunctional Block Diagram IRS4426AC Electrical CharacteristicsV BIAS (V S ) = 15 V, CL = 1000 pF, T A = 25 o C unless otherwise specified.Functional Block Diagram IRS44275 6IRS4426/IRS4427/IRS4428(S)PbFFunctional Block Diagram IRS4428 7IRS4426/IRS4427/IRS4428(S)PbFV S INA GND INBINA GND INBINA GND INBOUTA V S OUTBOUTA V S OUTBOUTA V S OUTB8 Lead PDIPINA OUTA V SINA GND INBINA GND INBGND INBOUTA V S OUTBOUTA V S OUTBV S OUTB8 Lead SOICIRS4426/IRS4427/IRS4428(S)PbF INA (IRS4426, IRS4428)INB (IRS4426)INA (IRS4427)INB (IRS4427, IRS4428)OUTAOUTBFigure 1. Timing DiagramINA (IRS4426, IRS4428)INB (IRS4426)INA (IRS4427)INB (IRS4427, IRS4428)OUTA OUTBtftd2td1trFigure 2. Switching Time Waveforms8IRS4426/IRS4427/IRS4428(S)PbFSS Array IRS4428Figure 3. Switching Time Test Circuits9IRS4426/IRS4427/IRS4428(S)PbF10 11IRS4426/IRS4427/IRS4428(S)PbFIRS4426/IRS4427/IRS4428(S)PbF12IRS4426/IRS4427/IRS4428(S)PbF13IRS4426/IRS4427/IRS4428(S)PbF14IRS4426/IRS4427/IRS4428(S)PbF15IRS4426/IRS4427/IRS4428(S)PbFIRS4426/IRS4427/IRS4428(S)PbF1718IRS4426/IRS4427/IRS4428(S)PbFCLOADED TAPE FEED DIRECTIONTape & Reel 8-lead SOIC 19IRS4426/IRS4427/IRS4428(S)PbF8-Lead PDIP IRS4426PbF 8-Lead SOIC IRS4426SPbF 8-Lead PDIP IRS4427PbF 8-Lead SOIC IRS4427SPbF 8-Lead PDIP IRS4428PbF 8-Lead SOIC IRS4428SPbFORDER INFORMATIONLEADFREE PART MARKING INFORMATIONPer SCOP 200-002The SOIC-8 is MSL2 qualified.This product has been designed and qualified for the industrial level.Qualification standardscan be found at IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105Data and specifications subject to change without notice. 11/20/2006。

March 26, 2010POWER MANAGEMENT 110-Channel, Integrated, High Efficiency120 White LED DriverSC442Typical Application CircuitFeaturesWide input voltage range from 4.5V to 21V 42V maximum operating output voltageProgrammable LED current up to 30mA per string +/- 1% current matching Integrated 3A switch Low current sink voltage Up to 91% efficiencyFlexible LED configurations Mismatched LED channels Disable individual channel(s) Parallel channels for high LED current PWM dimming capability Up to 50kHz dimming frequency >500:1 dimming rangeSwitching frequency: 500kHz - 1MHz Parallel device operation with Sync Pin Protection features: Adjustable OVP Cycle-by-cycle current limit LED short channel with disable /Open channnel Over-Temperature protectionMLPQ-28 lead-free package (WEEE and RoHS compliant), 4×4mm × 0.6mmApplicationsAutomotive LCD Backlighting Desktop monitors Notebook PCsPortable TVs⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹⏹DescriptionThe SC442 is a 10-channel, high efficiency integrated step-up (boost) driver IC capable of powering up to 120 WLEDs. The device has a wide input voltage of 4.5V to 21V with no internal regulator or bypass capacitor required. The wide input range, up to 42V output voltage and flexible implementation make it the ideal LED backlight driver solution for medium to large LCD displays. The current sink channels are programmed with an external resistor up to 30mA each.Channel-channel current matching is +/-1% . The device disables open or shorted LEDs by disabling only the affected LED channel; thus increasing LCD panel life. Channel-channel LED mismatch voltage is accomodated by adjusting the SCPSET resistor. The current sink channels may be operated in parallel for increased LED current. Unused channels are be disabled by connecting the pin to the input voltage.Losses in the switching device and current sinks are minimized across the operating range; yielding >90% efficiency and excel-lent battery life for portable systems.The device accepts PWM dimming up to 50kHz. Maximum dim-ming range is greater than 500:1 with excellent linearity for opti-mum PWM dimming characteristics. The high frequency dimming capability (>20kHz) eliminates audio emissions and allows small ceramic output capacitors.Switching frequency is programmable from 200kHz to 1MHz; allowing efficiency versus L/C sizing tradeoffs across the input/output voltage range. Alternatively, the SYNC pin allows the designer to synchronize the switching frequency to an external system clock and, if necessary, a parallel SC442 device - eliminating potential system intermodulation and interference problems.Over-temperature shutdown protects the IC from over-heating under abnormal conditions. The device is available in a small 4mmx4mm MLPQ-28 pin package with 0.6mm maximum height and is fully WEEE and RoHS compliant./分销商库存信息: SEMTECHSC442ULTRT。