MT8865XE中文资料

NAND Flash MemoryMT29F4G08ABADAH4, MT29F4G08ABADAWP, MT29F4G08ABBDAH4, MT29F4G08ABBDAHC, MT29F4G16ABADAH4, MT29F4G16ABADAWP, MT29F4G16ABBDAH4, MT29F4G16ABBDAHC, MT29F8G08ADADAH4,MT29F8G08ADBDAH4, MT29F8G16ADADAH4, MT29F8G16ADBDAH4, MT29F16G08AJADAWPFeatures•Open NAND Flash Interface (ONFI) 1.0-compliant1•Single-level cell (SLC) technology •Organization–Page size x8: 2112 bytes (2048 + 64 bytes)–Page size x16: 1056 words (1024 + 32 words)–Block size: 64 pages (128K + 4K bytes)–Plane size: 2 planes x 2048 blocks per plane–Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks 16Gb: 16,384 blocks•Asynchronous I/O performance–t RC/t WC: 20ns (3.3V), 25ns (1.8V)•Array performance–Read page: 25µs 3–Program page: 200µs (TYP: 1.8V, 3.3V)3–Erase block: 700µs (TYP)•Command set: ONFI NAND Flash Protocol •Advanced command set–Program page cache mode4–Read page cache mode 4–One-time programmable (OTP) mode–Two-plane commands 4–Interleaved die (LUN) operations–Read unique ID–Block lock (1.8V only)–Internal data move•Operation status byte provides software method for detecting–Operation completion–Pass/fail condition–Write-protect status•Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion•WP# signal: Write protect entire device •First block (block address 00h) is valid when ship-ped from factory with ECC. For minimum required ECC, see Error Management.•Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-cles are less than 1000•RESET (FFh) required as first command after pow-er-on•Alternate method of device initialization (Nand_In-it) after power up (contact factory)•Internal data move operations supported within the plane from which data is read•Quality and reliability–Data retention: 10 years–Endurance: 100,000 PROGRAM/ERASE cycles •Operating voltage range–V CC: 2.7–3.6V–V CC: 1.7–1.95V•Operating temperature:–Commercial: 0°C to +70°C–Industrial (IT): –40ºC to +85ºC•Package–48-pin TSOP type 1, CPL2–63-ball VFBGANotes: 1.The ONFI 1.0 specification is available at2.CPL = Center parting line.3.See Program and Erase Characteristics fort R_ECC and t PROG_ECC specifications.4.These commands supported only with ECCdisabled.Figure 78: TWO-PLANE BLOCK ERASERE#CE#ALECLE I/Ox R/B#WE#Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS CycleCE#CLE ALE RE#I/Ox4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryTwo-Plane OperationsInterleaved Die (Multi-LUN) OperationsIn devices that have more than one die (LUN) per target, it is possible to improve per-formance by interleaving operations between the die (LUNs). An interleaved die (multi-LUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die (LUN) is busy (RDY = 0).Interleaved die (multi-LUN) operations are prohibited following RESET (FFh), identifi-cation (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the die (LUNs) on the target.During an interleaved die (multi-LUN) operation, there are two methods to determine operation completion. The R/B# signal indicates when all of the die (LUNs) have finish-ed their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the READ STATUS ENHANCED (78h) command can report the status of each die (LUN) in-dividually.If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h),then the die (LUN) is able to accept the data for another cache operation when status register bit 6 is 1. All operations, including cache operations, are complete on a die when status register bit 5 is 1.During and following interleaved die (multi-LUN) operations, the READ STATUS (70h)command is prohibited. Instead, use the READ STATUS ENHANCED (78h) command to monitor status. This command selects which die (LUN) will report status. When two-plane commands are used with interleaved die (multi-LUN) operations, the two-plane commands must also meet the requirements in Two-Plane Operations.See Command Definitions for the list of commands that can be issued while other die (LUNs) are busy.During an interleaved die (multi-LUN) operation that involves a PROGRAM series (80h-10h, 80h-15h) operation and a READ operation, the PROGRAM series operation must be issued before the READ series operation. The data from the READ series opera-tion must be output to the host before the next PROGRAM series operation is issued.This is because the 80h command clears the cache register contents of all cache regis-ters on all planes.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryInterleaved Die (Multi-LUN) OperationsError ManagementEach NAND Flash die (LUN) is specified to have a minimum number of valid blocks(NVB) of the total available blocks. This means the die (LUNs) could have blocks thatare invalid when shipped from the factory. An invalid block is one that contains at leastone page that has more bad bits than can be corrected by the minimum required ECC.Additional blocks can develop with use. However, the total number of available blocksper die (LUN) will not fall below NVB during the endurance life of the product.Although NAND Flash memory devices could contain bad blocks, they can be usedquite reliably in systems that provide bad block management and error-correction algo-rithms. This type of software environment ensures data integrity.Internal circuitry isolates each block from other blocks, so the presence of a bad blockdoes not affect the operation of the rest of the NAND Flash array.NAND Flash devices are shipped from the factory erased. The factory identifies invalidblocks before shipping by attempting to program the bad block mark into every loca-tion in the first page of each invalid block. It may not be possible to program every loca-tion with the bad block mark. However, the first spare area location in each bad block isguaranteed to contain the bad block mark. This method is compliant with ONFI FactoryDefect Mapping requirements. See the following table for the first spare area locationand the bad block mark.System software should check the first spare area location on the first page of eachblock prior to performing any PROGRAM or ERASE operations on the NAND Flash de-vice. A bad block table can then be created, enabling system software to map aroundthese areas. Factory testing is performed under worst-case conditions. Because invalidblocks could be marginal, it may not be possible to recover this information if the blockis erased.Over time, some memory locations may fail to program or erase properly. In order toensure that data is stored properly over the life of the NAND Flash device, the followingprecautions are required:•Always check status after a PROGRAM or ERASE operation•Under typical conditions, use the minimum required ECC (see table below)•Use bad block management and wear-leveling algorithmsThe first block (physical block address 00h) for each CE# is guaranteed to be validwith ECC when shipped from the factory.Table 21: Error Management DetailsTable 21: Error Management Details (Continued)。

概述芯片是单线归零码9通道LED （发光二极管显示器）恒流驱动控制芯片，采用单线归零码通讯协议。

芯片内部集成有单线归零码数字接口、数据锁存器、LED 输出恒流驱动、电源稳压模块、内置RC 振荡器、输出数据自动整形转发等电路。

芯片通过外围MCU 控制实现该芯片的单独辉度、级联控制等实现户外大屏的彩色点阵发光控制。

本产品性能优良，质量可靠。

特点输出端口耐压>26V芯片内置稳压管，电源端需串电阻到IC VDD 脚，无需外加稳压管PWM 辉度调节电路（256级辉度可调），扫描频率1KHZ内置双RC 振荡，并根据数据线上信号进行时钟同步，在接受完本单元的数据后能自动将后续数据进行整形转发内置上电复位电路归零码通讯协议级联接口，能通过一根信号线完成数据的接收与解码当刷新速率30帧/秒时，级联数不小于1024点 数据发送采用800Kbps 的归零码单线通讯协议 上电默认不亮；没有外控数据1秒后芯片自动R=>G=>B 循环显示封装：DIP16、SOP16、DIP14、SOP14应用点光源 护栏管 软灯条户内外大屏等典型应用电路800K 传输速率的9通道LED 输出显示（SEL 端口悬空或者接地）深圳市昊海鑫科技有限公司联系人:陈功 186********QQ:SOP16/DIP16SOP14/DIP14极限参数推荐工作范围(无特殊说明，TA=-40~+85℃,GND=0V)电气参数开关特性内部框图功能描述芯片采用单线归零码协议通讯传输。

芯片在上电复位以后，接收DIN1端传输的数据，接受72bit数据后，DOUT端口开始转发数据，提供下一个芯片的输入数据。

在转发之前，DOUT端口一直拉低。

此时芯片将不接收新的数据，芯片输出端口Rn/Gn/Bn根据接收到的归零码数据，发出相应的不同占空比的信号，该信号周期在1ms左右。

如果DIN1端输入信号为RESET信号，芯片将接收到的数据送显示，芯片将在该信号结束后重新接收新的数据，在接收完本芯片的归零码数据后，通过DOUT端口转发数据。

Output Driver ImpedanceThe output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is per-formed. Output specifications refer to the default output driver unless specifically sta-ted otherwise. A functional representation of the output buffer is shown below. The out-put driver impedance R ON is defined by the value of the external reference resistor RZQ as follows:•R ON,x = RZQ /y (with RZQ = 240ȍ ±1%; x = 34ȍ or 40ȍ with y = 7 or 6, respectively)The individual pull-up and pull-down resistors R ON(PU) and R ON(PD) are defined as fol-lows:•R ON(PU) = (V DDQ - V OUT )/|I OUT |, when R ON(PD) is turned off•R ON(PD) = (V OUT )/|I OUT |, when R ON(PU) is turned offFigure 28: Output DriverOutput driverChip in drive modeV DDQV SSQV OUTDQ34 Ohm Output Driver ImpedanceThe 34ȍ driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34ȍ driver only. Its impedance R ON is de-fined by the value of the external reference resistor RZQ as follows: R ON34 = RZQ/7 (with nominal RZQ = 240ȍ ±1%) and is actually 34.3ȍ ±1%.Table 38: DDR3L 34 Ohm Driver Impedance CharacteristicsNotes: 1.Tolerance limits assume RZQ of 240˖ ±1% and are applicable after proper ZQ calibra-tion has been performed at a stable temperature and voltage: V DDQ = V DD ; V SSQ = V SS ).Refer to DDR3L 34 Ohm Output Driver Sensitivity (page 69) if either the temperature or the voltage changes after calibration.2.Measurement definition for mismatch between pull-up and pull-down (MM PUPD ). Meas-ure both R ON(PU) and R ON(PD) at 0.5 × V DDQ :MM PUPD = ×100R ON(PU) - R ON(PD)R ON,nom3.For IT and AT devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (T C ).A larger maximum limit will result in slightly lower minimum currents.DDR3L 34 Ohm DriverUsing Table 39, the 34ȍ driver’s current range has been calculated and summarized in Table 40 (page 68) V DD = 1.35V , Table 41 for V DD = 1.45V , and Table 42 (page 69) for V DD = 1.283V . The individual pull-up and pull-down resistors R ON34(PD) and R ON34(PU)are defined as follows:•R ON34(PD) = (V OUT )/|I OUT |; R ON34(PU) is turned off•R ON34(PU) = (V DDQ - V OUT )/|I OUT |; R ON34(PD) is turned offTable 39: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance CalculationsTable 40: DDR3L 34 Ohm Driver I OH /I OL Characteristics: V DD = V DDQ = DDR3L@1.35VTable 41: DDR3L 34 Ohm Driver I OH /I OL Characteristics: V DD = V DDQ = DDR3L@1.45V 4Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance。

警告本手册仅供有经验的维修人员使用，不使用于一般消费者，手册中没有对非技术人员企图维修本产品而存在的潜在危害提出警告或者提醒。

电器产品应由有经验的专业技术人员进行维护和修理，任何其它人企图对本手册涉及的产品进行维护和修理将有可能受到严重伤害甚至生命危险。

1 产品标准1.1 机芯概述本机芯使用MSTAR的高集成芯片MSD389I，内置32bit RISC CPU，是单芯片数模一体化，内置DEMOdulation的DVB-C和一路串行或并行TS流，可支持DMB-T。

多媒体部分设有两路USB接口，一路网络接口可实现下载和在线收看功能，支持酷K和网络酷开功能。

功放采用的是STA335BW，支持2.1声道。

本机芯的软件架构用的是 Linux的操作系统，Kenel版本是2.6.8.9，用到的Uboot版本是1.1.6。

1.2 主要功能8M86机芯的接口功能配置如下：A.2路AV输入，1组分量，3路HDMI，1路VGA。

B.3路音频输入，其中1组AV，1组AV2和分量共用，1路VGA。

C.1组AV输出，1路重低音输出，1路数字音频输出。

D.2路 USB输入（其中1路可以用于软件升级），2路MIC麦克风输入，1路RJ45网络输入。

本机芯具有网络酷开功能，除具备酷K功能外，还具备本地酷开功能和网络酷开功能，本地酷开支持USB播放酷影、音乐相册（音乐、图片、文本），网络酷开功能支持“在线酷影”可以通过网络实时点播电影：“下载搜索”可以在网上搜索视频节目并下载到本地USB设备；“网上邻居”酷影播放局域网中电脑上共享的媒体文本。

本机芯为数模一体机，支持 DMB-T标准，可接收并解调DVB-C数字信号，通过插入CAM卡可以支持各个CA厂商的CA系统。

1.3 主要技术规格1、支持ISP（在系统可编程）功能，同时支持USB升级功能。

2、内置32-bit RISC CPU。

3、TS流既可从文件读取，也可从TS输入口输入，其最大速率为108M/S。