MC100EP446FAR2G中文资料

© Semiconductor Components Industries, LLC, 2004October, 2004 − Rev. 131Publication Order Number:MC10EP195/DMC10EP195, MC100EP195

3.3V ECL Programmable

Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC)designed primarily for clock deskewing and timing adjustment. Itprovides variable delay of a differential NECL/PECL input transition.The delay section consists of a programmable matrix of gates andmultiplexers as shown in the logic diagram, Figure 2. The delayincrement of the EP195 has a digitally selectable resolution of about10 ps and a net range of up to 10.2 ns. The required delay is selected bythe 10 data select inputs D[9:0] values and controlled by the LEN(pin 10). A LOW level on LEN allows a transparent LOAD mode ofreal time delay values by D[9:0]. A LOW to HIGH transition on LENwill LOCK and HOLD current values present against any subsequentchanges in D[10:0]. The approximate delay values for varying tapnumbers correlating to D0 (LSB) through D9 (MSB) are shown inTable 6 and Figure 3.Because the EP195 is designed using a chain of multiplexers it has afixed minimum delay of 2.2 ns. An additional pin D10 is provided forcontrolling Pins 14 and 15, CASCADE and CASCADE, also latchedby LEN, in cascading multiple PDCs for increased programmablerange. The cascade logic allows full control of multiple PDCs.Switching devices from all “1” states on D[0:9] with SETMAX LOWto all “0” states on D[0:9] with SETMAX HIGH will increase thedelay equivalent to “D0”, the minimum increment.Select input pins D[10:0] may be threshold controlled bycombinations of interconnects between VEF (pin 7) and VCF (pin 8)for LVCMOS, ECL, or LVTTL level signals. For LVCMOS inputlevels, leave VCF and VEF open. For ECL operation, short VCF andVEF (pins 7 and 8). For LVTTL level operation, connect a 1.5 Vsupply reference to VCF and leave open VEF pin. The 1.5 V referencevoltage to VCF pin can be accomplished by placing a 2.2 kW resistorbetween VCF and VEE for a 3.3 V power supply.The VBB pin, an internally generated voltage supply, is available tothis device only. For single-ended input conditions, the unuseddifferential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBBand VCC via a 0.01 mF capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.•Maximum Input Clock Frequency >1.2 GHz Typical•Programmable Range: 0 ns to 10 ns•Delay Range: 2.2 ns to 12.2 ns•10 ps Increments•PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V•NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V•Open Input Default State•Safety Clamp on Inputs•A Logic High on the EN Pin Will Force Q to LogicLow•D[10:0] Can Accept Either ECL, LVCMOS, or LVTTLInputs•VBB Output Reference Voltage

MC100ES6039Rev 2, 06/2005Freescale SemiconductorTechnical Data

© Freescale Semiconductor, Inc., 2005. All rights reserved.3.3 V ECL/PECL/HSTL/LVDS ÷2/4,

÷4/6 Clock Generation Chip

The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device.The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.The 100ES Series contains temperature compensation.

© Semiconductor Components Industries, LLC, 2006December, 2006 − Rev. 51Publication Order Number:MC100LVEL16/DMC100LVEL16

3.3V󰀁ECL Differential

Receiver

DescriptionThe MC100LVEL16 is a differential receiver. The device isfunctionally equivalent to the EL16 device, operating from a 3.3 Vsupply. The LVEL16 exhibits a wider VIHCMR range than its EL16counterpart. With output transition times and propagation delayscomparable to the EL16 the LVEL16 is ideally suited for interfacingwith high frequency sources at 3.3 V supplies.Under open input conditions, the Q input will be pulled down to VEEand the Q input will be biased to VCC/2. This condition will force theQ output low.The VBB pin, an internally generated voltage supply, is available tothis device only. For single-ended input conditions, the unuseddifferential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBBand VCC via a 0.01 mF capacitor and limit current sourcing or sinkingto 0.5 mA. When not used, VBB should be left open.

MOTOROLASEMICONDUCTOR TECHNICAL DATA

3–1REV 2© Motorola, Inc. 199612/93Differential Clock D FlipĆFlop

The MC10EL/100EL51 is a differential clock D flip-flop with reset. Thedevice is functionally similar to the E151 device with higher performancecapabilities. With propagation delays and output transition timessignificantly faster than the E151 the EL51 is ideally suited for thoseapplications which require the ultimate in AC performance.The reset input is an asynchronous, level triggered signal. Data entersthe master portion of the flip-flop when the clock is LOW and istransferred to the slave, and thus the outputs, upon a positive transition ofthe clock. The differential clock inputs of the EL51 allow the device to beused as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability underopen input (pulled down to VEE) conditions.