The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.©1996Document No. M12263EJAV0DS00 (10th edition)Date Published February 2000 NS CP(K)Printed in JapanThe mark • shows major revised points.DescriptionThe MC-458CB64ESB and MC-458CB64PSB are 8,388,608 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on which 4 pieces of 128M SDRAM: µPD45128163 are assembled.These modules provide high density and large quantities of memory in a small space without utilizing the surface-mounting technology on the printed circuit board.Decoupling capacitors are mounted on power supply line for noise reduction.Features• 8,388,608 words by 64 bits organization • Clock frequency and access time from CLKPart number/CAS LatencyClock frequencyAccess time from CLK(MAX.)(MIN.)MC-458CB64ESB-A10BCL = 3100 MHz 7 ns CL = 267 MHz 8 ns MC-458CB64PSB-A10B CL = 3100 MHz 7 ns CL = 267 MHz8 ns• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface• Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 and BA1 (Bank Select)• Programmable burst-length (1, 2, 4, 8 and Full Page)• Programmable wrap sequence (Sequential / Interleave)• Programmable /CAS latency (2, 3)• Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • Single +3.3 V ± 0.3 V power supply • LVTTL compatible • 4,096 refresh cycles/64 ms• Burst termination by Burst Stop command and Precharge command • 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)• Unbuffered type • Serial PD5Data Sheet M12263EJAV0DS002Ordering InformationPart numberClock frequency MHz (MAX.)PackageMounted devicesMC-458CB64ESB-A10B100 MHz144-pin Small Outline DIMM (Socket Type)Edge connector: Gold plated4 pieces of µPD45128163G5 (Rev. E)(10.16mm (400) TSOP (II))MC-458CB64PSB-A10B 100 MHz 25.4 mm height4 pieces of µPD45128163G5 (Rev. P)(10.16mm (400) TSOP (II))5Pin Configuration144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)/xxx indicates active low signal.A0 - A11:Address Inputs[Row: A0 - A11, Column: A0 - A8]BA0(A13), BA1(A12):SDRAM Bank SelectDQ0 - DQ63:Data Inputs/OutputsCLK0, CLK1:Clock InputCKE0:Clock Enable Input/CS0:Chip Select Input/RAS:Row Address Strobe/CAS:Column Address Strobe/WE:Write EnableDQMB0 - DQMB7:DQ Mask EnableSDA:Serial Data I/O for PDSCL:Clock Input for PDV CC:Power SupplyV SS:GroundNC:No ConnectionData Sheet M12263EJAV0DS003Data Sheet M12263EJAV0DS004Block Diagram/WE /CS0A0 - A11A0 - A11 : D0 - D3SCLSDADQMB0DQMB1DQMB2DQMB3/RAS /RAS : D0 - D3/CAS /CAS : D0 - D3CKE0CKE : D0 - D3BA0A13 : D0 - D3V CC D0 - D3D0 - D3V SSBA1A12 : D0 - D3CLK110pFRemark D0 - D3: µPD45128163 (2M words × 16 bits × 4 banks)5Electrical Specifications•All voltages are referenced to V SS (GND).•After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved.Absolute Maximum RatingsParameter Symbol Condition Rating Unit Voltage on power supply pin relative to GND V CC–0.5 to +4.6V Voltage on input pin relative to GND V T–0.5 to +4.6V Short circuit output current I O50mA Power dissipation P D4W Operating ambient temperature T A0 to +70°C Storage temperature T stg–55 to +125°C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limitsdescribed in the operational section of this specification. Exposure to Absolute Maximum Ratingconditions for extended periods may affect device reliability.Recommended Operating ConditionsParameter Symbol Condition MIN.TYP.MAX.Unit Supply voltage V CC 3.0 3.3 3.6V High level input voltage V IH 2.0V CC +0.3V Low level input voltage V IL–0.3+0.8V Operating ambient temperature T A070°CCapacitance (T A = 25°C, f = 1 MHz)Parameter Symbol Test condition MIN.TYP.MAX.Unit30pF Input capacitance C I1A0 - A11, BA0 (A13), BA1 (A12),/RAS, /CAS, /WEC I2CLK030C I3CKE030C I4/CS030C I5DQMB0 -DQMB710Data input/output capacitance C I/O DQ0 - DQ6310pFData Sheet M12263EJAV0DS005DC Characteristics (Recommended Operating Conditions unless otherwise noted)Parameter Symbol Test condition MIN.MAX.Unit Notes Operating current I CC1Burst length=1, t RC ≥t RC(MIN.)/CAS latency = 2440mA1I O = 0mA/CAS latency = 3440Precharge standby current I CC2P CKE ≤ V IL(MAX.), t CK =15ns4mA5in power down mode I CC2PS CKE ≤ V IL(MAX.), t CK =∞4Precharge standby current I CC2N CKE≥V IH(MIN.), t CK =15ns, /CS≥V IH(MIN.),80mAin non power down mode Input signals are changed one time during 30ns.I CC2NS CKE ≥ V IH(MIN.), t CK =∞, Input signals are stable.32Active standby current in I CC3P CKE ≤ V IL(MAX.), t CK =15ns20mApower down mode I CC3PS CKE ≤ V IL(MAX.), t CK =∞16Active standby current in I CC3N CKE≥V IH(MIN.), t CK =15ns, /CS≥V IH(MIN.),120mAnon power down mode Input signals are changed one time during 30ns.I CC3NS CKE ≥ V IH(MIN.), t CK =∞, Input signals are stable.80Operating current I CC4t CK ≥t CK(MIN.) , I O = 0mA/CAS latency = 2400mA2 (Burst mode)/CAS latency = 3560CBR (Auto) refresh current I CC5t RC ≥t RC(MIN.)/CAS latency = 2880mA3/CAS latency = 3880 Self refresh current I CC6CKE ≤ 0.2V8mAInput leakage current I I(L)V I=0 to 3.6V,All other pins not under test =0 V–4+4µAOutput leakage current I O(L)D OUT is disabled, V O =0 to 3.6V–1.5+1.5µAHigh level output voltage V OH I O =–4.0mA 2.4VLow level output voltage V OL I O =+4.0mA0.4VNotes 1.I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during t CK(MIN.).2.I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Inaddition to this, I CC4 is measured on condition that addresses are changed only one time during t CK(MIN.).3.I CC5 is measured on condition that addresses are changed only one time during t CK(MIN.).6Data Sheet M12263EJAV0DS00AC Characteristics (Recommended Operating Conditions unless otherwise noted)Test ConditionsParameter Value Unit AC high level input voltage / low level input voltage 2.4 / 0.4V Input timing measurement reference level 1.4VTransition time (Input rise and fall time)1nsOutput timing measurement reference level 1.4V2.4 V1.4 V0.4 VCLK2.4 V1.4 V0.4 VInputOutput5Data Sheet M12263EJAV0DS007Data Sheet M12263EJAV0DS008MIN.MAX.Clock cycle time/CAS latency = 3t CK310ns /CAS latency = 2t CK215ns Access time from CLK/CAS latency = 3t AC37ns 1/CAS latency = 2t AC28ns 1CLK high level width t CH 3.5ns CLK low level width t CL 3.5ns Data-out hold timet OH 3ns 1Data-out low-impedance time t LZ 0ns Data-out high-impedance time/CAS latency = 3t HZ337ns /CAS latency = 2t HZ238ns Data-in setup time t DS 2.5ns Data-in hold time t DH 1ns Address setup time t AS 2.5ns Address hold time t AH 1ns CKE setup time t CKS 2.5ns CKE hold timet CKH 1ns CKE setup time (Power down exit)t CKSP 2.5ns Command (/CS0, /RAS, /CAS, /WE,DQMB0 - DQMB7) setup time t CMS2.5nsCommand (/CS0, /RAS, /CAS, /WE,DQMB0 - DQMB7) hold timet CMH1nsNote 1. Output loadOutput50 pFMIN.MAX.REF to REF/ACT command period t RC90nsACT to PRE command period t RAS60120,000nsPRE to ACT command period t RP30nsDelay time ACT to READ/WRITE command t RCD30nsACT(0) to ACT(1) command period t RRD20nsData-in to PRE command period t DPL10nsData-in to ACT(REF) command/CAS latency = 3t DAL31CLK+30nsperiod (Auto precharge)/CAS latency = 2t DAL21CLK+30nsMode register set cycle time t RSC2CLKTransition time t T130nsRefresh time (4,096 refresh cycles)t REF64msData Sheet M12263EJAV0DS009Serial PD(1/2) 5Byte No.Function Described Hex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes80H10000000128 bytes 0Defines the number of bytes written intoserial PD memory1Total number of bytes of serial PD memory08H00001000256 bytes 2Fundamental memory type04H00000100SDRAM 3Number of rows0CH0000110012 rows 4Number of columns09H000010019 columns 5Number of banks01H00000001 1 bank 6Data width40H010******* bits 7Data width (continued)00H0000000008Voltage interface01H00000001LVTTL 9CL = 3 Cycle time-A10B A0H1010000010 ns 10CL =3 Access time-A10B70H011100007 ns11DIMM configuration type00H00000000Non-parity 12Refresh rate/type80H10000000Normal 13SDRAM width10H00010000×1614Error checking SDRAM width00H00000000None 15Minimum clock delay01H00000001 1 clock 16Burst length supported8FH100011111, 2, 4, 8, F 17Number of banks on each SDRAM04H00000100 4 banks 18/CAS latency supported06H000001102, 319/CS latency supported01H00000001020/WE latency supported01H00000001021SDRAM module attributes00H0000000022SDRAM device attributes: General0EH0000111023CL = 2 Cycle time-A10B F0H1111000015 ns 24CL = 2 Access time-A10B80H100000008 ns 25-2600H0000000027t RP(MIN.)-A10B1EH0001111030 ns 28t RRD(MIN.)-A10B14H0001010020 ns 29t RCD(MIN.)-A10B1EH0001111030 ns 30t RAS(MIN.)-A10B3CH0011110060 ns10Data Sheet M12263EJAV0DS00(2/2) Byte No.Function Described Hex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 31Module bank density10H0001000064 M bytes-A10B25H00100101 2.5 ns 32Command and address signal setuptime-A10B10H00010000 1 ns 33Command and address signal holdtime34Data signal input setup time-A10B25H00100101 2.5 ns 35Data signal input hold time-A10B10H00010000 1 ns36-6100H0000000062SPD revision-A10B12H00010010 1.2 63Checksum for bytes 0 – 62B5H1011010164-71Manufacture’s JEDEC ID code72Manufacturing location73-90Manufacture’s P/N91-92Revision code93-94Manufacturing date95-98Assembly serial number99-125Mfg specific126Intel specification frequency-A10B66H0110011066 MHz-A10B06H00000110 127Intel specification /CAS latencysupportTiming ChartRefer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).Data Sheet M12263EJAV0DS0011Data Sheet M12263EJAV0DS0012Package Drawing144 PIN DUAL IN-LINE MODULE (SOCKET TYPE)M144S-80A10R 4.0±0.10S 1.8T 1.0±0.1U1 3.2 MIN.U2 4.0 MIN.V 0.25 MAX.W 0.6±0.05Y2.0 MIN.φ5Data Sheet M12263EJAV0DS001314Data Sheet M12263EJAV0DS00Data Sheet M12263EJAV0DS0015CAUTION FOR HANDLING MEMORY MODULESWhen handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them.When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.• The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual propertyrights of third parties by or arising from use of a device described herein or any other liability arising from useof such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or otherintellectual property rights of NEC Corporation or others.• Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits,software, and information in the design of the customer's equipment shall be done under the full responsibilityof the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons orproperty arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.• NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on acustomer designated "quality assurance program" for a specific application. The recommended applications ofa device depend on its quality grade, as indicated below. Customers must check the quality grade of each devicebefore using it in a particular application.Standard: Computers, office equipment, communications equipment, test and measurement equipment,audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robotsSpecial: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.M7 98. 8。
