DC介绍

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INDEXv1999.10Design Compiler User Guide1Introduction to Design Compiler1Design Compiler is the core of the Synopsys synthesis softwareproducts. It provides constraint-driven optimization and supports awide range of design styles. The Design Compiler tools synthesizeyourHDLdescriptionintoatechnology-dependent,gate-leveldesign.Design Compiler optimizes combinational or sequential designs forspeed, area, and power, and supports both flat and hierarchicaldesigns.Figure 1-1Design Compiler OverviewVHDL SourceVerilog SourceOther Input FormatsVHDL CompilerHDL CompilercompileDesign CompilerMapped,Technology-Dependent Netlist/1-2HOMECONTENTS

INDEXv1999.10Design Compiler User GuideDesignCompilerprovideslinkstoelectronicdesignautomation(EDA)tools, such as place and route tools, and post layout resynthesistechniques, such as in-place optimization. These EDA tool linksenable sharing of information (such as forward-directed constraintsand delays) between Design Compiler and external tools.This chapter includes the following sections:•Design Compiler Products•User Interfaces•Supported File Formats•Supported File Formats•License Requirements•Resource Requirements•High-Level Design FlowDesign Compiler ProductsSynopsysprovidesaspectrumofDesignCompilerproducts,whichvaryinthecomplexityofthefeaturesoffered.Choosetherightproductforyourdesignenvironment,basedonyoursynthesisrequirements.Using the Design Compiler products, you can•Producefast,area-efficientASICdesignsbyusinguser-specifiedgate-array, FPGA, or standard-cell libraries•Translate designs from one technology to another/1-3HOMECONTENTS

INDEXv1999.10Design Compiler User Guide•Explore design tradeoffs involving design constraints such astiming,area,andpowerundervariousloading,temperature,andvoltage conditions•Synthesize and optimize a finite state machine, includingautomatic state assignment and state minimization•Integrate netlist input and netlist or schematic output into third-party environments while still supporting delay information andplace and route constraints•Create and partition hierarchical schematics automaticallyThe Design Compiler products include•DC Professional•DC Expert•DC ExpertPlus•DC Ultra•DC Ultra PlusFigure1-2showstherelationshipbetweenthefeaturesintheDesignCompiler products./1-4HOMECONTENTS

INDEXv1999.10Design Compiler User GuideFigure 1-2Design Compiler ProductsThe following sections describe these products.DC ProfessionalThe DC Professional tools are applied to typical ASIC designs thatemployCMOStechnology.Thesedesignscanutilizemultipleclocks;however,theclocksmusthavethesamefrequency.DCProfessionaldoes not support time borrowing for latch-based designs.ThesetoffeaturesprovidedintheDCProfessionalproductcomprisethecoresynthesisfeatures.ThesefeaturesareavailableinallDesignCompiler products.The core synthesis features include•Hierarchical compile (top-down or bottom-up)•Full and incremental compile techniquesDC UltraDC ExpertPlusDC Ultra PlusDC ExpertProfessionalDC/1-5HOMECONTENTS

INDEXv1999.10Design Compiler User Guide•Sequential optimization for complex flip-flops and latches•I/O pad insertion and optimization•Finite state machine (FSM) optimization•Buffer balancing (within a hierarchical block)DC ExpertThe DC Expert tools are applied to high-performance ASIC and ICdesigns.In addition to the core synthesis features, DC Expert provides thefollowing features:•Multifrequency clocks•Time borrowing for latch-based designs•Critical path resynthesis•Retiming for minimum clock period•In-place optimization•Specification of both minimum and maximum constraints foroptimization and timing analysis•Synthesis of control logic and certain data-path and structuredlogic•Modeling of multiple paths that share a startpoint and endpointbut have different timing requirements/1-6HOMECONTENTS

INDEXv1999.10Design Compiler User GuideDC ExpertPlusTheDCExpertPlustoolsareappliedtohigh-performanceASICandIC designs that utilize scan test techniques.In addition to the DC Expert features, DC ExpertPlus providesintegrated design-for-test capabilities, including constraint-drivenscan insertion during compile.DC UltraTheDCUltratoolsareappliedtohigh-performancedeepsubmicronASICandICdesigns,wheremaximumcontrolovertheoptimizationprocess is required.InadditiontotheDCExpertfeatures,DCUltraprovidesthefollowingfeatures:•Additional high-effort delay minimization algorithms•Support for the cell-degradation design rule•Additional options for theset_cost_priority command•Fineroptimizationcontrolwiththeset_compile_directivescommand•Additional options forreport_timing•Support for behavioral optimization of arithmetic (BOA)•Support for behavioral retiming (BRT)/1-7HOMECONTENTS