Buffered Routing Tree Construction Under Buffer Placement
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BufferedRoutingTreeConstructionUnderBufferPlacement
Blockages
Abstract
Interconnectdelayhasbecomeacriticalfactorin
determiningtheperformanceofintegratedcircuits.Routing
andbufferingarepowerfulmeansofimprovingthecircuit
speedandcorrectingthetimingviolationsafterglobal
placement.Thisreportpresentsapractical,dynamic-
programmingbasedalgorithmforperformingnettopology
constructionandbufferinsertionandsizingsimultaneously
underthegivenbufferplacementblockages.Thedifferences
fromsomepreviousworksarethat(1)thebufferlocations
arenotpre-determined,(2)themulti-pinnetsareeasily
handledand(3)aline-searchbasedroutingalgorithmis
implementedtospeeduptheprocess.Someheuristicsare
usedtoreducetheproblemcomplexity.Theseheuristics
includelimitingthenumberofintermediatesolutionsthatwe
keep,usingacontinuousbuffersizingmethod,andrestricting
thebufferlocationsalongtheHanangraph.Thisalgorithm
wasappliedtoanumberofrealindustrialdesignsand
achievedanaverageof7.9%delayimprovementcomparedto
theconventionaldesignflowbasedonsequentialnettopology
constructionfollowedbybuffering.
1Introduction
Timingoptimizationhasbeenachallengingproblemindeep
sub-micron(DSM)designs.Withtherapiddecreaseindevice
sizes,resistanceperunitlengthininterconnectsisrising.At
thesametime,globalwiresarelengtheningwhilechipsizes
increase.Thesetwofactorsmakeinterconnectdelayplayan
increasinglyimportantroleindeterminingcircuit
performance.Manyoptimizationtechniqueshavebeen
developedtoreduceinterconnectdelays.Thesetechniques
include,forexample,logicrestructuringandoptimization,
wirerouting,gatesizing,andbufferinsertion.Amongthese
techniques,globalroutingandbuffersizingstandoutasthe
mosteffectivemeansofreducinginterconnectdelay.
Conventionaldesignflowproceedsasfollows:first,net
topologyisdeterminedbyconstructingaSteinertreeora
shortestpathroutingtree,thenbuffersareinsertedintothis
topologyandsized.In[1],adynamicprogramming-based
algorithmforinsertingandsizingbuffersintoagivennet
topologyisproposed.Theobjectiveistomaximizethe
requiredarrivaltimeattheoutputpinofthedriverofthenet.
Thistechniquehasproventobequiteeffectivewhenthe
insertedbufferscanbeplacedanywhereonthechiplayout.
However,inrealitytherearemanyplacementblockagesin
thecircuit,whichrestricttheareasonthechipwherethe
bufferscanbeplaced.Theseblockagesoccur,forexample,
becauseoftheexistenceofpre-designedcoresand,moregenerally,macro-cells.Noticethattheseblockagesare
placementblockages,notroutingones.Thus,wires(while
perhapsnotusingallpossiblelayers)cangothroughthese
blockages.Thealgorithmof[1]doesnotperformwellinsuch
circumstances,andhenceanewalgorithmmustbedeveloped
thattakesplacementblockagesintoaccount.Thenew
algorithmmustperformnettopologydesignandbuffer
insertionsimultaneously;otherwise,theexistenceofafixed,a
prioritopologythatmaygothroughplacementblockageswill
greatlylimittheeffectivenessofthesubsequentbuffer
insertionstep.
BlockageSinkSource(a)(b)(c)
Figure1.Anexampleofawirebufferwithaplacement
blockageproblem.
AsmallexampleisdepictedinFigure1.Thesource,sinkpins,
andplacementblockagesareshowninFigure1(a).Usinga
conventionaltoolflow,theglobalrouter,whichconsidersall
theplacementblockagesasrouting-availablespaces,will
constructaSteinertreenettopologyasshowninFigure1(b).
Theflowingwirebufferingtoolcannotinsertbuffersforthis
net,sinceitisblockedbytheblockagealmostcompletely.
Anotherchoiceistospecifythattheplacementblockagesare
alsoroutingblockages.Theglobalroutercangoaroundallthe
blockages,andthefollowingwirebufferingprocesscaninsert
buffersonthenet,asshowninFigure1(c).However,forthe
leftsink,anet,whichgoesthroughtheverticalblockageand
connectsthesinktothesource,isactuallyabettersolution.
Theoptimalsolutioncanbeachievedbyouralgorithm,as
evidencedinthefinalresultshowninFigure8.
Furthermore,theASICdesignflowaffectsthetechniqueused
tofindthesolutionaswell.Inordertoimprovecircuittiming
orformanyotherreasons,buffersareinsertedmultipletimes
atdifferentdesignstages.Thispost-layoutbufferinsertionwill
influencecircuitplacementandotherissues,suchas
congestion.Todealwiththeseproblems,therearesomesmall
differencesindiversedesignflows.Insomedesignsbuffer
stations,whichareblankspaceslargeenoughforseveral
buffers,aredistributedthroughoutthelayoutarea.Throughout
thedesignprocessbuffersareonlyplacedinthesebuffer
stations.Asaresult,thelayoutchangesarelimitedtothese
stationareas.Insomeotherdesigns,therearenobuffer
stations.Thebuffersareplacedattheoptimallocations.Gate
overlapping,congestion,andotherviolationsareresolvedby
thestepsthatfollowthebufferplacement.Obviously,thefirst