DS90C363/DS90CF364+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD)Link—65MHz,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD)Link—65MHzGeneral DescriptionThe DS90C363transmitter converts 21bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling)data streams.A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.Every cycle of the transmit clock 21bits of input data are sampled and transmitted.The DS90CF364receiver converts the LVDS data streams back into 21bits of CMOS/TTL data.At a transmit clock frequency of 65MHz,18bits of RGB data and 3bits of LCD timing and control data (FPLINE,FPFRAME,DRDY)are transmitted at a rate of 455Mbps per LVDS data ing a 65MHz clock,the data through-puts is 170Mbytes/sec.The Transmitter is offered with pro-grammable edge data strobes for convenient interface with a variety of graphics controllers.The Transmitter can be pro-grammed for Rising edge strobe or Falling edge strobe through a dedicated pin.A Rising edge Transmitter will inter-operate with a Falling edge Receiver (DS90CF364)without any translation logic.This chipset is an ideal means to solve EMI and cable size problems associated with wide,high speed TTL interfaces.Featuresn 20to 65MHz shift clock supportn Programmable Transmitter (DS90C363)strobe select (Rising or Falling edge strobe)n Single 3.3V supplyn Chipset (Tx +Rx)power consumption <250mW (typ)n Power-down mode (<0.5mW total)n Single pixel per clock XGA (1024x768)readyn Supports VGA,SVGA,XGA and higher addressability.n Up to 170Megabyte/sec bandwidth n Up to 1.3Gbps throughputn Narrow bus reduces cable size and cost n 290mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 48-lead TSSOP package n Falling edge data strobe Receivern Compatible with TIA/EIA-644LVDS standard n ESD rating >7kVn Operating Temperature:−40˚C to +85˚CBlock DiagramsTRI-STATE ®is a registered trademark of National Semiconductor Corporation.ApplicationDS012886-14September 1999DS90C363/DS90CF364+3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD)Link —65MHz©1999National Semiconductor Corporation Block Diagrams(Continued)DS90C363DS012886-1Order Number DS90C363MTDSee NS Package Number MTD48DS90CF364DS012886-24Order Number DS90CF364MTDSee NS Package Number MTD482Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)−0.3V to+4V CMOS/TTL Input Voltage−0.3V to(V CC+0.3V) CMOS/TTL Output Voltage−0.3V to(V CC+0.3V) LVDS Receiver Input Voltage−0.3V to(V CC+0.3V) LVDS Driver Output Voltage−0.3V to(V CC+0.3V) LVDS Output Short CircuitDuration Continuous Junction Temperature+150˚C Storage Temperature−65˚C to+150˚C Lead Temperature(Soldering,4sec)+260˚C Maximum Package Power Dissipation Capacity25˚CMTD48(TSSOP)Package:DS90C363 1.98W DS90CF364 1.89W Package Derating:DS90C36316mW/˚C above+25˚C DS90CF36415mW/˚C above+25˚C ESD Rating(HBM,1.5kΩ,100pF)>7kV Recommended Operating ConditionsMin Nom Max Units Supply Voltage(V CC) 3.0 3.3 3.6V Operating Free AirTemperature(T A)−40+25+85˚C Receiver Input Range0 2.4V Supply Noise Voltage(V CC)100mV PPElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified.Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONSV IH High Level Input Voltage 2.0V CC V V IL Low Level Input Voltage GND0.8V V OH High Level Output Voltage I OH=−0.4mA 2.7 3.3V V OL Low Level Output Voltage I OL=2mA0.060.3V V CL Input Clamp Voltage I CL=−18mA−0.79−1.5V I IN Input Current V IN=V CC,GND,2.5V or0.4V±5.1±10µA I OS Output Short Circuit Current V OUT=0V−60−120mA LVDS DC SPECIFICATIONSV OD Differential Output Voltage R L=100Ω250345450mV ∆V OD Change in V OD between35mV complimentary output statesV OS Offset Voltage(Note4) 1.125 1.25 1.375V ∆V OS Change in V OS between35mV complimentary output statesI OS Output Short Circuit Current V OUT=0V,R L=100Ω−3.5−5mA I OZ Output TRI-STATE®Current PWR DWN=0V,±1±10µAV OUT=0V or V CCV TH Differential Input High Threshold V CM=+1.2V+100mV V TL Differential Input Low Threshold−100mV I IN Input Current V IN=+2.4V,V CC=3.6V±10µAV IN=0V,V CC=3.6V±10µA TRANSMITTER SUPPLY CURRENTICCTW Transmitter Supply Current,Worst Case R L=100Ω,C L=5pF,WorstCase Pattern(Figures1,3),T A=−40˚C to+85˚Cf=32.5MHz3145mAf=37.5MHz3250mAf=65MHz4255mAICCTG Transmitter Supply Current,16Grayscale R L=100Ω,C L=5pF,16Grayscale Pattern(Figures2,3),T A=−40˚C to+85˚Cf=32.5MHz2335mAf=37.5MHz2840mAf=65MHz3145mA 3Electrical Characteristics(Continued)Over recommended operating supply and temperature ranges unless otherwise specified.Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENTICCTZ Transmitter Supply Current PWR DWN=Low1055µA Power Down Driver Outputs in TRI-STATE®underPower Down ModeRECEIVER SUPPLY CURRENTICCRW Receiver Supply Current,WorstCase C L=8pF,WorstCase Pattern(Figures1,4),T A=−40˚C to+85˚Cf=32.5MHz4965mAf=37.5MHz5370mAf=65MHz78105mAICCRG Receiver Supply Current,16Grayscale C L=8pF,16Grayscale Pattern(Figures2,4),T A=−40˚C to+85˚Cf=32.5MHz2845mAf=37.5MHz3047mAf=65MHz4360mAICCRZ Receiver Supply Current PWR DWN=Low1055µA Power Down Receiver Outputs Stay Low duringPower Down ModeNote1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the device should be operated at these limits.The tables of“Electrical Characteristics”specify conditions for device operation.Note2:Typical values are given for V CC=3.3V and T A=+25C.Note3:Current into device pins is defined as positive.Current out of device pins is defined as negative.Voltages are referenced to ground unless otherwise speci-fied(except V OD and∆V OD).Note4:V OS previously referred as V CM.4Transmitter Switching CharacteristicsOver recommended operating supply and−40˚C to+85˚C ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time(Figure3)0.75 1.5ns LHLT LVDS High-to-Low Transition Time(Figure3)0.75 1.5ns TCIT TxCLK IN Transition Time(Figure5)5ns TCCS TxOUT Channel-to-Channel Skew(Figure6)250ps TPPos0Transmitter Output Pulse Position for Bit0f=65MHz−0.400.3ns (Figure17)TPPos1Transmitter Output Pulse Position for Bit1 1.8 2.2 2.5ns TPPos2Transmitter Output Pulse Position for Bit2 4.0 4.4 4.7ns TPPos3Transmitter Output Pulse Position for Bit3 6.2 6.6 6.9ns TPPos4Transmitter Output Pulse Position for Bit48.48.89.1ns TPPos5Transmitter Output Pulse Position for Bit510.611.011.3ns TPPos6Transmitter Output Pulse Position for Bit612.813.213.5ns TCIP TxCLK IN Period(Figure7)15T50ns TCIH TxCLK IN High Time(Figure7)0.35T0.5T0.65T ns TCIL TxCLK IN Low Time(Figure7)0.35T0.5T0.65T ns TSTC TxIN Setup to TxCLK IN(Figure7)f=65MHz 2.5ns THTC TxIN Hold to TxCLK IN(Figure7)0ns TCCD TxCLK IN to TxCLK OUT Delay25˚C,V CC=3.3V(Figure9) 3.0 3.7 5.5ns TPLLS Transmitter Phase Lock Loop Set(Figure11)10ms TPDD Transmitter Power Down Delay(Figure15)100ns5Receiver Switching CharacteristicsOver recommended operating supply and−40˚C to+85˚C ranges unless otherwise specifiedSymbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time(Figure4) 2.2 5.0ns CHLT CMOS/TTL High-to-Low Transition Time(Figure4) 2.2 5.0ns RSPos0Receiver Input Strobe Position for Bit0(Figure18)f=65MHz0.7 1.1 1.4ns RSPos1Receiver Input Strobe Position for Bit1 2.9 3.3 3.6ns RSPos2Receiver Input Strobe Position for Bit2 5.1 5.5 5.8ns RSPos3Receiver Input Strobe Position for Bit37.37.78.0ns RSPos4Receiver Input Strobe Position for Bit49.59.910.2ns RSPos5Receiver Input Strobe Position for Bit511.712.112.4ns RSPos6Receiver Input Strobe Position for Bit613.914.314.6ns RSKM RxIN Skew Margin(Note5)(Figure19)f=65MHz400ps RCOP RxCLK OUT Period(Figure8)15T50ns RCOH RxCLK OUT High Time(Figure8)f=65MHz7.38.6ns RCOL RxCLK OUT Low Time(Figure8)f=65MHz 3.45 4.9ns RSRC RxOUT Setup to RxCLK OUT(Figure8)f=65MHz 2.5 6.9ns RHRC RxOUT Hold to RxCLK OUT(Figure8)f=65MHz 2.5 5.7ns RCCD RxCLK IN to RxCLK OUT Delay25˚C,V CC=3.3V(Figure10) 5.07.19.0ns RPLLS Receiver Phase Lock Loop Set(Figure12)10ms RPDD Receiver Power Down Delay(Figure16)1µs Note5:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.This margin takes into account the transmitter pulse positions(min and max)and the receiver input setup and hold time(internal data sampling window-RSPos).This margin allows for LVDS interconnect skew,inter-symbol inter-ference(both dependent on type/length of cable),and clock jitter(less than250ps).AC Timing DiagramsDS012886-2FIGURE1.“Worst Case”Test Pattern6AC Timing Diagrams(Continued)Note 6:The worst case test pattern produces a maximum toggling of digital circuits,LVDS I/O and CMOS/TTL I/O.Note 7:The 16grayscale test pattern tests device power consumption for a “typical”LCD display pattern.The test pattern approximates signal switching needed to produce groups of 16vertical stripes across the display.Note 8:Figures 1,2show a falling edge data strobe (TxCLK IN/RxCLK OUT).Note 9:Recommended pin to signal mapping.Customer may choose to define differently.DS012886-3FIGURE 2.“16Grayscale”Test Pattern (Notes 6,7,8,9)DS012886-15FIGURE 3.DS90C363(Transmitter)LVDS Output Load and Transition TimesDS012886-4FIGURE 4.DS90CF364(Receiver)CMOS/TTL Output Load and Transition TimesDS012886-16FIGURE 5.DS90C363(Transmitter)Input Clock Transition Time7AC Timing Diagrams(Continued)DS012886-17Measurements at Vdiff=0VTCCS measured between earliest and latest LVDS edgesTxCLK Differential Low→High EdgeFIGURE6.DS90C363(Transmitter)Channel-to-Channel SkewDS012886-18FIGURE7.DS90C363(Transmitter)Setup/Hold and High/Low TimesDS012886-5FIGURE8.DS90CF364(Receiver)Setup/Hold and High/Low TimesDS012886-19FIGURE9.DS90C363(Transmitter)Clock In to Clock Out Delay(Falling Edge Strobe) 8AC Timing Diagrams(Continued)DS012886-6FIGURE10.DS90CF364(Receiver)Clock In to Clock Out DelayDS012886-20FIGURE11.DS90C363(Transmitter)Phase Lock Loop Set TimeDS012886-7FIGURE12.DS90CF364(Receiver)Phase Lock Loop Set Time9AC Timing Diagrams(Continued)DS012886-9FIGURE13.Seven Bits of LVDS in One Clock CycleDS012886-10FIGURE14.21Parallel TTL Data Inputs Mapped to LVDS OutputsDS012886-21FIGURE15.Transmitter Power Down DelayDS012886-8FIGURE16.Receiver Power Down Delay10AC Timing Diagrams(Continued)DS012886-22FIGURE17.Transmitter LVDS Output Pulse Position Measurement11AC Timing Diagrams(Continued)DS012886-25FIGURE18.Receiver LVDS Input Strobe Position12AC Timing Diagrams(Continued)DS90C363Pin Description—FPD Link TransmitterPin Name I/O No.DescriptionTxIN I 21TTL level input.This includes:6Red,6Green,6Blue,and 3control lines —FPLINE,FPFRAME and DRDY (also referred to as HSYNC,VSYNC,Data Enable).TxOUT+O 3Positive LVDS differentiaI data output.TxOUT−O 3Negative LVDS differential data output.FPSHIFT IN I 1TTL Ievel clock input.The falling edge acts as data strobe.Pin name TxCLK IN.R_FBI 1Programmable strobe select.RTxCLK OUT+O 1Positive LVDS differential clock output.TxCLK OUT−O 1Negative LVDS differential clock output.PWR DWN I 1TTL level input.When asserted (low input)TRI-STATES the outputs,ensuring low current at power down.V CC I 3Power supply pins for TTL inputs.GND I 4Ground pins for TTL inputs.PLL V CC I 1Power supply pin for PLL.PLL GND I 2Ground pins for PLL.LVDS V CC I 1Power supply pin for LVDS outputs.LVDS GNDI3Ground pins for LVDS outputs.DS012886-11C —Setup and Hold Time (Internal data sampling window)defined by Rspos (receiver input strobe position)min and max Tppos —Transmitter output pulse position (min and max)RSKM =Cable Skew (type,length)+Source Clock Jitter (cycle to cycle)(Note 10)+ISI (Inter-symbol interference)(Note 11)Cable Skew —typically 10ps–40ps per foot,media dependent Note 10:Cycle-to-cycle jitter is less than 250ps at 65MHz.Note 11:ISI is dependent on interconnect length;may be zero.FIGURE 19.Receiver LVDS Input Skew Margin13DS90CF364Pin Description—FPD Link ReceiverPin Name I/O No.DescriptionRxIN+I3Positive LVDS differentiaI data inputs.RxIN−I3Negative LVDS differential data inputs.RxOUT O21TTL level data outputs.This includes:6Red,6Green,6Blue,and3control lines—FPLINE,FPFRAME,DRDY(also referred to as HSYNC,VSYNC,Data Enable).RxCLK IN+I1Positive LVDS differential clock input.RxCLK IN−I1Negative LVDS differential clock input.FPSHIFT OUT O1TTL Ievel clock output.The falling edge acts as data strobe.Pin name RxCLK OUT.PWR DWN I1TTL level input.When asserted(low input)the receiver outputs are low.V CC I4Power supply pins for TTL outputs.GND I5Ground pins for TTL outputs.PLL V CC I1Power supply for PLL.PLL GND I2Ground pin for PLL.LVDS V CC I1Power supply pin for LVDS inputs.LVDS GND I3Ground pins for LVDS inputs.Applications InformationThe DS90C363and DS90CF364are backward compatiblewith the existing5V FPD Link transmitter/receiver pair(DS90CF563and DS90CF564).To upgrade from a5V to a3.3V system the following must be addressed:1.Change5V power supply to3.3V.Provide this supply tothe V CC,LVDS V CC and PLL V CC of both the transmitterand receiver devices.This change may enable the re-moval of a5V supply from the system,and power maybe supplied from an existing3V power source.2.The DS90C363(transmitter)incorporates a rise/fallstrobe select pin.This select function is on pin14,for-merly a V CC connection on the5V products.When therise/fall strobe select pin is connected to V CC,the part isconfigured with a rising edge strobe.In a system cur-rently using a5V rising edge strobe transmitter(DS90CR563),no layout changes are required to ac-commodate the new rise/fall select pin on the 3.3Vtransmitter.The V CC signal may remain at pin14,andthe device will be configured with a rising edge strobe.When converting from a5V falling edge transmitter(DS90CF563)to the3V transmitter a minimal boardlayout change is necessary.The3.3V transmitter willnot be configured with a falling edge strobe if V CC re-mains connected to the select pin.To guarantee the3.3V transmitter functions with a falling edge strobe pin14should be connected to ground OR left unconnected.When not connected(left open)and internal pull-downresistor ties pin14to ground,thus configuring the trans-mitter with a falling edge strobe.3.The DS90C363transmitter input and control inputs ac-cept3.3V TTL/CMOS levels.They are not5V tolerant.14Pin DiagramTABLE 1.Programmable Transmitter Pin Condition Strobe Status R_FB R_FB =V CC Rising edge strobe R_FBR_FB =GNDFalling edge strobeDS90C363DS012886-23DS90CF364DS012886-1315Physical Dimensions inches(millimeters)unless otherwise notedLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices orsystems which,(a)are intended for surgical implantinto the body,or(b)support or sustain life,andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling,can be reasonably expected to result in asignificant injury to the user.2.A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system,or to affect itssafety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507 48-Lead Molded Thin Shrink Small Outline Package,JEDECDimensions show in millimetersOrder Number DS90C363MTD and DS90CF364MTDNS Package Number MTD48DS9C363/DS9CF364+3.3VProgrammableLVDS18-Bit-ColorFlatPanelDisplay(FPD)Link—65MHzNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。
3 手动数据输入定位3.1简单加工操作的程序编写和执行手动数据输入操作方式特别适用于简单加工操作和刀具的预定位。
该方式能使您用HEIDENHAIN对话式编程方法或者用ISO格式编写一段短程序并立即执行它。
您也能够调用TNC循环。
程序储存在＄MDI文件中。
再用MDI定位的操作方式中，辅助状态显示也能被激活。
手动数据输入定位（MDI）选择操作的MDI定位方式，按您的要求编写程序文件＄MDI。
按下机床START按钮，开始程序运行。
限制不能使用FK任意轮廓编程、图形编程和程序运行图形。
＄MDI文件不得包含程序调用命令（PGMCALL）。
例1：在一个工件上钻一个深度为20mm的孔。
当工件被夹紧并校准好、设置好座标原点以后，您即可开始编制几行程序并进行钻孔操作。
首先，在L程序块中把刀具预定位在孔中心座标上方，距工件表面5mm。
然后可以用循环1 PECKING（啄式钻孔）进行钻孔操作。
0 BEGIN PGM $MDI MM1 TOOL DEF 1 L+0 R+52 TOOL CALL 1 Z 520003 L Z+200 RO F MAX4 L X+50 Y+50 RO F MAX M35 L Z+5 F 20006 CYCL DEF 1.0 PECKING7 CYCL DEF 1.1 SET UP 58 CYCL DEF 1.2 DEPTH -20 定义刀具：零点刀具，半径5。
调用刀具：Z刀具轴线。
主轴转速，2000 rpm。
刀具缩回（F MAX=快速行程）。
刀具以快速行程移到孔上方。
主轴开。
刀具定位到孔上方5mm处。
定义PECKING循环。
设置刀具在孔上方的间隔。
309 CYCL DEF 1.2 PECKG 1010 CYCL DEF 1.4 DWELL 0.511 CYCL DEF 1.5 F 25012 CYCL CALL13 L Z+200 RO F MAX M214 END PGM ＄MDI MM直线功能程序块L（参阅126页“直线L”），啄式钻孔循环（参阅195页“啄式钻孔（循环1）”）。
MONOLITHIC TRIPLE FIXED DELAY LINE (SERIES 3D7303)FEATURES• All-silicon, low-power CMOS technology • TTL/CMOS compatible inputs and outputs • Vapor phase, IR and wave solderable • Auto-insertable (DIP pkg.)• Low ground bounce noise• Leading- and trailing-edge accuracy • Delay range: 10 through 500ns • Delay tolerance: 2% or 1.0ns• Temperature stability: ±3% typical (0C-70C)• Vdd stability: ±1% typical (4.75V-5.25V)• Minimum input pulse width: 20% of totaldelay• 14-pin DIP available as drop-in replacement forhybrid delay linesFUNCTIONAL DESCRIPTIONThe 3D7303 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched,independent delay lines. Delay values can range from 10ns through 500ns. The input is reproduced at the output without inversion,shifted in time as per the user-specified dash number. The 3D7303is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.The all-CMOS 3D7303 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It isoffered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.data delay devices, inc.®3PACKAGES87651234I1I2I3GNDVDD O1O2O33D7303M DIP3D7303H Gull-Wing(300 Mil)12348765I1I2I3GNDVDD O1O2O33D7303Z SOIC(150 Mil)1413121110981234567I1N/C I2N/C I3N/C GNDVDD N/C O1N/C O2N/C O33D7303DIP3D7303G Gull-Wing 3D7303K Unused pinsremoved (300 Mil)PIN DESCRIPTIONSI1Delay Line 1 Input I2Delay Line 2 Input I3Delay Line 3 Input O1Delay Line 1 Output O2Delay Line 2 Output O3Delay Line 3 Output VCC +5 Volts GND GroundN/CNo ConnectionTABLE 1: PART NUMBER SPECIFICATIONSPART NUMBER DELAY INPUT RESTRICTIONS DIP-83D7303M 3D7303H SOIC-83D7303Z DIP-143D73033D7303GDIP-143D7303K PER LINE (ns)Max Operating FrequencyAbsolute Max Oper. Freq.Min Operating Pulse WidthAbsolute Min Oper. P.W.-10-10-10-1010 ± 1.033.3 MHz 100.0 MHz 15.0 ns 5.0 ns -15-15-15-1515 ± 1.022.2 MHz 100.0 MHz 22.5 ns 5.0 ns -20-20-20-2020 ± 1.016.7 MHz 100.0 MHz 30.0 ns 5.0 ns -25-25-25-2525 ± 1.013.3 MHz 83.3 MHz 37.5 ns 6.0 ns -30-30-30-3030 ± 1.011.1 MHz 71.4 MHz 45.0 ns 7.0 ns -40-40-40-4040 ± 1.08.33 MHz 62.5 MHz 60.0 ns 8.0 ns -50-50-50-5050 ± 1.0 6.67 MHz 50.0 MHz 75.0 ns 10.0 ns -100-100-100-100100 ± 2.0 3.33 MHz 25.0 MHz 150.0 ns 20.0 ns -200-200-200-200200 ± 4.0 1.67 MHz 12.5 MHz 300.0 ns 40.0 ns -300-300-300-300300 ± 6.0 1.11 MHz 8.33 MHz 450.0 ns 60.0 ns -400-400-400-400400 ± 8.00.83 MHz 6.25 MHz 600.0 ns 80.0 ns -500-500-500-500500 ± 10.00.67 MHz5.00 MHz750.0 ns100.0 nsNOTE:Any delay between 10 and 500 ns not shown is also available.©1996 Data Delay DevicesAPPLICATION NOTESOPERATIONAL DESCRIPTIONThe 3D7303 triple delay line architecture isshown in Figure 1. The individual delay lines are composed of a number of delay cells connected in series. Each delay line produces at its output a replica of the signal present at its input, shifted in time. The delay lines are matched and share the same compensation signals, whichminimizes line-to-line delay deviations over temperature and supply voltage variations.INPUT SIGNAL CHARACTERISTICSThe Frequency and/or Pulse Width (high or low)of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating inputfrequency and a Minimum and an Absolute Minimum operating pulse width have been specified.OPERATING FREQUENCYThe Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.The Maximum Operating Frequencyspecification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency , the 3D7303 must be tested at the user operating frequency.Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. Theprogrammed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.OPERATING PULSE WIDTHThe Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can bereproduced, shifted in time at the device output,with acceptable pulse width distortion.The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width , the 3D7303 must be tested at the user operating pulse width.Therefore, to facilitate production and device identification, the part number will include aO1I1Delay Line Delay Line Delay LineO2I2O3I3Temp & VDD Compensation VDDGND Figure 1: 3D7303 Functional DiagramAPPLICATION NOTES (CONT’D)custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7303 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature.The thermal coefficient is reduced to 600PPM/C, which is equivalent to a variation , over the 0C-70C operating range, of ±3% from the room-temperature delay settings and/or 1.0ns, whichever is greater. The power supply coefficient is reduced, over the 4.75V-5.25V operating range, to ±1% of the delay settings at the nominal 5.0VDC power supply and/or 2.0ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred.DEVICE SPECIFICATIONSTABLE 2: ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage V DD-0.37.0VInput Pin Voltage V IN-0.3V DD+0.3VInput Pin Current I IN-1.0 1.0mA25CStorage Temperature T STRG-55150CLead Temperature T LEAD300C10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS(0C to 70C, 4.75V to 5.25V)PARAMETER SYMBOL MIN MAX UNITS NOTES Static Supply Current*I DD30mAHigh Level Input Voltage V IH 2.0VLow Level Input Voltage V IL0.8VHigh Level Input Current I IH1µA V IH = V DD Low Level Input Current I IL1µA V IL = 0V High Level Output Current I OH-4.0mA V DD = 4.75VV OH = 2.4V Low Level Output Current I OL 4.0mA V DD = 4.75VV OL = 0.4V Output Rise & Fall Time T R & T F2ns C LD = 5 pf*I DD(Dynamic) = 3 * C LD * V DD * F Input Capacitance = 10 pf typical where:C LD = Average capacitance load/line (pf)Output Load Capacitance (C LD) = 25 pf maxF = Input frequency (GHz)SILICON DELAY LINE AUTOMATED TESTINGTEST CONDITIONSINPUT:OUTPUT:Ambient Temperature:25o C ± 3o C R load :10K Ω ± 10%Supply Voltage (Vcc): 5.0V ± 0.1V C load :5pf ± 10%Input Pulse:High = 3.0V ± 0.1VThreshold:1.5V (Rising & Falling)Low = 0.0V ± 0.1VSource Impedance:50Ω Max.Rise/Fall Time: 3.0 ns Max. (measuredbetween 0.6V and 2.4V )Pulse Width:PW IN = 1.25 x Total Delay Period:PER IN = 2.5 x Total DelayNOTE:The above conditions are for test only and do not in any way restrict the operation of the device.10K Ω470Ω5pfDevice Under TestDigital ScopeFigure 2: Test SetupFigure 3: Timing Diagramt PLHt PHLPER INPW INt RISEt FALL0.6V0.6V1.5V 1.5V2.4V 2.4V 1.5V1.5VV IHV ILV OHV OLINPUT SIGNALOUTPUT SIGNAL。
